MCC'2023- Execution of r359-smll-167891808400058

About the Execution of LoLa+red for RobotManipulation-PT-00200

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
4446.548	3600000.00	225537.00	11239.50	???TTTT????TFFFF	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r359-smll-1
Waiting for the VM to be ready (probing ssh)
.............................................
.......................
.............................................
=============================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is RobotManipulation-PT-00200,
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r359-smll-1678918084000
======================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 408K
-rw-r--r-- 1 mcc users 6.3K Feb 26 05:33
-rw-r--r-- 1 mcc users 61K Feb 26 05:33
-rw-r--r-- 1 mcc users 5.7K Feb 26 05:32
-rw-r--r-- 1 mcc users 46K Feb 26 05:32
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41
-rw-r--r-- 1 mcc users 6.6K Jan 29 11:41
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:47
-rw-r--r-- 1 mcc users 25K Feb 25 16:47
-rw-r--r-- 1 mcc users 2.6K Feb 25 16:48
-rw-r--r-- 1 mcc users 17K Feb 25 16:48
-rw-r--r-- 1 mcc users 8.2K Feb 26 05:34
-rw-r--r-- 1 mcc users 74K Feb 26 05:34
-rw-r--r-- 1 mcc users 11K Feb 26 05:34
-rw-r--r-- 1 mcc users 78K Feb 26 05:34
-rw-r--r-- 1 mcc users 1.8K Feb 25 16:48
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:48
-rw-r--r-- 1 mcc users 6 Mar 5 18:23
-rw-r--r-- 1 mcc users 6 Mar 5 18:23
-rw-r--r-- 1 mcc users 6 Mar 5 18:23
-rw-r--r-- 1 mcc users 6.4K Mar 5 18:23

--------------------
content from stdout:

=== Data for post analysis generated

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the
FORMULA_NAME RobotManipulation-PT-00200-CTLFi
FORMULA_NAME RobotManipulation-PT-00200-CTLFi
FORMULA_NAME RobotManipulation-PT-00200-CTLFi
FORMULA_NAME RobotManipulation-PT-00200-CTLFi
FORMULA_NAME RobotManipulation-PT-00200-CTLFi
FORMULA_NAME RobotManipulation-PT-00200-CTLFi
FORMULA_NAME RobotManipulation-PT-00200-CTLFi
FORMULA_NAME RobotManipulation-PT-00200-CTLFi
FORMULA_NAME RobotManipulation-PT-00200-CTLFi
FORMULA_NAME RobotManipulation-PT-00200-CTLFi
FORMULA_NAME RobotManipulation-PT-00200-CTLFi
FORMULA_NAME RobotManipulation-PT-00200-CTLFi
FORMULA_NAME RobotManipulation-PT-00200-CTLFi
FORMULA_NAME RobotManipulation-PT-00200-CTLFi
FORMULA_NAME RobotManipulation-PT-00200-CTLFi
FORMULA_NAME RobotManipulation-PT-00200-CTLFi

=== Now, execution of the tool begins

BK_START 1678989999071

bash -c /home/mcc/BenchKit/BenchKit_head.sh
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RobotManipulation-PT-00200
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-16 18:06:42] [INFO ] Running
[2023-03-16 18:06:42] [INFO ] Parsing
[2023-03-16 18:06:42] [INFO ] Load
[2023-03-16 18:06:42] [INFO ] Transformed
[2023-03-16 18:06:42] [INFO ] Transformed
[2023-03-16 18:06:42] [INFO ] Parsed
Parsed 16 properties from file /home/mcc/exec
Support contains 15 out of 15 places.
Starting structural reductions in LTL
Applied a total of 0 rules in 19 ms.
// Phase 1: matrix 11 rows 15 cols
[2023-03-16 18:06:43] [INFO ] Computed
[2023-03-16 18:06:43] [INFO ] Implicit
[2023-03-16 18:06:43] [INFO ] Invariant
[2023-03-16 18:06:43] [INFO ] Implicit
Implicit Place search using SMT with
[2023-03-16 18:06:43] [INFO ] Invariant
[2023-03-16 18:06:43] [INFO ] Dead
Finished structural reductions in LTL
Support contains 15 out of 15 places
[2023-03-16 18:06:43] [INFO ] Flatten
[2023-03-16 18:06:43] [INFO ] Flatten
[2023-03-16 18:06:43] [INFO ] Input
Incomplete random walk after 10032
Finished Best-First random walk after 94
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Input
Computed a total of 0 stabilizing places
Starting structural reductions in LTL
Discarding 1 places :
Implicit places reduction removed 1 places
Iterating post reduction 0 with 1 rules
Applied a total of 1 rules in 3 ms.
Finished structural reductions in LTL
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Input
Starting structural reductions in LTL
Discarding 2 places :
Implicit places reduction removed 2 places
Iterating post reduction 0 with 2 rules
Applied a total of 2 rules in 2 ms.
Finished structural reductions in LTL
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Input
Starting structural reductions in LTL
Discarding 1 places :
Implicit places reduction removed 1 places
Iterating post reduction 0 with 1 rules
Applied a total of 1 rules in 2 ms.
Finished structural reductions in LTL
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Input
Starting structural reductions in LTL
Discarding 2 places :
Implicit places reduction removed 2 places
Iterating post reduction 0 with 2 rules
Applied a total of 2 rules in 2 ms.
Finished structural reductions in LTL
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Input
Starting structural reductions in LTL
Discarding 2 places :
Implicit places reduction removed 2 places
Iterating post reduction 0 with 2 rules
Applied a total of 2 rules in 1 ms.
Finished structural reductions in LTL
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Input
Starting structural reductions in SI_CTL
Discarding 1 places :
Implicit places reduction removed 1 places
Iterating post reduction 0 with 1 rules
Applied a total of 1 rules in 6 ms.
Finished structural reductions in SI_CTL
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Input
Starting structural reductions in LTL
Discarding 2 places :
Implicit places reduction removed 2 places
Iterating post reduction 0 with 2 rules
Applied a total of 2 rules in 1 ms.
Finished structural reductions in LTL
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Input
Starting structural reductions in SI_CTL
Discarding 1 places :
Implicit places reduction removed 1 places
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1
Performed 1 trivial Post agglomeration.
Iterating post reduction 0 with 2 rules
Reduce places removed 1 places and 0
Performed 1 Post agglomeration using
Iterating post reduction 1 with 2 rules
Reduce places removed 1 places and 0
Iterating post reduction 2 with 1 rules
Applied a total of 5 rules in 9 ms.
Finished structural reductions in SI_CTL
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Input
Starting structural reductions in LTL
Discarding 2 places :
Implicit places reduction removed 2 places
Iterating post reduction 0 with 2 rules
Applied a total of 2 rules in 1 ms.
Finished structural reductions in LTL
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Input
Starting structural reductions in SI_CTL
Discarding 2 places :
Implicit places reduction removed 2 places
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded 3
Performed 3 trivial Post agglomeration.
Iterating post reduction 0 with 5 rules
Reduce places removed 3 places and 0
Iterating post reduction 1 with 3 rules
Performed 2 Post agglomeration using
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0
Iterating global reduction 2 with 4
Applied a total of 12 rules in 4 ms.
Finished structural reductions in SI_CTL
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Input
Starting structural reductions in LTL
Applied a total of 0 rules in 1 ms.
Finished structural reductions in LTL
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Input
Starting structural reductions in SI_CTL
Discarding 1 places :
Implicit places reduction removed 1 places
Iterating post reduction 0 with 1 rules
Applied a total of 1 rules in 3 ms.
Finished structural reductions in SI_CTL
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Input
Starting structural reductions in LTL
Discarding 1 places :
Implicit places reduction removed 1 places
Iterating post reduction 0 with 1 rules
Applied a total of 1 rules in 1 ms.
Finished structural reductions in LTL
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Input
Starting structural reductions in LTL
Applied a total of 0 rules in 0 ms.
Finished structural reductions in LTL
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Input
Starting structural reductions in LTL
Discarding 1 places :
Implicit places reduction removed 1 places
Iterating post reduction 0 with 1 rules
Applied a total of 1 rules in 1 ms.
Finished structural reductions in LTL
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Input
Starting structural reductions in LTL
Discarding 1 places :
Implicit places reduction removed 1 places
Iterating post reduction 0 with 1 rules
Applied a total of 1 rules in 1 ms.
Finished structural reductions in LTL
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Input
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Flatten
[2023-03-16 18:06:44] [INFO ] Export
[2023-03-16 18:06:44] [INFO ] Export
Total runtime 1793 ms.
There are residual formulas that ITS
starting LoLA
BK_INPUT RobotManipulation-PT-00200
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../red
current directory: /home/mcc/execution/372
CTLFireability

FORMULA RobotManipulation-PT-00200-CTLFireability-06

FORMULA RobotManipulation-PT-00200-CTLFireability-15

FORMULA RobotManipulation-PT-00200-CTLFireability-14

FORMULA RobotManipulation-PT-00200-CTLFireability-13

FORMULA RobotManipulation-PT-00200-CTLFireability-04

FORMULA RobotManipulation-PT-00200-CTLFireability-12

FORMULA RobotManipulation-PT-00200-CTLFireability-11

FORMULA RobotManipulation-PT-00200-CTLFireability-03

FORMULA RobotManipulation-PT-00200-CTLFireability-05
TIME LIMIT: Killed by timeout after
MemTotal: 16393216 kB
MemFree: 11707668 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16103500 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstoo
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pyli
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/i
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin/
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/
lola: reading pnml
lola: PNML file contains place/transition
lola: finished parsing
lola: closed net file /home/mcc/execution/3
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execut
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 28 (type CNST)
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 28 (type CNST)
lola: result : false
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: LAUNCH task # 96 (type EXCL)
lola: time limit : 92 sec
lola: memory limit: 32 pages
lola: FINISHED task # 96 (type EXCL)
lola: result : false
lola: markings : 401
lola: fired transitions : 400
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 43 (type EXCL)
lola: time limit : 97 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: rewrite Frontend/Parser/formula_rewri
lola: LAUNCH task # 103 (type FNDP)
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 104 (type EQUN)
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewri
lola: LAUNCH task # 106 (type SRCH)
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewri
lola: FINISHED task # 106 (type SRCH)
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 103 (type FNDP)
lola: result : true
lola: fired transitions : 400
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 104 (type EQUN)
lola: FINISHED task # 104 (type EQUN)
lola: result : unknown
FINISHED FORMULA: CATEGORY

PENDING FORMULAS: CATEGORY
RobotManipulation-PT-00200-CTLFireability-00:
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RobotManipulation-PT-00200-CTLFireability-07:
RobotManipulation-PT-00200-CTLFireability-08:
RobotManipulation-PT-00200-CTLFireability-09: AGEFAG
RobotManipulation-PT-00200-CTLFireability-10:
RobotManipulation-PT-00200-CTLFireability-11:
RobotManipulation-PT-00200-CTLFireability-12:
RobotManipulation-PT-00200-CTLFireability-13:
RobotManipulation-PT-00200-CTLFireability-14:
RobotManipulation-PT-00200-CTLFireability-15:

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RobotManipulation-PT-00200-CTLFireability-09: AGEFAG
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======================== examination is CTLFireability 58 =============================== CTLCardinality.txt CTLCardinality.xml CTLFireability.txt CTLFireability.xml GenericPropertiesDefinition.xml GenericPropertiesVerdict.xml LTLCardinality.txt LTLCardinality.xml LTLFireability.txt LTLFireability.xml ReachabilityCardinality.txt ReachabilityCardinality.xml ReachabilityFireability.txt ReachabilityFireability.xml UpperBounds.txt UpperBounds.xml equiv_col instance iscolored model.pnml by BenchKit (invocation template) result vector(from text file) reability-00 reability-01 reability-02 reability-03 reability-04 reability-05 reability-06 reability-07 reability-08 reability-09 reability-10 reability-11 reability-12 reability-13 reability-14 reability-15 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML] pnml file : /home/mcc/execution/model.pnml time of PNML (sax parser for PT used): 44 ms 15 places. 11 transitions. PT model containing 15 places and 11 transitions and 34 arcs in 179 ms. ution/CTLFireability.xml in 24 ms. Attempting structural reductions. mode, iteration 0 : 15/15 places, 11/11 transitions. Remains 15 /15 variables (removed 0) and now considering 11/11 (removed 0) transitions. 6 place invariants in 7 ms Places using invariants in 233 ms returned [] cache hit. Places using invariants and state equation in 67 ms returned [] State Equation took 361 ms to find 0 implicit places. cache hit. Transitions using invariants and state equation in 60 ms found 0 transitions. mode , in 1 iterations and 445 ms. Remains : 15/15 places, 11/11 transitions. after structural reductions. gal took : 30 ms gal took : 10 ms system was already deterministic with 11 transitions. steps, including 2 resets, run finished after 60 ms. (steps per millisecond=167 ) properties (out of 29) seen :26 steps, including 0 resets, run visited all 3 properties in 4 ms. (steps per millisecond=23 ) gal took : 5 ms gal took : 6 ms system was already deterministic with 11 transitions. and 0 stable transitions mode, iteration 0 : 15/15 places, 11/11 transitions. applied. Total rules applied 1 place count 14 transition count 11 Remains 14 /15 variables (removed 1) and now considering 11/11 (removed 0) transitions. mode , in 1 iterations and 3 ms. Remains : 14/15 places, 11/11 transitions. gal took : 3 ms gal took : 2 ms system was already deterministic with 11 transitions. mode, iteration 0 : 15/15 places, 11/11 transitions. applied. Total rules applied 2 place count 13 transition count 11 Remains 13 /15 variables (removed 2) and now considering 11/11 (removed 0) transitions. mode , in 1 iterations and 2 ms. Remains : 13/15 places, 11/11 transitions. gal took : 2 ms gal took : 2 ms system was already deterministic with 11 transitions. mode, iteration 0 : 15/15 places, 11/11 transitions. applied. Total rules applied 1 place count 14 transition count 11 Remains 14 /15 variables (removed 1) and now considering 11/11 (removed 0) transitions. mode , in 1 iterations and 2 ms. Remains : 14/15 places, 11/11 transitions. gal took : 3 ms gal took : 3 ms system was already deterministic with 11 transitions. mode, iteration 0 : 15/15 places, 11/11 transitions. applied. Total rules applied 2 place count 13 transition count 11 Remains 13 /15 variables (removed 2) and now considering 11/11 (removed 0) transitions. mode , in 1 iterations and 2 ms. Remains : 13/15 places, 11/11 transitions. gal took : 3 ms gal took : 3 ms system was already deterministic with 11 transitions. mode, iteration 0 : 15/15 places, 11/11 transitions. applied. Total rules applied 2 place count 13 transition count 11 Remains 13 /15 variables (removed 2) and now considering 11/11 (removed 0) transitions. mode , in 1 iterations and 1 ms. Remains : 13/15 places, 11/11 transitions. gal took : 2 ms gal took : 2 ms system was already deterministic with 11 transitions. mode, iteration 0 : 15/15 places, 11/11 transitions. applied. Total rules applied 1 place count 14 transition count 11 Remains 14 /15 variables (removed 1) and now considering 11/11 (removed 0) transitions. mode , in 1 iterations and 6 ms. Remains : 14/15 places, 11/11 transitions. gal took : 3 ms gal took : 3 ms system was already deterministic with 11 transitions. mode, iteration 0 : 15/15 places, 11/11 transitions. applied. Total rules applied 2 place count 13 transition count 11 Remains 13 /15 variables (removed 2) and now considering 11/11 (removed 0) transitions. mode , in 1 iterations and 1 ms. Remains : 13/15 places, 11/11 transitions. gal took : 2 ms gal took : 2 ms system was already deterministic with 11 transitions. mode, iteration 0 : 15/15 places, 11/11 transitions. transitions Transition count delta: 1 applied. Total rules applied 2 place count 14 transition count 10 transitions. F-continuation condition.Transition count delta: 1 applied. Total rules applied 4 place count 13 transition count 9 transitions. applied. Total rules applied 5 place count 12 transition count 9 Remains 12 /15 variables (removed 3) and now considering 9/11 (removed 2) transitions. mode , in 1 iterations and 9 ms. Remains : 12/15 places, 9/11 transitions. gal took : 2 ms gal took : 1 ms system was already deterministic with 9 transitions. mode, iteration 0 : 15/15 places, 11/11 transitions. applied. Total rules applied 2 place count 13 transition count 11 Remains 13 /15 variables (removed 2) and now considering 11/11 (removed 0) transitions. mode , in 1 iterations and 1 ms. Remains : 13/15 places, 11/11 transitions. gal took : 2 ms gal took : 1 ms system was already deterministic with 11 transitions. mode, iteration 0 : 15/15 places, 11/11 transitions. transitions Transition count delta: 3 applied. Total rules applied 5 place count 13 transition count 8 transitions. applied. Total rules applied 8 place count 10 transition count 8 F-continuation condition.Transition count delta: 2 transitions. rules applied. Total rules applied 12 place count 8 transition count 6 Remains 8 /15 variables (removed 7) and now considering 6/11 (removed 5) transitions. mode , in 1 iterations and 4 ms. Remains : 8/15 places, 6/11 transitions. gal took : 1 ms gal took : 1 ms system was already deterministic with 6 transitions. mode, iteration 0 : 15/15 places, 11/11 transitions. Remains 15 /15 variables (removed 0) and now considering 11/11 (removed 0) transitions. mode , in 1 iterations and 1 ms. Remains : 15/15 places, 11/11 transitions. gal took : 2 ms gal took : 3 ms system was already deterministic with 11 transitions. mode, iteration 0 : 15/15 places, 11/11 transitions. applied. Total rules applied 1 place count 14 transition count 11 Remains 14 /15 variables (removed 1) and now considering 11/11 (removed 0) transitions. mode , in 1 iterations and 3 ms. Remains : 14/15 places, 11/11 transitions. gal took : 2 ms gal took : 2 ms system was already deterministic with 11 transitions. mode, iteration 0 : 15/15 places, 11/11 transitions. applied. Total rules applied 1 place count 14 transition count 11 Remains 14 /15 variables (removed 1) and now considering 11/11 (removed 0) transitions. mode , in 1 iterations and 1 ms. Remains : 14/15 places, 11/11 transitions. gal took : 2 ms gal took : 2 ms system was already deterministic with 11 transitions. mode, iteration 0 : 15/15 places, 11/11 transitions. Remains 15 /15 variables (removed 0) and now considering 11/11 (removed 0) transitions. mode , in 1 iterations and 0 ms. Remains : 15/15 places, 11/11 transitions. gal took : 2 ms gal took : 2 ms system was already deterministic with 11 transitions. mode, iteration 0 : 15/15 places, 11/11 transitions. applied. Total rules applied 1 place count 14 transition count 11 Remains 14 /15 variables (removed 1) and now considering 11/11 (removed 0) transitions. mode , in 1 iterations and 1 ms. Remains : 14/15 places, 11/11 transitions. gal took : 2 ms gal took : 2 ms system was already deterministic with 11 transitions. mode, iteration 0 : 15/15 places, 11/11 transitions. applied. Total rules applied 1 place count 14 transition count 11 Remains 14 /15 variables (removed 1) and now considering 11/11 (removed 0) transitions. mode , in 1 iterations and 1 ms. Remains : 14/15 places, 11/11 transitions. gal took : 1 ms gal took : 1 ms system was already deterministic with 11 transitions. gal took : 24 ms gal took : 19 ms to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms. to PNML in file /home/mcc/execution/model.sr.pnml of net with 15 places, 11 transitions and 34 arcs took 1 ms. could not solve within timeout ucer/bin//../../lola/bin/ TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT 3600 seconds ls/pylibs bs tstools/pylibs: /pylibs: /../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar ../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML 372/model.pnml net 72/model.pnml ion/372/CTLFireability.xml te.k:451 te.k:322 te.k:334 te.k:296 te.k:469 te.k:478 te.k:472 te.k:463 te.k:415 te.k:147 te.k:296 te.k:322 te.k:328 te.k:296 te.k:325 te.k:337 te.k:296 te.k:296 te.k:250 te.k:250 te.k:250 te.k:550 te.k:550 te.k:550 te.k:550 te.k:550 te.k:550 te.k:322 te.k:337 te.k:296 te.k:296 te.k:325 te.k:337 te.k:296 te.k:296 te.k:250 places removed for 25 RobotManipulation-PT-00200-CTLFireability-07 for RobotManipulation-PT-00200-CTLFireability-07 te.k:749 te.k:787 te.k:807 te.k:811 te.k:813 te.k:814 te.k:809 te.k:813 for 25 RobotManipulation-PT-00200-CTLFireability-07 for RobotManipulation-PT-00200-CTLFireability-07 for 42 RobotManipulation-PT-00200-CTLFireability-10 te.k:754 te.k:787 te.k:753 te.k:787 te.k:814 te.k:812 te.k:811 te.k:811 te.k:806 te.k:806 te.k:813 te.k:807 te.k:812 te.k:753 te.k:787 te.k:746 te.k:787 te.k:754 te.k:787 te.k:811 te.k:808 te.k:810 te.k:815 te.k:807 te.k:811 te.k:806 te.k:808 te.k:812 te.k:808 te.k:812 te.k:812 te.k:812 te.k:808 te.k:807 te.k:807 te.k:813 te.k:812 te.k:813 te.k:811 te.k:808 te.k:814 te.k:813 te.k:807 te.k:809 te.k:814 te.k:814 te.k:813 te.k:815 te.k:813 te.k:806 te.k:809 te.k:808 te.k:811 te.k:813 te.k:806 te.k:813 te.k:808 te.k:814 te.k:808 te.k:812 te.k:807 te.k:813 te.k:806 te.k:813 te.k:814 te.k:809 te.k:813 te.k:806 te.k:811 te.k:811 te.k:809 te.k:811 te.k:814 te.k:809 te.k:811 te.k:806 te.k:812 te.k:813 te.k:812 te.k:721 te.k:787 te.k:721 te.k:787 te.k:721 te.k:787 for 18 RobotManipulation-PT-00200-CTLFireability-06 for 18 RobotManipulation-PT-00200-CTLFireability-06 te.k:721 for 18 RobotManipulation-PT-00200-CTLFireability-06 te.k:787 for RobotManipulation-PT-00200-CTLFireability-06 for RobotManipulation-PT-00200-CTLFireability-06 for RobotManipulation-PT-00200-CTLFireability-06 (obsolete) for RobotManipulation-PT-00200-CTLFireability-06 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 1 DISJ 0 1 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 10 0 0 10 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 RobotManipulation-PT-00200-CTLFireability-10 1249586 m, 249917 m/sec, 5778935 t fired, . VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 1 DISJ 0 1 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 10 0 0 10 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS RobotManipulation-PT-00200-CTLFireability-10 2294766 m, 209036 m/sec, 11065115 t fired, . VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 1 DISJ 0 1 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 10 0 0 10 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS RobotManipulation-PT-00200-CTLFireability-10 3260039 m, 193054 m/sec, 16175856 t fired, . VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 1 DISJ 0 1 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 10 0 0 10 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS RobotManipulation-PT-00200-CTLFireability-10 4199782 m, 187948 m/sec, 21213647 t fired, . VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 1 DISJ 0 1 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 10 0 0 10 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS RobotManipulation-PT-00200-CTLFireability-10 5075041 m, 175051 m/sec, 26007234 t fired, . VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 1 DISJ 0 1 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 10 0 0 10 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS RobotManipulation-PT-00200-CTLFireability-10 5950880 m, 175167 m/sec, 30797314 t fired, . VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 1 DISJ 0 1 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 10 0 0 10 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS RobotManipulation-PT-00200-CTLFireability-10 6806175 m, 171059 m/sec, 35530208 t fired, . VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 1 DISJ 0 1 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 10 0 0 10 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS RobotManipulation-PT-00200-CTLFireability-10 7654760 m, 169717 m/sec, 40255476 t fired, . for RobotManipulation-PT-00200-CTLFireability-10 (memory limit exceeded) VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 1 DISJ 0 1 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 10 0 0 10 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS for 18 RobotManipulation-PT-00200-CTLFireability-06 for RobotManipulation-PT-00200-CTLFireability-06 for 48 RobotManipulation-PT-00200-CTLFireability-12 for RobotManipulation-PT-00200-CTLFireability-12 for 93 RobotManipulation-PT-00200-CTLFireability-15 for RobotManipulation-PT-00200-CTLFireability-15 for 90 RobotManipulation-PT-00200-CTLFireability-14 for RobotManipulation-PT-00200-CTLFireability-14 for 87 RobotManipulation-PT-00200-CTLFireability-13 for RobotManipulation-PT-00200-CTLFireability-13 for 48 RobotManipulation-PT-00200-CTLFireability-12 for RobotManipulation-PT-00200-CTLFireability-12 for 36 RobotManipulation-PT-00200-CTLFireability-08 VALUE PRODUCED BY DISJ true state space /EXEG CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 12 0 0 7 MEM PG/PGLIMIT FORMULA STATUS RobotManipulation-PT-00200-CTLFireability-08 4690008 m, 938001 m/sec, 4936110 t fired, . for RobotManipulation-PT-00200-CTLFireability-08 (memory limit exceeded) VALUE PRODUCED BY DISJ true state space /EXEG CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 3 0 0 0 CTL 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 12 0 0 7 MEM PG/PGLIMIT FORMULA STATUS for 12 RobotManipulation-PT-00200-CTLFireability-04 for RobotManipulation-PT-00200-CTLFireability-04 for 3 RobotManipulation-PT-00200-CTLFireability-01 VALUE PRODUCED BY CTL true CTL model checker DISJ true state space /EXEG CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 3 0 0 0 CTL 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 12 0 0 7 MEM PG/PGLIMIT FORMULA STATUS 5/32 RobotManipulation-PT-00200-CTLFireability-01 1129201 m, 225840 m/sec, 5061007 t fired, . VALUE PRODUCED BY CTL true CTL model checker DISJ true state space /EXEG CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 3 0 0 0 CTL 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 12 0 0 7 MEM PG/PGLIMIT FORMULA STATUS 9/32 RobotManipulation-PT-00200-CTLFireability-01 2192746 m, 212709 m/sec, 10219121 t fired, . VALUE PRODUCED BY CTL true CTL model checker DISJ true state space /EXEG CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 3 0 0 0 CTL 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 12 0 0 7 MEM PG/PGLIMIT FORMULA STATUS RobotManipulation-PT-00200-CTLFireability-01 3159668 m, 193384 m/sec, 15084281 t fired, . VALUE PRODUCED BY CTL true CTL model checker DISJ true state space /EXEG CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 3 0 0 0 CTL 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 12 0 0 7 MEM PG/PGLIMIT FORMULA STATUS RobotManipulation-PT-00200-CTLFireability-01 4076768 m, 183420 m/sec, 19777260 t fired, . VALUE PRODUCED BY CTL true CTL model checker DISJ true state space /EXEG CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 3 0 0 0 CTL 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 12 0 0 7 MEM PG/PGLIMIT FORMULA STATUS RobotManipulation-PT-00200-CTLFireability-01 4958252 m, 176296 m/sec, 24345117 t fired, . VALUE PRODUCED BY CTL true CTL model checker DISJ true state space /EXEG CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 3 0 0 0 CTL 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 12 0 0 7 MEM PG/PGLIMIT FORMULA STATUS RobotManipulation-PT-00200-CTLFireability-01 5819633 m, 172276 m/sec, 28835946 t fired, . VALUE PRODUCED BY CTL true CTL model checker DISJ true state space /EXEG CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 3 0 0 0 CTL 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 12 0 0 7 MEM PG/PGLIMIT FORMULA STATUS RobotManipulation-PT-00200-CTLFireability-01 6653309 m, 166735 m/sec, 33217965 t fired, . VALUE PRODUCED BY CTL true CTL model checker DISJ true state space /EXEG CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 3 0 0 0 CTL 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 12 0 0 7 MEM PG/PGLIMIT FORMULA STATUS RobotManipulation-PT-00200-CTLFireability-01 7490153 m, 167368 m/sec, 37601928 t fired, . for RobotManipulation-PT-00200-CTLFireability-01 (memory limit exceeded) VALUE PRODUCED BY CTL true CTL model checker DISJ true state space /EXEG CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 3 0 0 0 CTL 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 12 0 0 7 MEM PG/PGLIMIT FORMULA STATUS for 0 RobotManipulation-PT-00200-CTLFireability-00 VALUE PRODUCED BY CTL true CTL model checker DISJ true state space /EXEG CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 3 0 0 0 CTL 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 12 0 0 7 MEM PG/PGLIMIT FORMULA STATUS RobotManipulation-PT-00200-CTLFireability-00 3195134 m, 639026 m/sec, 7024107 t fired, . VALUE PRODUCED BY CTL true CTL model checker DISJ true state space /EXEG CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 3 0 0 0 CTL 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 12 0 0 7 MEM PG/PGLIMIT FORMULA STATUS RobotManipulation-PT-00200-CTLFireability-00 5697888 m, 500550 m/sec, 13834847 t fired, . for RobotManipulation-PT-00200-CTLFireability-00 (memory limit exceeded) VALUE PRODUCED BY CTL true CTL model checker DISJ true state space /EXEG CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 3 0 0 0 CTL 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 12 0 0 7 MEM PG/PGLIMIT FORMULA STATUS for 39 RobotManipulation-PT-00200-CTLFireability-09 VALUE PRODUCED BY CTL true CTL model checker DISJ true state space /EXEG CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 3 0 0 0 CTL 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 12 0 0 7 MEM PG/PGLIMIT FORMULA STATUS 8/32 RobotManipulation-PT-00200-CTLFireability-09 2056669 m, 411333 m/sec, 5678159 t fired, . VALUE PRODUCED BY CTL true CTL model checker DISJ true state space /EXEG CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 3 0 0 0 CTL 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 12 0 0 7 MEM PG/PGLIMIT FORMULA STATUS RobotManipulation-PT-00200-CTLFireability-09 3552481 m, 299162 m/sec, 10692449 t fired, . VALUE PRODUCED BY CTL true CTL model checker DISJ true state space /EXEG CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 3 0 0 0 CTL 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 12 0 0 7 MEM PG/PGLIMIT FORMULA STATUS RobotManipulation-PT-00200-CTLFireability-09 4934042 m, 276312 m/sec, 15404857 t fired, . VALUE PRODUCED BY CTL true CTL model checker DISJ true state space /EXEG CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 3 0 0 0 CTL 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 12 0 0 7 MEM PG/PGLIMIT FORMULA STATUS RobotManipulation-PT-00200-CTLFireability-09 6244241 m, 262039 m/sec, 19948851 t fired, . VALUE PRODUCED BY CTL true CTL model checker DISJ true state space /EXEG CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 3 0 0 0 CTL 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 12 0 0 7 MEM PG/PGLIMIT FORMULA STATUS RobotManipulation-PT-00200-CTLFireability-09 7494354 m, 250022 m/sec, 24343759 t fired, . VALUE PRODUCED BY CTL true CTL model checker DISJ true state space /EXEG CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 3 0 0 0 CTL 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 12 0 0 7 MEM PG/PGLIMIT FORMULA STATUS RobotManipulation-PT-00200-CTLFireability-09 8725954 m, 246320 m/sec, 28671405 t fired, . for RobotManipulation-PT-00200-CTLFireability-09 (memory limit exceeded) VALUE PRODUCED BY CTL true CTL model checker DISJ true state space /EXEG CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 3 0 0 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 12 0 0 7 MEM PG/PGLIMIT FORMULA STATUS for 48 RobotManipulation-PT-00200-CTLFireability-12 for RobotManipulation-PT-00200-CTLFireability-12 for 45 RobotManipulation-PT-00200-CTLFireability-11 for RobotManipulation-PT-00200-CTLFireability-11 for 9 RobotManipulation-PT-00200-CTLFireability-03 for RobotManipulation-PT-00200-CTLFireability-03 for 25 RobotManipulation-PT-00200-CTLFireability-07 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 3 0 0 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS RobotManipulation-PT-00200-CTLFireability-07 5350027 m, 1070005 m/sec, 5575664 t fired, . for RobotManipulation-PT-00200-CTLFireability-07 (memory limit exceeded) VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS for 6 RobotManipulation-PT-00200-CTLFireability-02 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 RobotManipulation-PT-00200-CTLFireability-02 801198 m, 160239 m/sec, 5061340 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 RobotManipulation-PT-00200-CTLFireability-02 1565732 m, 152906 m/sec, 9970469 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS RobotManipulation-PT-00200-CTLFireability-02 2294560 m, 145765 m/sec, 14643884 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS RobotManipulation-PT-00200-CTLFireability-02 3008113 m, 142710 m/sec, 19219038 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS RobotManipulation-PT-00200-CTLFireability-02 3703721 m, 139121 m/sec, 23684467 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS RobotManipulation-PT-00200-CTLFireability-02 4387354 m, 136726 m/sec, 28073869 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS RobotManipulation-PT-00200-CTLFireability-02 5060969 m, 134723 m/sec, 32402392 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS RobotManipulation-PT-00200-CTLFireability-02 5731040 m, 134014 m/sec, 36706211 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS RobotManipulation-PT-00200-CTLFireability-02 6394566 m, 132705 m/sec, 40970238 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS RobotManipulation-PT-00200-CTLFireability-02 7051615 m, 131409 m/sec, 45193792 t fired, . for RobotManipulation-PT-00200-CTLFireability-02 (memory limit exceeded) VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS for 15 RobotManipulation-PT-00200-CTLFireability-05 for RobotManipulation-PT-00200-CTLFireability-05 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ true state space /EXEG CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL false CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 3 0 1 0 CTL 0 0 0 0 1 0 1 0 ======

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RobotManipulation-PT-00200"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is RobotManipulation-PT-00200, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r359-smll-167891808400058"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RobotManipulation-PT-00200.tgz
mv RobotManipulation-PT-00200 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;