fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r358-smll-167891807400194
Last Updated
May 14, 2023

About the Execution of LoLA for RwMutex-PT-r2000w0010

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16222.228 308962.00 411332.00 15020.60 F??T?T?T??F??T?T normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r358-smll-167891807400194.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is RwMutex-PT-r2000w0010, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r358-smll-167891807400194
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 4.9M
-rw-r--r-- 1 mcc users 8.0K Feb 25 22:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 90K Feb 25 22:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.5K Feb 25 22:47 CTLFireability.txt
-rw-r--r-- 1 mcc users 48K Feb 25 22:47 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 16:49 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Feb 25 16:49 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 16:49 LTLFireability.txt
-rw-r--r-- 1 mcc users 21K Feb 25 16:49 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 23:21 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 134K Feb 25 23:21 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 23:06 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 95K Feb 25 23:06 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:49 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:49 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 11 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 4.4M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-00
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-01
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-02
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-03
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-04
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-05
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-06
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-07
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-08
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-09
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-10
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-11
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-12
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-13
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-14
FORMULA_NAME RwMutex-PT-r2000w0010-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678980799358

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RwMutex-PT-r2000w0010
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT RwMutex-PT-r2000w0010
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA RwMutex-PT-r2000w0010-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r2000w0010-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r2000w0010-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r2000w0010-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r2000w0010-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r2000w0010-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r2000w0010-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678981108320

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: ASSUMEDDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 81 (type SKEL/SRCH) for 0 RwMutex-PT-r2000w0010-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 81 (type SKEL/SRCH) for RwMutex-PT-r2000w0010-CTLFireability-00
lola: result : true
lola: markings : 2
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 84 (type SKEL/FNDP) for 0 RwMutex-PT-r2000w0010-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 85 (type SKEL/EQUN) for 0 RwMutex-PT-r2000w0010-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 86 (type SKEL/SRCH) for 0 RwMutex-PT-r2000w0010-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 87 (type SKEL/SRCH) for 0 RwMutex-PT-r2000w0010-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: FINISHED task # 86 (type SKEL/SRCH) for RwMutex-PT-r2000w0010-CTLFireability-00
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 87 (type SKEL/SRCH) for RwMutex-PT-r2000w0010-CTLFireability-00
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 84 (type FNDP) for RwMutex-PT-r2000w0010-CTLFireability-00 (obsolete)
lola: CANCELED task # 85 (type EQUN) for RwMutex-PT-r2000w0010-CTLFireability-00 (obsolete)
lola: FINISHED task # 84 (type SKEL/FNDP) for RwMutex-PT-r2000w0010-CTLFireability-00
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/CTLFireability-85.sara.

lola: FINISHED task # 85 (type SKEL/EQUN) for RwMutex-PT-r2000w0010-CTLFireability-00
lola: result : true
lola: Created skeleton in 1.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 1.000000 secs.
lola: ASSUMEDDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 89 (type SKEL/SRCH) for 17 RwMutex-PT-r2000w0010-CTLFireability-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 89 (type SKEL/SRCH) for RwMutex-PT-r2000w0010-CTLFireability-03
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r2000w0010-CTLFireability-00: CONJ 0 0 0 0 6 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-05: DISJ 0 0 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-15: EG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 129 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 1.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 92 (type SKEL/FNDP) for 44 RwMutex-PT-r2000w0010-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 93 (type SKEL/EQUN) for 44 RwMutex-PT-r2000w0010-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 94 (type SKEL/SRCH) for 44 RwMutex-PT-r2000w0010-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 95 (type SKEL/SRCH) for 44 RwMutex-PT-r2000w0010-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 92 (type SKEL/FNDP) for RwMutex-PT-r2000w0010-CTLFireability-08
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 93 (type EQUN) for RwMutex-PT-r2000w0010-CTLFireability-08 (obsolete)
lola: CANCELED task # 94 (type SRCH) for RwMutex-PT-r2000w0010-CTLFireability-08 (obsolete)
lola: CANCELED task # 95 (type SRCH) for RwMutex-PT-r2000w0010-CTLFireability-08 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
sara: try reading problem file /home/mcc/execution/CTLFireability-93.sara.

lola: FINISHED task # 93 (type SKEL/EQUN) for RwMutex-PT-r2000w0010-CTLFireability-08
lola: result : true
lola: Created skeleton in 2.000000 secs.
lola: RELEASE
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 2.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

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lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:715
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r2000w0010-CTLFireability-00: CONJ false state space / EG
RwMutex-PT-r2000w0010-CTLFireability-03: CONJ true CONJ
RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-07: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
RwMutex-PT-r2000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-15: EG true state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r2000w0010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-08: DISJ 0 1 0 0 6 0 0 3
RwMutex-PT-r2000w0010-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 1/380 1/32 RwMutex-PT-r2000w0010-CTLFireability-09 1162 m, 232 m/sec, 5969 t fired, .

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RwMutex-PT-r2000w0010-CTLFireability-00: CONJ false state space / EG
RwMutex-PT-r2000w0010-CTLFireability-03: CONJ true CONJ
RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-07: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
RwMutex-PT-r2000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-15: EG true state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r2000w0010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-08: DISJ 0 1 0 0 6 0 0 3
RwMutex-PT-r2000w0010-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 6/380 2/32 RwMutex-PT-r2000w0010-CTLFireability-09 56750 m, 11117 m/sec, 417664 t fired, .

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RwMutex-PT-r2000w0010-CTLFireability-00: CONJ false state space / EG
RwMutex-PT-r2000w0010-CTLFireability-03: CONJ true CONJ
RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-07: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
RwMutex-PT-r2000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-15: EG true state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r2000w0010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-08: DISJ 0 1 0 0 6 0 0 3
RwMutex-PT-r2000w0010-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 11/380 3/32 RwMutex-PT-r2000w0010-CTLFireability-09 112093 m, 11068 m/sec, 853750 t fired, .

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RwMutex-PT-r2000w0010-CTLFireability-00: CONJ false state space / EG
RwMutex-PT-r2000w0010-CTLFireability-03: CONJ true CONJ
RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-07: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
RwMutex-PT-r2000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-15: EG true state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r2000w0010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-08: DISJ 0 1 0 0 6 0 0 3
RwMutex-PT-r2000w0010-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

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52 CTL EXCL 16/380 4/32 RwMutex-PT-r2000w0010-CTLFireability-09 167647 m, 11110 m/sec, 1292202 t fired, .

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RwMutex-PT-r2000w0010-CTLFireability-00: CONJ false state space / EG
RwMutex-PT-r2000w0010-CTLFireability-03: CONJ true CONJ
RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-07: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
RwMutex-PT-r2000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-15: EG true state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r2000w0010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-08: DISJ 0 1 0 0 6 0 0 3
RwMutex-PT-r2000w0010-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 21/380 5/32 RwMutex-PT-r2000w0010-CTLFireability-09 221347 m, 10740 m/sec, 1740442 t fired, .

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RwMutex-PT-r2000w0010-CTLFireability-00: CONJ false state space / EG
RwMutex-PT-r2000w0010-CTLFireability-03: CONJ true CONJ
RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-07: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
RwMutex-PT-r2000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-15: EG true state space / EG

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RwMutex-PT-r2000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-08: DISJ 0 1 0 0 6 0 0 3
RwMutex-PT-r2000w0010-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 26/380 6/32 RwMutex-PT-r2000w0010-CTLFireability-09 276279 m, 10986 m/sec, 2181663 t fired, .

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RwMutex-PT-r2000w0010-CTLFireability-00: CONJ false state space / EG
RwMutex-PT-r2000w0010-CTLFireability-03: CONJ true CONJ
RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-07: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
RwMutex-PT-r2000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-15: EG true state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r2000w0010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-08: DISJ 0 1 0 0 6 0 0 3
RwMutex-PT-r2000w0010-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 31/380 7/32 RwMutex-PT-r2000w0010-CTLFireability-09 330254 m, 10795 m/sec, 2626574 t fired, .

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RwMutex-PT-r2000w0010-CTLFireability-00: CONJ false state space / EG
RwMutex-PT-r2000w0010-CTLFireability-03: CONJ true CONJ
RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-07: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
RwMutex-PT-r2000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-15: EG true state space / EG

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RwMutex-PT-r2000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-08: DISJ 0 1 0 0 6 0 0 3
RwMutex-PT-r2000w0010-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 36/380 8/32 RwMutex-PT-r2000w0010-CTLFireability-09 384877 m, 10924 m/sec, 3068943 t fired, .

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RwMutex-PT-r2000w0010-CTLFireability-03: CONJ true CONJ
RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-07: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
RwMutex-PT-r2000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-15: EG true state space / EG

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RwMutex-PT-r2000w0010-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
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RwMutex-PT-r2000w0010-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

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52 CTL EXCL 41/380 9/32 RwMutex-PT-r2000w0010-CTLFireability-09 438884 m, 10801 m/sec, 3513873 t fired, .

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RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-07: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
RwMutex-PT-r2000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-15: EG true state space / EG

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RwMutex-PT-r2000w0010-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

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52 CTL EXCL 46/380 11/32 RwMutex-PT-r2000w0010-CTLFireability-09 492487 m, 10720 m/sec, 3959076 t fired, .

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RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-07: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
RwMutex-PT-r2000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-15: EG true state space / EG

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RwMutex-PT-r2000w0010-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

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52 CTL EXCL 51/380 12/32 RwMutex-PT-r2000w0010-CTLFireability-09 544685 m, 10439 m/sec, 4412344 t fired, .

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RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-07: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
RwMutex-PT-r2000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-15: EG true state space / EG

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RwMutex-PT-r2000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-08: DISJ 0 1 0 0 6 0 0 3
RwMutex-PT-r2000w0010-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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52 CTL EXCL 56/380 13/32 RwMutex-PT-r2000w0010-CTLFireability-09 596113 m, 10285 m/sec, 4863524 t fired, .

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RwMutex-PT-r2000w0010-CTLFireability-00: CONJ false state space / EG
RwMutex-PT-r2000w0010-CTLFireability-03: CONJ true CONJ
RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-07: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
RwMutex-PT-r2000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-15: EG true state space / EG

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RwMutex-PT-r2000w0010-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-08: DISJ 0 1 0 0 6 0 0 3
RwMutex-PT-r2000w0010-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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RwMutex-PT-r2000w0010-CTLFireability-03: CONJ true CONJ
RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-07: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
RwMutex-PT-r2000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-15: EG true state space / EG

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RwMutex-PT-r2000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-08: DISJ 0 1 0 0 6 0 0 3
RwMutex-PT-r2000w0010-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

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52 CTL EXCL 66/380 14/32 RwMutex-PT-r2000w0010-CTLFireability-09 645486 m, 6300 m/sec, 5280670 t fired, .

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RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-07: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
RwMutex-PT-r2000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-15: EG true state space / EG

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RwMutex-PT-r2000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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52 CTL EXCL 71/380 14/32 RwMutex-PT-r2000w0010-CTLFireability-09 654718 m, 1846 m/sec, 5364293 t fired, .

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RwMutex-PT-r2000w0010-CTLFireability-03: CONJ true CONJ
RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-07: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
RwMutex-PT-r2000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-15: EG true state space / EG

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RwMutex-PT-r2000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
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RwMutex-PT-r2000w0010-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-07: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
RwMutex-PT-r2000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-15: EG true state space / EG

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RwMutex-PT-r2000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

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52 CTL EXCL 81/380 15/32 RwMutex-PT-r2000w0010-CTLFireability-09 700538 m, 4950 m/sec, 5769252 t fired, .

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RwMutex-PT-r2000w0010-CTLFireability-03: CONJ true CONJ
RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-07: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
RwMutex-PT-r2000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-15: EG true state space / EG

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RwMutex-PT-r2000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-08: DISJ 0 1 0 0 6 0 0 3
RwMutex-PT-r2000w0010-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

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52 CTL EXCL 86/380 15/32 RwMutex-PT-r2000w0010-CTLFireability-09 715381 m, 2968 m/sec, 5893286 t fired, .

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RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-07: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
RwMutex-PT-r2000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-15: EG true state space / EG

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RwMutex-PT-r2000w0010-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

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RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-07: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
RwMutex-PT-r2000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-15: EG true state space / EG

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RwMutex-PT-r2000w0010-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
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RwMutex-PT-r2000w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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52 CTL EXCL 97/380 16/32 RwMutex-PT-r2000w0010-CTLFireability-09 760477 m, 2427 m/sec, 6251844 t fired, .

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RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-07: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
RwMutex-PT-r2000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-15: EG true state space / EG

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RwMutex-PT-r2000w0010-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-08: DISJ 0 1 0 0 6 0 0 3
RwMutex-PT-r2000w0010-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-07: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
RwMutex-PT-r2000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-15: EG true state space / EG

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RwMutex-PT-r2000w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-07: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
RwMutex-PT-r2000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-15: EG true state space / EG

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RwMutex-PT-r2000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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RwMutex-PT-r2000w0010-CTLFireability-05: DISJ true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-07: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-10: CONJ false state space /EFEG
RwMutex-PT-r2000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r2000w0010-CTLFireability-15: EG true state space / EG

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RwMutex-PT-r2000w0010-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-08: DISJ 0 1 0 0 6 0 0 3
RwMutex-PT-r2000w0010-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r2000w0010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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RwMutex-PT-r2000w0010-CTLFireability-00: CONJ false state space / EG
/home/mcc/BenchKit/bin//../lola/bin//../BenchKit_head.sh: line 63: 374 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RwMutex-PT-r2000w0010"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is RwMutex-PT-r2000w0010, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r358-smll-167891807400194"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RwMutex-PT-r2000w0010.tgz
mv RwMutex-PT-r2000w0010 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;