About the Execution of LoLa+red for ResAllocation-PT-R003C050
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 2675.067 | 456834.00 | 449248.00 | 1597.70 | TT??T??T???TT??? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r327-tall-167889200000714.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is ResAllocation-PT-R003C050, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r327-tall-167889200000714
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 816K
-rw-r--r-- 1 mcc users 8.3K Feb 25 15:20 CTLCardinality.txt
-rw-r--r-- 1 mcc users 91K Feb 25 15:20 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.8K Feb 25 15:20 CTLFireability.txt
-rw-r--r-- 1 mcc users 51K Feb 25 15:20 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 16:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.3K Feb 25 15:22 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 89K Feb 25 15:22 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.7K Feb 25 15:21 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 81K Feb 25 15:21 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 16:44 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:44 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 9 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 360K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-00
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-01
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-02
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-03
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-04
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-05
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-06
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-07
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-08
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-09
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-10
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-11
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-12
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-13
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-14
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679055219859
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ResAllocation-PT-R003C050
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-17 12:13:41] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-17 12:13:41] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-17 12:13:41] [INFO ] Load time of PNML (sax parser for PT used): 76 ms
[2023-03-17 12:13:41] [INFO ] Transformed 300 places.
[2023-03-17 12:13:41] [INFO ] Transformed 200 transitions.
[2023-03-17 12:13:41] [INFO ] Parsed PT model containing 300 places and 200 transitions and 894 arcs in 138 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 8 ms.
Support contains 166 out of 300 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 300/300 places, 200/200 transitions.
Applied a total of 0 rules in 16 ms. Remains 300 /300 variables (removed 0) and now considering 200/200 (removed 0) transitions.
// Phase 1: matrix 200 rows 300 cols
[2023-03-17 12:13:41] [INFO ] Computed 150 place invariants in 18 ms
[2023-03-17 12:13:41] [INFO ] Implicit Places using invariants in 299 ms returned [295, 297]
Discarding 2 places :
Implicit Place search using SMT only with invariants took 326 ms to find 2 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 298/300 places, 200/200 transitions.
Applied a total of 0 rules in 6 ms. Remains 298 /298 variables (removed 0) and now considering 200/200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 2 iterations and 348 ms. Remains : 298/300 places, 200/200 transitions.
Support contains 166 out of 298 places after structural reductions.
[2023-03-17 12:13:42] [INFO ] Flatten gal took : 47 ms
[2023-03-17 12:13:42] [INFO ] Flatten gal took : 31 ms
[2023-03-17 12:13:42] [INFO ] Input system was already deterministic with 200 transitions.
Support contains 158 out of 298 places (down from 166) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 94 resets, run finished after 483 ms. (steps per millisecond=20 ) properties (out of 73) seen :65
Incomplete Best-First random walk after 10001 steps, including 3 resets, run finished after 37 ms. (steps per millisecond=270 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 8) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 34 ms. (steps per millisecond=294 ) properties (out of 7) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=384 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 3 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 6) seen :1
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=384 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 3 resets, run finished after 30 ms. (steps per millisecond=333 ) properties (out of 5) seen :0
Running SMT prover for 5 properties.
// Phase 1: matrix 200 rows 298 cols
[2023-03-17 12:13:43] [INFO ] Computed 148 place invariants in 5 ms
[2023-03-17 12:13:43] [INFO ] [Real]Absence check using 148 positive place invariants in 20 ms returned sat
[2023-03-17 12:13:43] [INFO ] After 360ms SMT Verify possible using all constraints in real domain returned unsat :2 sat :0 real:3
[2023-03-17 12:13:43] [INFO ] [Nat]Absence check using 148 positive place invariants in 18 ms returned sat
[2023-03-17 12:13:43] [INFO ] After 110ms SMT Verify possible using state equation in natural domain returned unsat :2 sat :3
[2023-03-17 12:13:43] [INFO ] Deduced a trap composed of 4 places in 36 ms of which 4 ms to minimize.
[2023-03-17 12:13:43] [INFO ] Deduced a trap composed of 4 places in 30 ms of which 1 ms to minimize.
[2023-03-17 12:13:44] [INFO ] Deduced a trap composed of 4 places in 22 ms of which 1 ms to minimize.
[2023-03-17 12:13:44] [INFO ] Trap strengthening (SAT) tested/added 4/3 trap constraints in 132 ms
[2023-03-17 12:13:44] [INFO ] After 290ms SMT Verify possible using trap constraints in natural domain returned unsat :2 sat :3
Attempting to minimize the solution found.
Minimization took 31 ms.
[2023-03-17 12:13:44] [INFO ] After 425ms SMT Verify possible using all constraints in natural domain returned unsat :2 sat :3
Fused 5 Parikh solutions to 2 different solutions.
Parikh walk visited 1 properties in 6 ms.
Support contains 6 out of 298 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 298/298 places, 200/200 transitions.
Performed 47 Post agglomeration using F-continuation condition.Transition count delta: 47
Deduced a syphon composed of 47 places in 1 ms
Reduce places removed 47 places and 0 transitions.
Iterating global reduction 0 with 94 rules applied. Total rules applied 94 place count 251 transition count 153
Free-agglomeration rule applied 1 times.
Iterating global reduction 0 with 1 rules applied. Total rules applied 95 place count 251 transition count 152
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 97 place count 249 transition count 152
Free-agglomeration rule applied 1 times.
Iterating global reduction 1 with 1 rules applied. Total rules applied 98 place count 249 transition count 151
Reduce places removed 1 places and 0 transitions.
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 100 place count 248 transition count 150
Free-agglomeration rule (complex) applied 48 times.
Iterating global reduction 2 with 48 rules applied. Total rules applied 148 place count 248 transition count 102
Discarding 2 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Remove reverse transitions (loop back) rule discarded transition t5.t4 and 2 places that fell out of Prefix Of Interest.
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 36 transitions
Trivial Post-agglo rules discarded 36 transitions
Performed 36 trivial Post agglomeration. Transition count delta: 36
Iterating post reduction 2 with 38 rules applied. Total rules applied 186 place count 108 transition count 64
Reduce places removed 69 places and 0 transitions.
Drop transitions removed 36 transitions
Reduce isomorphic transitions removed 36 transitions.
Iterating post reduction 3 with 105 rules applied. Total rules applied 291 place count 39 transition count 28
Performed 6 Post agglomeration using F-continuation condition.Transition count delta: 6
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 12 places and 0 transitions.
Iterating global reduction 4 with 18 rules applied. Total rules applied 309 place count 27 transition count 22
Drop transitions removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 4 with 6 rules applied. Total rules applied 315 place count 27 transition count 16
Ensure Unique test removed 6 places
Iterating post reduction 5 with 6 rules applied. Total rules applied 321 place count 21 transition count 16
Performed 3 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 6 with 3 Pre rules applied. Total rules applied 321 place count 21 transition count 13
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 6 with 9 rules applied. Total rules applied 330 place count 15 transition count 13
Applied a total of 330 rules in 66 ms. Remains 15 /298 variables (removed 283) and now considering 13/200 (removed 187) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 66 ms. Remains : 15/298 places, 13/200 transitions.
Finished random walk after 7 steps, including 0 resets, run visited all 2 properties in 1 ms. (steps per millisecond=7 )
Successfully simplified 2 atomic propositions for a total of 16 simplifications.
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 18 ms
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 18 ms
[2023-03-17 12:13:44] [INFO ] Input system was already deterministic with 200 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 298/298 places, 200/200 transitions.
Applied a total of 0 rules in 3 ms. Remains 298 /298 variables (removed 0) and now considering 200/200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 298/298 places, 200/200 transitions.
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 14 ms
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 13 ms
[2023-03-17 12:13:44] [INFO ] Input system was already deterministic with 200 transitions.
Starting structural reductions in LTL mode, iteration 0 : 298/298 places, 200/200 transitions.
Applied a total of 0 rules in 6 ms. Remains 298 /298 variables (removed 0) and now considering 200/200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 298/298 places, 200/200 transitions.
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 12 ms
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 13 ms
[2023-03-17 12:13:44] [INFO ] Input system was already deterministic with 200 transitions.
Starting structural reductions in LTL mode, iteration 0 : 298/298 places, 200/200 transitions.
Applied a total of 0 rules in 4 ms. Remains 298 /298 variables (removed 0) and now considering 200/200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 298/298 places, 200/200 transitions.
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 11 ms
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 12 ms
[2023-03-17 12:13:44] [INFO ] Input system was already deterministic with 200 transitions.
Starting structural reductions in LTL mode, iteration 0 : 298/298 places, 200/200 transitions.
Applied a total of 0 rules in 2 ms. Remains 298 /298 variables (removed 0) and now considering 200/200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 298/298 places, 200/200 transitions.
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 13 ms
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 12 ms
[2023-03-17 12:13:44] [INFO ] Input system was already deterministic with 200 transitions.
Starting structural reductions in LTL mode, iteration 0 : 298/298 places, 200/200 transitions.
Applied a total of 0 rules in 2 ms. Remains 298 /298 variables (removed 0) and now considering 200/200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 298/298 places, 200/200 transitions.
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 15 ms
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 9 ms
[2023-03-17 12:13:44] [INFO ] Input system was already deterministic with 200 transitions.
Starting structural reductions in LTL mode, iteration 0 : 298/298 places, 200/200 transitions.
Applied a total of 0 rules in 2 ms. Remains 298 /298 variables (removed 0) and now considering 200/200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 298/298 places, 200/200 transitions.
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 10 ms
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 10 ms
[2023-03-17 12:13:44] [INFO ] Input system was already deterministic with 200 transitions.
Starting structural reductions in LTL mode, iteration 0 : 298/298 places, 200/200 transitions.
Applied a total of 0 rules in 2 ms. Remains 298 /298 variables (removed 0) and now considering 200/200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 298/298 places, 200/200 transitions.
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 10 ms
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 9 ms
[2023-03-17 12:13:44] [INFO ] Input system was already deterministic with 200 transitions.
Starting structural reductions in LTL mode, iteration 0 : 298/298 places, 200/200 transitions.
Applied a total of 0 rules in 2 ms. Remains 298 /298 variables (removed 0) and now considering 200/200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 298/298 places, 200/200 transitions.
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 8 ms
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 9 ms
[2023-03-17 12:13:44] [INFO ] Input system was already deterministic with 200 transitions.
Starting structural reductions in LTL mode, iteration 0 : 298/298 places, 200/200 transitions.
Applied a total of 0 rules in 2 ms. Remains 298 /298 variables (removed 0) and now considering 200/200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 298/298 places, 200/200 transitions.
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 8 ms
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 8 ms
[2023-03-17 12:13:44] [INFO ] Input system was already deterministic with 200 transitions.
Starting structural reductions in LTL mode, iteration 0 : 298/298 places, 200/200 transitions.
Applied a total of 0 rules in 2 ms. Remains 298 /298 variables (removed 0) and now considering 200/200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 298/298 places, 200/200 transitions.
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 9 ms
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 8 ms
[2023-03-17 12:13:44] [INFO ] Input system was already deterministic with 200 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 298/298 places, 200/200 transitions.
Performed 44 Post agglomeration using F-continuation condition.Transition count delta: 44
Deduced a syphon composed of 44 places in 0 ms
Reduce places removed 44 places and 0 transitions.
Iterating global reduction 0 with 88 rules applied. Total rules applied 88 place count 254 transition count 156
Applied a total of 88 rules in 13 ms. Remains 254 /298 variables (removed 44) and now considering 156/200 (removed 44) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 13 ms. Remains : 254/298 places, 156/200 transitions.
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 6 ms
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 8 ms
[2023-03-17 12:13:44] [INFO ] Input system was already deterministic with 156 transitions.
Starting structural reductions in LTL mode, iteration 0 : 298/298 places, 200/200 transitions.
Applied a total of 0 rules in 2 ms. Remains 298 /298 variables (removed 0) and now considering 200/200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 298/298 places, 200/200 transitions.
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 8 ms
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 10 ms
[2023-03-17 12:13:44] [INFO ] Input system was already deterministic with 200 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 298/298 places, 200/200 transitions.
Performed 42 Post agglomeration using F-continuation condition.Transition count delta: 42
Deduced a syphon composed of 42 places in 0 ms
Reduce places removed 42 places and 0 transitions.
Iterating global reduction 0 with 84 rules applied. Total rules applied 84 place count 256 transition count 158
Applied a total of 84 rules in 12 ms. Remains 256 /298 variables (removed 42) and now considering 158/200 (removed 42) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 12 ms. Remains : 256/298 places, 158/200 transitions.
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 5 ms
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 6 ms
[2023-03-17 12:13:44] [INFO ] Input system was already deterministic with 158 transitions.
Starting structural reductions in LTL mode, iteration 0 : 298/298 places, 200/200 transitions.
Applied a total of 0 rules in 2 ms. Remains 298 /298 variables (removed 0) and now considering 200/200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 298/298 places, 200/200 transitions.
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 7 ms
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 9 ms
[2023-03-17 12:13:44] [INFO ] Input system was already deterministic with 200 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 298/298 places, 200/200 transitions.
Performed 49 Post agglomeration using F-continuation condition.Transition count delta: 49
Deduced a syphon composed of 49 places in 0 ms
Reduce places removed 49 places and 0 transitions.
Iterating global reduction 0 with 98 rules applied. Total rules applied 98 place count 249 transition count 151
Applied a total of 98 rules in 12 ms. Remains 249 /298 variables (removed 49) and now considering 151/200 (removed 49) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 12 ms. Remains : 249/298 places, 151/200 transitions.
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 5 ms
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 6 ms
[2023-03-17 12:13:44] [INFO ] Input system was already deterministic with 151 transitions.
Starting structural reductions in LTL mode, iteration 0 : 298/298 places, 200/200 transitions.
Applied a total of 0 rules in 1 ms. Remains 298 /298 variables (removed 0) and now considering 200/200 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 298/298 places, 200/200 transitions.
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 8 ms
[2023-03-17 12:13:44] [INFO ] Flatten gal took : 14 ms
[2023-03-17 12:13:44] [INFO ] Input system was already deterministic with 200 transitions.
[2023-03-17 12:13:45] [INFO ] Flatten gal took : 8 ms
[2023-03-17 12:13:45] [INFO ] Flatten gal took : 8 ms
[2023-03-17 12:13:45] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-17 12:13:45] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 298 places, 200 transitions and 890 arcs took 1 ms.
Total runtime 3761 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT ResAllocation-PT-R003C050
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability
FORMULA ResAllocation-PT-R003C050-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R003C050-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R003C050-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R003C050-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R003C050-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R003C050-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679055676693
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 10 (type EXCL) for 9 ResAllocation-PT-R003C050-CTLFireability-03
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 56 (type FNDP) for 36 ResAllocation-PT-R003C050-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 57 (type EQUN) for 36 ResAllocation-PT-R003C050-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 59 (type SRCH) for 36 ResAllocation-PT-R003C050-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 59 (type SRCH) for ResAllocation-PT-R003C050-CTLFireability-12
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 56 (type FNDP) for ResAllocation-PT-R003C050-CTLFireability-12
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
sara: try reading problem file /home/mcc/execution/373/CTLFireability-57.sara.
lola: CANCELED task # 57 (type EQUN) for ResAllocation-PT-R003C050-CTLFireability-12 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
sara: lola: place or transition ordering is non-deterministic
rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 57 (type EQUN) for ResAllocation-PT-R003C050-CTLFireability-12
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-12: CONJ 0 1 0 0 6 0 0 5
ResAllocation-PT-R003C050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/225 4/32 ResAllocation-PT-R003C050-CTLFireability-03 628076 m, 125615 m/sec, 3987850 t fired, .
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-12: CONJ 0 1 0 0 6 0 0 5
ResAllocation-PT-R003C050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 10/225 8/32 ResAllocation-PT-R003C050-CTLFireability-03 1250422 m, 124469 m/sec, 8082325 t fired, .
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ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-12: CONJ 0 1 0 0 6 0 0 5
ResAllocation-PT-R003C050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 15/225 11/32 ResAllocation-PT-R003C050-CTLFireability-03 1834732 m, 116862 m/sec, 12257051 t fired, .
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ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-12: CONJ 0 1 0 0 6 0 0 5
ResAllocation-PT-R003C050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 20/225 14/32 ResAllocation-PT-R003C050-CTLFireability-03 2437121 m, 120477 m/sec, 16298962 t fired, .
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
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ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
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ResAllocation-PT-R003C050-CTLFireability-00: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
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ResAllocation-PT-R003C050-CTLFireability-00: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
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ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CONJ true CONJ
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ResAllocation-PT-R003C050-CTLFireability-00: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CONJ true CONJ
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ResAllocation-PT-R003C050-CTLFireability-00: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
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ResAllocation-PT-R003C050-CTLFireability-00: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CONJ true CONJ
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-00: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-00: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-02: CTL unknown AGGR
ResAllocation-PT-R003C050-CTLFireability-03: CTL unknown AGGR
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-05: CTL unknown AGGR
ResAllocation-PT-R003C050-CTLFireability-06: CTL unknown AGGR
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-08: CTL unknown AGGR
ResAllocation-PT-R003C050-CTLFireability-09: CTL unknown AGGR
ResAllocation-PT-R003C050-CTLFireability-10: CTL unknown AGGR
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CONJ true CONJ
ResAllocation-PT-R003C050-CTLFireability-13: CTL unknown AGGR
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ResAllocation-PT-R003C050"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is ResAllocation-PT-R003C050, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r327-tall-167889200000714"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ResAllocation-PT-R003C050.tgz
mv ResAllocation-PT-R003C050 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;