Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r327-tall-167889200000706.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is ResAllocation-PT-R003C020, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r327-tall-167889200000706
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 676K
-rw-r--r-- 1 mcc users 6.0K Feb 25 15:24 CTLCardinality.txt
-rw-r--r-- 1 mcc users 57K Feb 25 15:24 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.2K Feb 25 15:23 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K Feb 25 15:23 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 16:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Feb 25 16:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 19K Feb 25 15:26 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 203K Feb 25 15:26 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.1K Feb 25 15:25 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 75K Feb 25 15:25 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 16:44 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:44 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 9 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 143K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ResAllocation-PT-R003C020-CTLFireability-00
FORMULA_NAME ResAllocation-PT-R003C020-CTLFireability-01
FORMULA_NAME ResAllocation-PT-R003C020-CTLFireability-02
FORMULA_NAME ResAllocation-PT-R003C020-CTLFireability-03
FORMULA_NAME ResAllocation-PT-R003C020-CTLFireability-04
FORMULA_NAME ResAllocation-PT-R003C020-CTLFireability-05
FORMULA_NAME ResAllocation-PT-R003C020-CTLFireability-06
FORMULA_NAME ResAllocation-PT-R003C020-CTLFireability-07
FORMULA_NAME ResAllocation-PT-R003C020-CTLFireability-08
FORMULA_NAME ResAllocation-PT-R003C020-CTLFireability-09
FORMULA_NAME ResAllocation-PT-R003C020-CTLFireability-10
FORMULA_NAME ResAllocation-PT-R003C020-CTLFireability-11
FORMULA_NAME ResAllocation-PT-R003C020-CTLFireability-12
FORMULA_NAME ResAllocation-PT-R003C020-CTLFireability-13
FORMULA_NAME ResAllocation-PT-R003C020-CTLFireability-14
FORMULA_NAME ResAllocation-PT-R003C020-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679054924999

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ResAllocation-PT-R003C020
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-17 12:08:46] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-17 12:08:46] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-17 12:08:46] [INFO ] Load time of PNML (sax parser for PT used): 51 ms
[2023-03-17 12:08:46] [INFO ] Transformed 120 places.
[2023-03-17 12:08:46] [INFO ] Transformed 80 transitions.
[2023-03-17 12:08:46] [INFO ] Parsed PT model containing 120 places and 80 transitions and 354 arcs in 120 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Support contains 101 out of 120 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 120/120 places, 80/80 transitions.
Applied a total of 0 rules in 10 ms. Remains 120 /120 variables (removed 0) and now considering 80/80 (removed 0) transitions.
// Phase 1: matrix 80 rows 120 cols
[2023-03-17 12:08:46] [INFO ] Computed 60 place invariants in 14 ms
[2023-03-17 12:08:47] [INFO ] Implicit Places using invariants in 409 ms returned []
[2023-03-17 12:08:47] [INFO ] Invariant cache hit.
[2023-03-17 12:08:47] [INFO ] Implicit Places using invariants and state equation in 92 ms returned []
Implicit Place search using SMT with State Equation took 522 ms to find 0 implicit places.
[2023-03-17 12:08:47] [INFO ] Invariant cache hit.
[2023-03-17 12:08:47] [INFO ] Dead Transitions using invariants and state equation in 65 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 599 ms. Remains : 120/120 places, 80/80 transitions.
Support contains 101 out of 120 places after structural reductions.
[2023-03-17 12:08:47] [INFO ] Flatten gal took : 29 ms
[2023-03-17 12:08:47] [INFO ] Flatten gal took : 12 ms
[2023-03-17 12:08:47] [INFO ] Input system was already deterministic with 80 transitions.
Incomplete random walk after 10000 steps, including 223 resets, run finished after 375 ms. (steps per millisecond=26 ) properties (out of 72) seen :70
Incomplete Best-First random walk after 10001 steps, including 16 resets, run finished after 30 ms. (steps per millisecond=333 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 8 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-17 12:08:48] [INFO ] Invariant cache hit.
[2023-03-17 12:08:48] [INFO ] [Real]Absence check using 60 positive place invariants in 8 ms returned sat
[2023-03-17 12:08:48] [INFO ] After 121ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0 real:1
[2023-03-17 12:08:48] [INFO ] [Nat]Absence check using 60 positive place invariants in 12 ms returned sat
[2023-03-17 12:08:48] [INFO ] After 28ms SMT Verify possible using state equation in natural domain returned unsat :1 sat :1
[2023-03-17 12:08:48] [INFO ] Deduced a trap composed of 4 places in 28 ms of which 4 ms to minimize.
[2023-03-17 12:08:48] [INFO ] Deduced a trap composed of 4 places in 30 ms of which 1 ms to minimize.
[2023-03-17 12:08:48] [INFO ] Deduced a trap composed of 4 places in 21 ms of which 1 ms to minimize.
[2023-03-17 12:08:48] [INFO ] Trap strengthening (SAT) tested/added 4/3 trap constraints in 105 ms
[2023-03-17 12:08:48] [INFO ] After 140ms SMT Verify possible using trap constraints in natural domain returned unsat :1 sat :1
Attempting to minimize the solution found.
Minimization took 5 ms.
[2023-03-17 12:08:48] [INFO ] After 211ms SMT Verify possible using all constraints in natural domain returned unsat :1 sat :1
Fused 2 Parikh solutions to 1 different solutions.
Finished Parikh walk after 18 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=18 )
Parikh walk visited 1 properties in 2 ms.
Successfully simplified 1 atomic propositions for a total of 16 simplifications.
Initial state reduction rules removed 1 formulas.
FORMULA ResAllocation-PT-R003C020-CTLFireability-03 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-17 12:08:48] [INFO ] Flatten gal took : 8 ms
[2023-03-17 12:08:48] [INFO ] Flatten gal took : 8 ms
[2023-03-17 12:08:48] [INFO ] Input system was already deterministic with 80 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 120/120 places, 80/80 transitions.
Applied a total of 0 rules in 3 ms. Remains 120 /120 variables (removed 0) and now considering 80/80 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 120/120 places, 80/80 transitions.
[2023-03-17 12:08:48] [INFO ] Flatten gal took : 6 ms
[2023-03-17 12:08:48] [INFO ] Flatten gal took : 6 ms
[2023-03-17 12:08:48] [INFO ] Input system was already deterministic with 80 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 120/120 places, 80/80 transitions.
Performed 8 Post agglomeration using F-continuation condition.Transition count delta: 8
Deduced a syphon composed of 8 places in 1 ms
Reduce places removed 8 places and 0 transitions.
Iterating global reduction 0 with 16 rules applied. Total rules applied 16 place count 112 transition count 72
Applied a total of 16 rules in 14 ms. Remains 112 /120 variables (removed 8) and now considering 72/80 (removed 8) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 14 ms. Remains : 112/120 places, 72/80 transitions.
[2023-03-17 12:08:48] [INFO ] Flatten gal took : 5 ms
[2023-03-17 12:08:48] [INFO ] Flatten gal took : 6 ms
[2023-03-17 12:08:48] [INFO ] Input system was already deterministic with 72 transitions.
Starting structural reductions in LTL mode, iteration 0 : 120/120 places, 80/80 transitions.
Applied a total of 0 rules in 2 ms. Remains 120 /120 variables (removed 0) and now considering 80/80 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 120/120 places, 80/80 transitions.
[2023-03-17 12:08:48] [INFO ] Flatten gal took : 6 ms
[2023-03-17 12:08:48] [INFO ] Flatten gal took : 7 ms
[2023-03-17 12:08:48] [INFO ] Input system was already deterministic with 80 transitions.
Starting structural reductions in LTL mode, iteration 0 : 120/120 places, 80/80 transitions.
Applied a total of 0 rules in 3 ms. Remains 120 /120 variables (removed 0) and now considering 80/80 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 120/120 places, 80/80 transitions.
[2023-03-17 12:08:48] [INFO ] Flatten gal took : 6 ms
[2023-03-17 12:08:48] [INFO ] Flatten gal took : 6 ms
[2023-03-17 12:08:48] [INFO ] Input system was already deterministic with 80 transitions.
Starting structural reductions in LTL mode, iteration 0 : 120/120 places, 80/80 transitions.
Applied a total of 0 rules in 3 ms. Remains 120 /120 variables (removed 0) and now considering 80/80 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 120/120 places, 80/80 transitions.
[2023-03-17 12:08:48] [INFO ] Flatten gal took : 5 ms
[2023-03-17 12:08:48] [INFO ] Flatten gal took : 5 ms
[2023-03-17 12:08:48] [INFO ] Input system was already deterministic with 80 transitions.
Starting structural reductions in LTL mode, iteration 0 : 120/120 places, 80/80 transitions.
Applied a total of 0 rules in 3 ms. Remains 120 /120 variables (removed 0) and now considering 80/80 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 120/120 places, 80/80 transitions.
[2023-03-17 12:08:48] [INFO ] Flatten gal took : 4 ms
[2023-03-17 12:08:48] [INFO ] Flatten gal took : 5 ms
[2023-03-17 12:08:48] [INFO ] Input system was already deterministic with 80 transitions.
Starting structural reductions in LTL mode, iteration 0 : 120/120 places, 80/80 transitions.
Applied a total of 0 rules in 2 ms. Remains 120 /120 variables (removed 0) and now considering 80/80 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 120/120 places, 80/80 transitions.
[2023-03-17 12:08:48] [INFO ] Flatten gal took : 5 ms
[2023-03-17 12:08:48] [INFO ] Flatten gal took : 9 ms
[2023-03-17 12:08:48] [INFO ] Input system was already deterministic with 80 transitions.
Starting structural reductions in LTL mode, iteration 0 : 120/120 places, 80/80 transitions.
Applied a total of 0 rules in 3 ms. Remains 120 /120 variables (removed 0) and now considering 80/80 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 120/120 places, 80/80 transitions.
[2023-03-17 12:08:48] [INFO ] Flatten gal took : 5 ms
[2023-03-17 12:08:48] [INFO ] Flatten gal took : 5 ms
[2023-03-17 12:08:48] [INFO ] Input system was already deterministic with 80 transitions.
Starting structural reductions in LTL mode, iteration 0 : 120/120 places, 80/80 transitions.
Applied a total of 0 rules in 14 ms. Remains 120 /120 variables (removed 0) and now considering 80/80 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 14 ms. Remains : 120/120 places, 80/80 transitions.
[2023-03-17 12:08:48] [INFO ] Flatten gal took : 5 ms
[2023-03-17 12:08:48] [INFO ] Flatten gal took : 5 ms
[2023-03-17 12:08:48] [INFO ] Input system was already deterministic with 80 transitions.
Starting structural reductions in LTL mode, iteration 0 : 120/120 places, 80/80 transitions.
Applied a total of 0 rules in 1 ms. Remains 120 /120 variables (removed 0) and now considering 80/80 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 120/120 places, 80/80 transitions.
[2023-03-17 12:08:48] [INFO ] Flatten gal took : 5 ms
[2023-03-17 12:08:48] [INFO ] Flatten gal took : 5 ms
[2023-03-17 12:08:48] [INFO ] Input system was already deterministic with 80 transitions.
Starting structural reductions in LTL mode, iteration 0 : 120/120 places, 80/80 transitions.
Applied a total of 0 rules in 1 ms. Remains 120 /120 variables (removed 0) and now considering 80/80 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 120/120 places, 80/80 transitions.
[2023-03-17 12:08:48] [INFO ] Flatten gal took : 5 ms
[2023-03-17 12:08:48] [INFO ] Flatten gal took : 5 ms
[2023-03-17 12:08:48] [INFO ] Input system was already deterministic with 80 transitions.
Starting structural reductions in LTL mode, iteration 0 : 120/120 places, 80/80 transitions.
Applied a total of 0 rules in 1 ms. Remains 120 /120 variables (removed 0) and now considering 80/80 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 120/120 places, 80/80 transitions.
[2023-03-17 12:08:48] [INFO ] Flatten gal took : 4 ms
[2023-03-17 12:08:48] [INFO ] Flatten gal took : 4 ms
[2023-03-17 12:08:48] [INFO ] Input system was already deterministic with 80 transitions.
Starting structural reductions in LTL mode, iteration 0 : 120/120 places, 80/80 transitions.
Applied a total of 0 rules in 1 ms. Remains 120 /120 variables (removed 0) and now considering 80/80 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 120/120 places, 80/80 transitions.
[2023-03-17 12:08:49] [INFO ] Flatten gal took : 4 ms
[2023-03-17 12:08:49] [INFO ] Flatten gal took : 4 ms
[2023-03-17 12:08:49] [INFO ] Input system was already deterministic with 80 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 120/120 places, 80/80 transitions.
Performed 19 Post agglomeration using F-continuation condition.Transition count delta: 19
Deduced a syphon composed of 19 places in 1 ms
Reduce places removed 20 places and 0 transitions.
Iterating global reduction 0 with 39 rules applied. Total rules applied 39 place count 100 transition count 61
Applied a total of 39 rules in 7 ms. Remains 100 /120 variables (removed 20) and now considering 61/80 (removed 19) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 7 ms. Remains : 100/120 places, 61/80 transitions.
[2023-03-17 12:08:49] [INFO ] Flatten gal took : 3 ms
[2023-03-17 12:08:49] [INFO ] Flatten gal took : 4 ms
[2023-03-17 12:08:49] [INFO ] Input system was already deterministic with 61 transitions.
Starting structural reductions in LTL mode, iteration 0 : 120/120 places, 80/80 transitions.
Applied a total of 0 rules in 1 ms. Remains 120 /120 variables (removed 0) and now considering 80/80 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 120/120 places, 80/80 transitions.
[2023-03-17 12:08:49] [INFO ] Flatten gal took : 4 ms
[2023-03-17 12:08:49] [INFO ] Flatten gal took : 4 ms
[2023-03-17 12:08:49] [INFO ] Input system was already deterministic with 80 transitions.
[2023-03-17 12:08:49] [INFO ] Flatten gal took : 5 ms
[2023-03-17 12:08:49] [INFO ] Flatten gal took : 6 ms
[2023-03-17 12:08:49] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-17 12:08:49] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 120 places, 80 transitions and 354 arcs took 1 ms.
Total runtime 2604 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT ResAllocation-PT-R003C020
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA ResAllocation-PT-R003C020-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C020-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C020-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C020-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C020-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C020-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C020-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C020-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C020-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C020-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679055210490

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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lola: rewrite Frontend/Parser/formula_rewrite.k:317
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lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
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lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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lola: RELEASE
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lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
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lola: FINISHED task # 22 (type EXCL) for ResAllocation-PT-R003C020-CTLFireability-08
lola: result : true
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lola: rewrite Frontend/Parser/formula_rewrite.k:812
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lola: rewrite Frontend/Parser/formula_rewrite.k:808
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
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lola: Created skeleton in 0.000000 secs.
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C020-CTLFireability-06: CTL false CTL model checker
ResAllocation-PT-R003C020-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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32 CTL EXCL 5/257 6/32 ResAllocation-PT-R003C020-CTLFireability-10 1231956 m, 246391 m/sec, 6423894 t fired, .

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32 CTL EXCL 10/257 11/32 ResAllocation-PT-R003C020-CTLFireability-10 2416080 m, 236824 m/sec, 12979903 t fired, .

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32 CTL EXCL 15/257 15/32 ResAllocation-PT-R003C020-CTLFireability-10 3495044 m, 215792 m/sec, 19410527 t fired, .

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32 CTL EXCL 20/257 20/32 ResAllocation-PT-R003C020-CTLFireability-10 4630692 m, 227129 m/sec, 25895819 t fired, .

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32 CTL EXCL 25/257 25/32 ResAllocation-PT-R003C020-CTLFireability-10 5783308 m, 230523 m/sec, 31969229 t fired, .

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32 CTL EXCL 30/257 29/32 ResAllocation-PT-R003C020-CTLFireability-10 6849897 m, 213317 m/sec, 38478098 t fired, .

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7 CTL EXCL 40/848 19/32 ResAllocation-PT-R003C020-CTLFireability-02 4496327 m, 96855 m/sec, 44917743 t fired, .

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ResAllocation-PT-R003C020-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C020-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

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7 CTL EXCL 45/848 21/32 ResAllocation-PT-R003C020-CTLFireability-02 4934884 m, 87711 m/sec, 49989016 t fired, .

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7 CTL EXCL 50/848 24/32 ResAllocation-PT-R003C020-CTLFireability-02 5534343 m, 119891 m/sec, 55506082 t fired, .

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7 CTL EXCL 55/848 26/32 ResAllocation-PT-R003C020-CTLFireability-02 6113708 m, 115873 m/sec, 61117249 t fired, .

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ResAllocation-PT-R003C020-CTLFireability-07: CTL true CTL model checker
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7 CTL EXCL 60/848 28/32 ResAllocation-PT-R003C020-CTLFireability-02 6604429 m, 98144 m/sec, 66467907 t fired, .

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ResAllocation-PT-R003C020-CTLFireability-07: CTL true CTL model checker
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ResAllocation-PT-R003C020-CTLFireability-11: CTL true CTL model checker
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7 CTL EXCL 65/848 30/32 ResAllocation-PT-R003C020-CTLFireability-02 7061339 m, 91382 m/sec, 71784660 t fired, .

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ResAllocation-PT-R003C020-CTLFireability-11: CTL true CTL model checker
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lola: LAUNCH task # 1 (type EXCL) for 0 ResAllocation-PT-R003C020-CTLFireability-00
lola: time limit : 1106 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for ResAllocation-PT-R003C020-CTLFireability-00
lola: result : false
lola: markings : 14
lola: fired transitions : 76
lola: time used : 0.000000
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lola: LAUNCH task # 44 (type EXCL) for 43 ResAllocation-PT-R003C020-CTLFireability-14
lola: time limit : 1660 sec
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lola: result : false
lola: markings : 11
lola: fired transitions : 22
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 ResAllocation-PT-R003C020-CTLFireability-01
lola: time limit : 3320 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for ResAllocation-PT-R003C020-CTLFireability-01
lola: result : true
lola: markings : 2514
lola: fired transitions : 21241
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 15

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C020-CTLFireability-00: CTL false CTL model checker
ResAllocation-PT-R003C020-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C020-CTLFireability-02: CTL unknown AGGR
ResAllocation-PT-R003C020-CTLFireability-04: CTL unknown AGGR
ResAllocation-PT-R003C020-CTLFireability-05: CTL true CTL model checker
ResAllocation-PT-R003C020-CTLFireability-06: CTL false CTL model checker
ResAllocation-PT-R003C020-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C020-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R003C020-CTLFireability-09: CONJ unknown CONJ
ResAllocation-PT-R003C020-CTLFireability-10: CTL unknown AGGR
ResAllocation-PT-R003C020-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C020-CTLFireability-12: CTL unknown AGGR
ResAllocation-PT-R003C020-CTLFireability-13: CTL false CTL model checker
ResAllocation-PT-R003C020-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C020-CTLFireability-15: CTL true CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ResAllocation-PT-R003C020"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is ResAllocation-PT-R003C020, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r327-tall-167889200000706"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ResAllocation-PT-R003C020.tgz
mv ResAllocation-PT-R003C020 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;