Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r327-tall-167889199900690.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is ResAllocation-PT-R003C010, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r327-tall-167889199900690
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 568K
-rw-r--r-- 1 mcc users 7.8K Feb 25 15:32 CTLCardinality.txt
-rw-r--r-- 1 mcc users 83K Feb 25 15:32 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.7K Feb 25 15:31 CTLFireability.txt
-rw-r--r-- 1 mcc users 50K Feb 25 15:31 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.1K Feb 25 16:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Feb 25 16:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 16:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 16:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 25 15:33 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 112K Feb 25 15:33 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 13K Feb 25 15:33 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 110K Feb 25 15:33 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 16:44 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:44 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 9 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 71K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ResAllocation-PT-R003C010-CTLFireability-00
FORMULA_NAME ResAllocation-PT-R003C010-CTLFireability-01
FORMULA_NAME ResAllocation-PT-R003C010-CTLFireability-02
FORMULA_NAME ResAllocation-PT-R003C010-CTLFireability-03
FORMULA_NAME ResAllocation-PT-R003C010-CTLFireability-04
FORMULA_NAME ResAllocation-PT-R003C010-CTLFireability-05
FORMULA_NAME ResAllocation-PT-R003C010-CTLFireability-06
FORMULA_NAME ResAllocation-PT-R003C010-CTLFireability-07
FORMULA_NAME ResAllocation-PT-R003C010-CTLFireability-08
FORMULA_NAME ResAllocation-PT-R003C010-CTLFireability-09
FORMULA_NAME ResAllocation-PT-R003C010-CTLFireability-10
FORMULA_NAME ResAllocation-PT-R003C010-CTLFireability-11
FORMULA_NAME ResAllocation-PT-R003C010-CTLFireability-12
FORMULA_NAME ResAllocation-PT-R003C010-CTLFireability-13
FORMULA_NAME ResAllocation-PT-R003C010-CTLFireability-14
FORMULA_NAME ResAllocation-PT-R003C010-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679054440865

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ResAllocation-PT-R003C010
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-17 12:00:42] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-17 12:00:42] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-17 12:00:42] [INFO ] Load time of PNML (sax parser for PT used): 39 ms
[2023-03-17 12:00:42] [INFO ] Transformed 60 places.
[2023-03-17 12:00:42] [INFO ] Transformed 40 transitions.
[2023-03-17 12:00:42] [INFO ] Parsed PT model containing 60 places and 40 transitions and 174 arcs in 96 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Initial state reduction rules removed 2 formulas.
FORMULA ResAllocation-PT-R003C010-CTLFireability-11 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA ResAllocation-PT-R003C010-CTLFireability-15 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 56 out of 60 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 60/60 places, 40/40 transitions.
Applied a total of 0 rules in 10 ms. Remains 60 /60 variables (removed 0) and now considering 40/40 (removed 0) transitions.
// Phase 1: matrix 40 rows 60 cols
[2023-03-17 12:00:42] [INFO ] Computed 30 place invariants in 12 ms
[2023-03-17 12:00:42] [INFO ] Implicit Places using invariants in 165 ms returned []
[2023-03-17 12:00:42] [INFO ] Invariant cache hit.
[2023-03-17 12:00:42] [INFO ] Implicit Places using invariants and state equation in 54 ms returned []
Implicit Place search using SMT with State Equation took 241 ms to find 0 implicit places.
[2023-03-17 12:00:42] [INFO ] Invariant cache hit.
[2023-03-17 12:00:42] [INFO ] Dead Transitions using invariants and state equation in 60 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 312 ms. Remains : 60/60 places, 40/40 transitions.
Support contains 56 out of 60 places after structural reductions.
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 21 ms
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 8 ms
[2023-03-17 12:00:43] [INFO ] Input system was already deterministic with 40 transitions.
Incomplete random walk after 10000 steps, including 427 resets, run finished after 266 ms. (steps per millisecond=37 ) properties (out of 50) seen :48
Incomplete Best-First random walk after 10001 steps, including 53 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 57 resets, run finished after 22 ms. (steps per millisecond=454 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-17 12:00:43] [INFO ] Invariant cache hit.
[2023-03-17 12:00:43] [INFO ] [Real]Absence check using 30 positive place invariants in 8 ms returned sat
[2023-03-17 12:00:43] [INFO ] After 63ms SMT Verify possible using all constraints in real domain returned unsat :2 sat :0
Fused 2 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 2 atomic propositions for a total of 14 simplifications.
FORMULA ResAllocation-PT-R003C010-CTLFireability-06 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 6 ms
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 5 ms
[2023-03-17 12:00:43] [INFO ] Input system was already deterministic with 40 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 60/60 places, 40/40 transitions.
Applied a total of 0 rules in 1 ms. Remains 60 /60 variables (removed 0) and now considering 40/40 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 60/60 places, 40/40 transitions.
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 4 ms
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 4 ms
[2023-03-17 12:00:43] [INFO ] Input system was already deterministic with 40 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 60/60 places, 40/40 transitions.
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 0 with 7 rules applied. Total rules applied 7 place count 56 transition count 37
Applied a total of 7 rules in 9 ms. Remains 56 /60 variables (removed 4) and now considering 37/40 (removed 3) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 9 ms. Remains : 56/60 places, 37/40 transitions.
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 3 ms
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 3 ms
[2023-03-17 12:00:43] [INFO ] Input system was already deterministic with 37 transitions.
Starting structural reductions in LTL mode, iteration 0 : 60/60 places, 40/40 transitions.
Applied a total of 0 rules in 1 ms. Remains 60 /60 variables (removed 0) and now considering 40/40 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 60/60 places, 40/40 transitions.
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 3 ms
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 3 ms
[2023-03-17 12:00:43] [INFO ] Input system was already deterministic with 40 transitions.
Starting structural reductions in LTL mode, iteration 0 : 60/60 places, 40/40 transitions.
Applied a total of 0 rules in 2 ms. Remains 60 /60 variables (removed 0) and now considering 40/40 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 60/60 places, 40/40 transitions.
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 3 ms
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 4 ms
[2023-03-17 12:00:43] [INFO ] Input system was already deterministic with 40 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 60/60 places, 40/40 transitions.
Performed 10 Post agglomeration using F-continuation condition.Transition count delta: 10
Deduced a syphon composed of 10 places in 0 ms
Reduce places removed 11 places and 0 transitions.
Iterating global reduction 0 with 21 rules applied. Total rules applied 21 place count 49 transition count 30
Applied a total of 21 rules in 5 ms. Remains 49 /60 variables (removed 11) and now considering 30/40 (removed 10) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 49/60 places, 30/40 transitions.
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 2 ms
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 3 ms
[2023-03-17 12:00:43] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 60/60 places, 40/40 transitions.
Applied a total of 0 rules in 1 ms. Remains 60 /60 variables (removed 0) and now considering 40/40 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 60/60 places, 40/40 transitions.
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 2 ms
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 3 ms
[2023-03-17 12:00:43] [INFO ] Input system was already deterministic with 40 transitions.
Starting structural reductions in LTL mode, iteration 0 : 60/60 places, 40/40 transitions.
Applied a total of 0 rules in 2 ms. Remains 60 /60 variables (removed 0) and now considering 40/40 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 60/60 places, 40/40 transitions.
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 3 ms
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 3 ms
[2023-03-17 12:00:43] [INFO ] Input system was already deterministic with 40 transitions.
Starting structural reductions in LTL mode, iteration 0 : 60/60 places, 40/40 transitions.
Applied a total of 0 rules in 1 ms. Remains 60 /60 variables (removed 0) and now considering 40/40 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 60/60 places, 40/40 transitions.
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 3 ms
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 3 ms
[2023-03-17 12:00:43] [INFO ] Input system was already deterministic with 40 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 60/60 places, 40/40 transitions.
Performed 7 Post agglomeration using F-continuation condition.Transition count delta: 7
Deduced a syphon composed of 7 places in 0 ms
Reduce places removed 8 places and 0 transitions.
Iterating global reduction 0 with 15 rules applied. Total rules applied 15 place count 52 transition count 33
Applied a total of 15 rules in 4 ms. Remains 52 /60 variables (removed 8) and now considering 33/40 (removed 7) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 52/60 places, 33/40 transitions.
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 2 ms
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 3 ms
[2023-03-17 12:00:43] [INFO ] Input system was already deterministic with 33 transitions.
Starting structural reductions in LTL mode, iteration 0 : 60/60 places, 40/40 transitions.
Applied a total of 0 rules in 1 ms. Remains 60 /60 variables (removed 0) and now considering 40/40 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 60/60 places, 40/40 transitions.
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 2 ms
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 2 ms
[2023-03-17 12:00:43] [INFO ] Input system was already deterministic with 40 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 60/60 places, 40/40 transitions.
Performed 9 Post agglomeration using F-continuation condition.Transition count delta: 9
Deduced a syphon composed of 9 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 0 with 19 rules applied. Total rules applied 19 place count 50 transition count 31
Applied a total of 19 rules in 4 ms. Remains 50 /60 variables (removed 10) and now considering 31/40 (removed 9) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 50/60 places, 31/40 transitions.
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 2 ms
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 2 ms
[2023-03-17 12:00:43] [INFO ] Input system was already deterministic with 31 transitions.
Starting structural reductions in LTL mode, iteration 0 : 60/60 places, 40/40 transitions.
Applied a total of 0 rules in 1 ms. Remains 60 /60 variables (removed 0) and now considering 40/40 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 60/60 places, 40/40 transitions.
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 2 ms
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 3 ms
[2023-03-17 12:00:43] [INFO ] Input system was already deterministic with 40 transitions.
Starting structural reductions in LTL mode, iteration 0 : 60/60 places, 40/40 transitions.
Applied a total of 0 rules in 1 ms. Remains 60 /60 variables (removed 0) and now considering 40/40 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 60/60 places, 40/40 transitions.
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 2 ms
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 2 ms
[2023-03-17 12:00:43] [INFO ] Input system was already deterministic with 40 transitions.
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 3 ms
[2023-03-17 12:00:43] [INFO ] Flatten gal took : 3 ms
[2023-03-17 12:00:43] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-17 12:00:43] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 60 places, 40 transitions and 174 arcs took 1 ms.
Total runtime 1607 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT ResAllocation-PT-R003C010
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA ResAllocation-PT-R003C010-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C010-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C010-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C010-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C010-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C010-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C010-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C010-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C010-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C010-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C010-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C010-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C010-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679054460085

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 1 (type EXCL) for 0 ResAllocation-PT-R003C010-CTLFireability-00
lola: time limit : 199 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 1 (type EXCL) for ResAllocation-PT-R003C010-CTLFireability-00
lola: result : false
lola: markings : 1324
lola: fired transitions : 4640
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 24 (type EXCL) for 23 ResAllocation-PT-R003C010-CTLFireability-05
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:736
lola: rewrite Frontend/Parser/formula_rewrite.k:696
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 47 (type FNDP) for 16 ResAllocation-PT-R003C010-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 48 (type EQUN) for 16 ResAllocation-PT-R003C010-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 50 (type SRCH) for 16 ResAllocation-PT-R003C010-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 50 (type SRCH) for ResAllocation-PT-R003C010-CTLFireability-04
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 47 (type FNDP) for ResAllocation-PT-R003C010-CTLFireability-04
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 48 (type EQUN) for ResAllocation-PT-R003C010-CTLFireability-04 (obsolete)
lola: FINISHED task # 48 (type EQUN) for ResAllocation-PT-R003C010-CTLFireability-04
lola: result : unknown
lola: FINISHED task # 24 (type EXCL) for ResAllocation-PT-R003C010-CTLFireability-05
lola: result : false
lola: markings : 823552
lola: fired transitions : 7172032
lola: time used : 4.000000
lola: memory pages used : 4
lola: LAUNCH task # 45 (type EXCL) for 44 ResAllocation-PT-R003C010-CTLFireability-14
lola: time limit : 299 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for ResAllocation-PT-R003C010-CTLFireability-14
lola: result : true
lola: markings : 17683
lola: fired transitions : 71113
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 41 ResAllocation-PT-R003C010-CTLFireability-13
lola: time limit : 326 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C010-CTLFireability-00: CTL false CTL model checker
ResAllocation-PT-R003C010-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C010-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C010-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
ResAllocation-PT-R003C010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C010-CTLFireability-04: CONJ 0 1 0 0 5 0 0 1
ResAllocation-PT-R003C010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C010-CTLFireability-09: F 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C010-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 1/326 1/32 ResAllocation-PT-R003C010-CTLFireability-13 5788 m, 1157 m/sec, 34951 t fired, .

Time elapsed: 6 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 13
lola: FINISHED task # 42 (type EXCL) for ResAllocation-PT-R003C010-CTLFireability-13
lola: result : true
lola: markings : 20537
lola: fired transitions : 134070
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 36 (type EXCL) for 35 ResAllocation-PT-R003C010-CTLFireability-10
lola: time limit : 359 sec
lola: memory limit: 32 pages
lola: FINISHED task # 36 (type EXCL) for ResAllocation-PT-R003C010-CTLFireability-10
lola: result : true
lola: markings : 8858
lola: fired transitions : 22108
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 30 (type EXCL) for 29 ResAllocation-PT-R003C010-CTLFireability-08
lola: time limit : 399 sec
lola: memory limit: 32 pages
lola: FINISHED task # 30 (type EXCL) for ResAllocation-PT-R003C010-CTLFireability-08
lola: result : true
lola: markings : 48
lola: fired transitions : 202
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 14 (type EXCL) for 13 ResAllocation-PT-R003C010-CTLFireability-03
lola: time limit : 449 sec
lola: memory limit: 32 pages
lola: FINISHED task # 14 (type EXCL) for ResAllocation-PT-R003C010-CTLFireability-03
lola: result : false
lola: markings : 818
lola: fired transitions : 2759
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 11 (type EXCL) for 6 ResAllocation-PT-R003C010-CTLFireability-02
lola: time limit : 513 sec
lola: memory limit: 32 pages
lola: FINISHED task # 11 (type EXCL) for ResAllocation-PT-R003C010-CTLFireability-02
lola: result : false
lola: markings : 823552
lola: fired transitions : 7417296
lola: time used : 4.000000
lola: memory pages used : 4
lola: LAUNCH task # 51 (type EXCL) for 32 ResAllocation-PT-R003C010-CTLFireability-09
lola: time limit : 718 sec
lola: memory limit: 32 pages
lola: FINISHED task # 51 (type EXCL) for ResAllocation-PT-R003C010-CTLFireability-09
lola: result : true
lola: markings : 11
lola: fired transitions : 11
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 39 (type EXCL) for 38 ResAllocation-PT-R003C010-CTLFireability-12
lola: time limit : 897 sec
lola: memory limit: 32 pages
lola: FINISHED task # 39 (type EXCL) for ResAllocation-PT-R003C010-CTLFireability-12
lola: result : true
lola: markings : 8207
lola: fired transitions : 35516
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 27 (type EXCL) for 26 ResAllocation-PT-R003C010-CTLFireability-07
lola: time limit : 1196 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C010-CTLFireability-00: CTL false CTL model checker
ResAllocation-PT-R003C010-CTLFireability-02: CONJ false CTL model checker
ResAllocation-PT-R003C010-CTLFireability-03: CTL false CTL model checker
ResAllocation-PT-R003C010-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C010-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R003C010-CTLFireability-09: F false state space / EG
ResAllocation-PT-R003C010-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R003C010-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C010-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C010-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C010-CTLFireability-04: CONJ 0 1 0 0 5 0 0 1
ResAllocation-PT-R003C010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 1/1196 1/32 ResAllocation-PT-R003C010-CTLFireability-07 81164 m, 16232 m/sec, 654473 t fired, .

Time elapsed: 11 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 13
lola: FINISHED task # 27 (type EXCL) for ResAllocation-PT-R003C010-CTLFireability-07
lola: result : true
lola: markings : 823552
lola: fired transitions : 7998848
lola: time used : 5.000000
lola: memory pages used : 4
lola: LAUNCH task # 21 (type EXCL) for 16 ResAllocation-PT-R003C010-CTLFireability-04
lola: time limit : 1792 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C010-CTLFireability-00: CTL false CTL model checker
ResAllocation-PT-R003C010-CTLFireability-02: CONJ false CTL model checker
ResAllocation-PT-R003C010-CTLFireability-03: CTL false CTL model checker
ResAllocation-PT-R003C010-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C010-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C010-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R003C010-CTLFireability-09: F false state space / EG
ResAllocation-PT-R003C010-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R003C010-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C010-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C010-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C010-CTLFireability-04: CONJ 0 0 1 0 5 0 0 1

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 1/1792 1/32 ResAllocation-PT-R003C010-CTLFireability-04 145351 m, 29070 m/sec, 1633588 t fired, .

Time elapsed: 16 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 13
lola: FINISHED task # 21 (type EXCL) for ResAllocation-PT-R003C010-CTLFireability-04
lola: result : false
lola: markings : 147456
lola: fired transitions : 1698433
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 ResAllocation-PT-R003C010-CTLFireability-01
lola: time limit : 3584 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for ResAllocation-PT-R003C010-CTLFireability-01
lola: result : true
lola: markings : 2223
lola: fired transitions : 9250
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C010-CTLFireability-00: CTL false CTL model checker
ResAllocation-PT-R003C010-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C010-CTLFireability-02: CONJ false CTL model checker
ResAllocation-PT-R003C010-CTLFireability-03: CTL false CTL model checker
ResAllocation-PT-R003C010-CTLFireability-04: CONJ false CTL model checker
ResAllocation-PT-R003C010-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C010-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C010-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R003C010-CTLFireability-09: F false state space / EG
ResAllocation-PT-R003C010-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R003C010-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C010-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C010-CTLFireability-14: CTL true CTL model checker


Time elapsed: 16 secs. Pages in use: 4

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ResAllocation-PT-R003C010"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is ResAllocation-PT-R003C010, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r327-tall-167889199900690"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ResAllocation-PT-R003C010.tgz
mv ResAllocation-PT-R003C010 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;