About the Execution of LoLa+red for RefineWMG-PT-025026
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 4239.464 | 72845.00 | 75428.00 | 579.40 | ?TT?F??TFFFTTTTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r327-tall-167889199800618.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is RefineWMG-PT-025026, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r327-tall-167889199800618
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 512K
-rw-r--r-- 1 mcc users 7.3K Feb 26 16:06 CTLCardinality.txt
-rw-r--r-- 1 mcc users 81K Feb 26 16:06 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.6K Feb 26 16:06 CTLFireability.txt
-rw-r--r-- 1 mcc users 39K Feb 26 16:06 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.9K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:43 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Feb 25 16:43 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 16:43 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:43 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 26 16:08 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 110K Feb 26 16:08 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.5K Feb 26 16:07 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 86K Feb 26 16:07 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:43 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:43 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 7 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 56K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-00
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-01
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-02
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-03
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-04
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-05
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-06
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-07
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-08
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-09
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-10
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-11
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-12
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-13
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-14
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679053383234
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RefineWMG-PT-025026
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-17 11:43:04] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-17 11:43:04] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-17 11:43:05] [INFO ] Load time of PNML (sax parser for PT used): 42 ms
[2023-03-17 11:43:05] [INFO ] Transformed 129 places.
[2023-03-17 11:43:05] [INFO ] Transformed 103 transitions.
[2023-03-17 11:43:05] [INFO ] Parsed PT model containing 129 places and 103 transitions and 308 arcs in 108 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Support contains 80 out of 129 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 129/129 places, 103/103 transitions.
Applied a total of 0 rules in 11 ms. Remains 129 /129 variables (removed 0) and now considering 103/103 (removed 0) transitions.
// Phase 1: matrix 103 rows 129 cols
[2023-03-17 11:43:05] [INFO ] Computed 52 place invariants in 11 ms
[2023-03-17 11:43:05] [INFO ] Dead Transitions using invariants and state equation in 222 ms found 0 transitions.
[2023-03-17 11:43:05] [INFO ] Invariant cache hit.
[2023-03-17 11:43:05] [INFO ] Implicit Places using invariants in 75 ms returned []
[2023-03-17 11:43:05] [INFO ] Invariant cache hit.
[2023-03-17 11:43:05] [INFO ] Implicit Places using invariants and state equation in 96 ms returned []
Implicit Place search using SMT with State Equation took 173 ms to find 0 implicit places.
[2023-03-17 11:43:05] [INFO ] Invariant cache hit.
[2023-03-17 11:43:05] [INFO ] Dead Transitions using invariants and state equation in 93 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 524 ms. Remains : 129/129 places, 103/103 transitions.
Support contains 80 out of 129 places after structural reductions.
[2023-03-17 11:43:05] [INFO ] Flatten gal took : 27 ms
[2023-03-17 11:43:05] [INFO ] Flatten gal took : 13 ms
[2023-03-17 11:43:05] [INFO ] Input system was already deterministic with 103 transitions.
Support contains 79 out of 129 places (down from 80) after GAL structural reductions.
Incomplete random walk after 10010 steps, including 2 resets, run finished after 180 ms. (steps per millisecond=55 ) properties (out of 51) seen :32
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 39 ms. (steps per millisecond=25 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 19) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 3 ms. (steps per millisecond=333 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 3 ms. (steps per millisecond=333 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 3 ms. (steps per millisecond=333 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 3 ms. (steps per millisecond=333 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 18) seen :0
Running SMT prover for 18 properties.
[2023-03-17 11:43:06] [INFO ] Invariant cache hit.
[2023-03-17 11:43:06] [INFO ] [Real]Absence check using 52 positive place invariants in 7 ms returned sat
[2023-03-17 11:43:06] [INFO ] After 305ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:18
[2023-03-17 11:43:06] [INFO ] [Nat]Absence check using 52 positive place invariants in 9 ms returned sat
[2023-03-17 11:43:07] [INFO ] After 314ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :18
[2023-03-17 11:43:07] [INFO ] After 558ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :18
Attempting to minimize the solution found.
Minimization took 125 ms.
[2023-03-17 11:43:07] [INFO ] After 850ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :18
Finished Parikh walk after 464 steps, including 0 resets, run visited all 1 properties in 3 ms. (steps per millisecond=154 )
Parikh walk visited 18 properties in 25 ms.
[2023-03-17 11:43:07] [INFO ] Flatten gal took : 7 ms
[2023-03-17 11:43:07] [INFO ] Flatten gal took : 8 ms
[2023-03-17 11:43:07] [INFO ] Input system was already deterministic with 103 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 129/129 places, 103/103 transitions.
Applied a total of 0 rules in 10 ms. Remains 129 /129 variables (removed 0) and now considering 103/103 (removed 0) transitions.
[2023-03-17 11:43:07] [INFO ] Invariant cache hit.
[2023-03-17 11:43:07] [INFO ] Dead Transitions using invariants and state equation in 178 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 191 ms. Remains : 129/129 places, 103/103 transitions.
[2023-03-17 11:43:07] [INFO ] Flatten gal took : 9 ms
[2023-03-17 11:43:07] [INFO ] Flatten gal took : 6 ms
[2023-03-17 11:43:07] [INFO ] Input system was already deterministic with 103 transitions.
Starting structural reductions in LTL mode, iteration 0 : 129/129 places, 103/103 transitions.
Applied a total of 0 rules in 5 ms. Remains 129 /129 variables (removed 0) and now considering 103/103 (removed 0) transitions.
[2023-03-17 11:43:07] [INFO ] Invariant cache hit.
[2023-03-17 11:43:07] [INFO ] Dead Transitions using invariants and state equation in 89 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 94 ms. Remains : 129/129 places, 103/103 transitions.
[2023-03-17 11:43:07] [INFO ] Flatten gal took : 5 ms
[2023-03-17 11:43:07] [INFO ] Flatten gal took : 6 ms
[2023-03-17 11:43:07] [INFO ] Input system was already deterministic with 103 transitions.
Starting structural reductions in LTL mode, iteration 0 : 129/129 places, 103/103 transitions.
Applied a total of 0 rules in 4 ms. Remains 129 /129 variables (removed 0) and now considering 103/103 (removed 0) transitions.
[2023-03-17 11:43:07] [INFO ] Invariant cache hit.
[2023-03-17 11:43:08] [INFO ] Dead Transitions using invariants and state equation in 281 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 289 ms. Remains : 129/129 places, 103/103 transitions.
[2023-03-17 11:43:08] [INFO ] Flatten gal took : 5 ms
[2023-03-17 11:43:08] [INFO ] Flatten gal took : 5 ms
[2023-03-17 11:43:08] [INFO ] Input system was already deterministic with 103 transitions.
Starting structural reductions in LTL mode, iteration 0 : 129/129 places, 103/103 transitions.
Applied a total of 0 rules in 7 ms. Remains 129 /129 variables (removed 0) and now considering 103/103 (removed 0) transitions.
[2023-03-17 11:43:08] [INFO ] Invariant cache hit.
[2023-03-17 11:43:08] [INFO ] Dead Transitions using invariants and state equation in 94 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 103 ms. Remains : 129/129 places, 103/103 transitions.
[2023-03-17 11:43:08] [INFO ] Flatten gal took : 5 ms
[2023-03-17 11:43:08] [INFO ] Flatten gal took : 4 ms
[2023-03-17 11:43:08] [INFO ] Input system was already deterministic with 103 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 129/129 places, 103/103 transitions.
Graph (trivial) has 73 edges and 129 vertex of which 48 / 129 are part of one of the 24 SCC in 3 ms
Free SCC test removed 24 places
Ensure Unique test removed 24 transitions
Reduce isomorphic transitions removed 24 transitions.
Reduce places removed 24 places and 0 transitions.
Ensure Unique test removed 23 transitions
Reduce isomorphic transitions removed 23 transitions.
Iterating post reduction 0 with 23 rules applied. Total rules applied 24 place count 81 transition count 56
Performed 25 Post agglomeration using F-continuation condition.Transition count delta: 25
Deduced a syphon composed of 25 places in 0 ms
Reduce places removed 50 places and 0 transitions.
Iterating global reduction 1 with 75 rules applied. Total rules applied 99 place count 31 transition count 31
Drop transitions removed 22 transitions
Trivial Post-agglo rules discarded 22 transitions
Performed 22 trivial Post agglomeration. Transition count delta: 22
Iterating post reduction 1 with 22 rules applied. Total rules applied 121 place count 31 transition count 9
Reduce places removed 22 places and 0 transitions.
Iterating post reduction 2 with 22 rules applied. Total rules applied 143 place count 9 transition count 9
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 1 Pre rules applied. Total rules applied 143 place count 9 transition count 8
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 145 place count 8 transition count 8
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 147 place count 7 transition count 7
Applied a total of 147 rules in 15 ms. Remains 7 /129 variables (removed 122) and now considering 7/103 (removed 96) transitions.
// Phase 1: matrix 7 rows 7 cols
[2023-03-17 11:43:08] [INFO ] Computed 3 place invariants in 1 ms
[2023-03-17 11:43:08] [INFO ] Dead Transitions using invariants and state equation in 16 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 32 ms. Remains : 7/129 places, 7/103 transitions.
[2023-03-17 11:43:08] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:43:08] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:43:08] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 129/129 places, 103/103 transitions.
Applied a total of 0 rules in 3 ms. Remains 129 /129 variables (removed 0) and now considering 103/103 (removed 0) transitions.
// Phase 1: matrix 103 rows 129 cols
[2023-03-17 11:43:08] [INFO ] Computed 52 place invariants in 2 ms
[2023-03-17 11:43:08] [INFO ] Dead Transitions using invariants and state equation in 147 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 151 ms. Remains : 129/129 places, 103/103 transitions.
[2023-03-17 11:43:08] [INFO ] Flatten gal took : 5 ms
[2023-03-17 11:43:08] [INFO ] Flatten gal took : 5 ms
[2023-03-17 11:43:08] [INFO ] Input system was already deterministic with 103 transitions.
Starting structural reductions in LTL mode, iteration 0 : 129/129 places, 103/103 transitions.
Applied a total of 0 rules in 2 ms. Remains 129 /129 variables (removed 0) and now considering 103/103 (removed 0) transitions.
[2023-03-17 11:43:08] [INFO ] Invariant cache hit.
[2023-03-17 11:43:08] [INFO ] Dead Transitions using invariants and state equation in 55 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 58 ms. Remains : 129/129 places, 103/103 transitions.
[2023-03-17 11:43:08] [INFO ] Flatten gal took : 4 ms
[2023-03-17 11:43:08] [INFO ] Flatten gal took : 6 ms
[2023-03-17 11:43:08] [INFO ] Input system was already deterministic with 103 transitions.
Starting structural reductions in LTL mode, iteration 0 : 129/129 places, 103/103 transitions.
Applied a total of 0 rules in 5 ms. Remains 129 /129 variables (removed 0) and now considering 103/103 (removed 0) transitions.
[2023-03-17 11:43:08] [INFO ] Invariant cache hit.
[2023-03-17 11:43:08] [INFO ] Dead Transitions using invariants and state equation in 103 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 110 ms. Remains : 129/129 places, 103/103 transitions.
[2023-03-17 11:43:08] [INFO ] Flatten gal took : 4 ms
[2023-03-17 11:43:08] [INFO ] Flatten gal took : 4 ms
[2023-03-17 11:43:08] [INFO ] Input system was already deterministic with 103 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 129/129 places, 103/103 transitions.
Graph (trivial) has 74 edges and 129 vertex of which 50 / 129 are part of one of the 25 SCC in 0 ms
Free SCC test removed 25 places
Ensure Unique test removed 25 transitions
Reduce isomorphic transitions removed 25 transitions.
Reduce places removed 25 places and 0 transitions.
Ensure Unique test removed 24 transitions
Reduce isomorphic transitions removed 24 transitions.
Iterating post reduction 0 with 24 rules applied. Total rules applied 25 place count 79 transition count 54
Performed 24 Post agglomeration using F-continuation condition.Transition count delta: 24
Deduced a syphon composed of 24 places in 0 ms
Reduce places removed 48 places and 0 transitions.
Iterating global reduction 1 with 72 rules applied. Total rules applied 97 place count 31 transition count 30
Drop transitions removed 22 transitions
Trivial Post-agglo rules discarded 22 transitions
Performed 22 trivial Post agglomeration. Transition count delta: 22
Iterating post reduction 1 with 22 rules applied. Total rules applied 119 place count 31 transition count 8
Reduce places removed 22 places and 0 transitions.
Iterating post reduction 2 with 22 rules applied. Total rules applied 141 place count 9 transition count 8
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 1 Pre rules applied. Total rules applied 141 place count 9 transition count 7
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 143 place count 8 transition count 7
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 145 place count 7 transition count 6
Applied a total of 145 rules in 7 ms. Remains 7 /129 variables (removed 122) and now considering 6/103 (removed 97) transitions.
// Phase 1: matrix 6 rows 7 cols
[2023-03-17 11:43:08] [INFO ] Computed 3 place invariants in 0 ms
[2023-03-17 11:43:08] [INFO ] Dead Transitions using invariants and state equation in 34 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 42 ms. Remains : 7/129 places, 6/103 transitions.
[2023-03-17 11:43:08] [INFO ] Flatten gal took : 0 ms
[2023-03-17 11:43:08] [INFO ] Flatten gal took : 0 ms
[2023-03-17 11:43:08] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 129/129 places, 103/103 transitions.
Applied a total of 0 rules in 1 ms. Remains 129 /129 variables (removed 0) and now considering 103/103 (removed 0) transitions.
// Phase 1: matrix 103 rows 129 cols
[2023-03-17 11:43:08] [INFO ] Computed 52 place invariants in 1 ms
[2023-03-17 11:43:08] [INFO ] Dead Transitions using invariants and state equation in 63 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 65 ms. Remains : 129/129 places, 103/103 transitions.
[2023-03-17 11:43:08] [INFO ] Flatten gal took : 5 ms
[2023-03-17 11:43:08] [INFO ] Flatten gal took : 4 ms
[2023-03-17 11:43:08] [INFO ] Input system was already deterministic with 103 transitions.
Starting structural reductions in LTL mode, iteration 0 : 129/129 places, 103/103 transitions.
Applied a total of 0 rules in 2 ms. Remains 129 /129 variables (removed 0) and now considering 103/103 (removed 0) transitions.
[2023-03-17 11:43:08] [INFO ] Invariant cache hit.
[2023-03-17 11:43:09] [INFO ] Dead Transitions using invariants and state equation in 96 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 106 ms. Remains : 129/129 places, 103/103 transitions.
[2023-03-17 11:43:09] [INFO ] Flatten gal took : 5 ms
[2023-03-17 11:43:09] [INFO ] Flatten gal took : 5 ms
[2023-03-17 11:43:09] [INFO ] Input system was already deterministic with 103 transitions.
Starting structural reductions in LTL mode, iteration 0 : 129/129 places, 103/103 transitions.
Applied a total of 0 rules in 2 ms. Remains 129 /129 variables (removed 0) and now considering 103/103 (removed 0) transitions.
[2023-03-17 11:43:09] [INFO ] Invariant cache hit.
[2023-03-17 11:43:09] [INFO ] Dead Transitions using invariants and state equation in 110 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 114 ms. Remains : 129/129 places, 103/103 transitions.
[2023-03-17 11:43:09] [INFO ] Flatten gal took : 4 ms
[2023-03-17 11:43:09] [INFO ] Flatten gal took : 4 ms
[2023-03-17 11:43:09] [INFO ] Input system was already deterministic with 103 transitions.
Starting structural reductions in LTL mode, iteration 0 : 129/129 places, 103/103 transitions.
Applied a total of 0 rules in 3 ms. Remains 129 /129 variables (removed 0) and now considering 103/103 (removed 0) transitions.
[2023-03-17 11:43:09] [INFO ] Invariant cache hit.
[2023-03-17 11:43:09] [INFO ] Dead Transitions using invariants and state equation in 65 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 68 ms. Remains : 129/129 places, 103/103 transitions.
[2023-03-17 11:43:09] [INFO ] Flatten gal took : 4 ms
[2023-03-17 11:43:09] [INFO ] Flatten gal took : 5 ms
[2023-03-17 11:43:09] [INFO ] Input system was already deterministic with 103 transitions.
Starting structural reductions in LTL mode, iteration 0 : 129/129 places, 103/103 transitions.
Applied a total of 0 rules in 2 ms. Remains 129 /129 variables (removed 0) and now considering 103/103 (removed 0) transitions.
[2023-03-17 11:43:09] [INFO ] Invariant cache hit.
[2023-03-17 11:43:09] [INFO ] Dead Transitions using invariants and state equation in 107 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 118 ms. Remains : 129/129 places, 103/103 transitions.
[2023-03-17 11:43:09] [INFO ] Flatten gal took : 4 ms
[2023-03-17 11:43:09] [INFO ] Flatten gal took : 4 ms
[2023-03-17 11:43:09] [INFO ] Input system was already deterministic with 103 transitions.
Starting structural reductions in LTL mode, iteration 0 : 129/129 places, 103/103 transitions.
Applied a total of 0 rules in 1 ms. Remains 129 /129 variables (removed 0) and now considering 103/103 (removed 0) transitions.
[2023-03-17 11:43:09] [INFO ] Invariant cache hit.
[2023-03-17 11:43:09] [INFO ] Dead Transitions using invariants and state equation in 102 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 105 ms. Remains : 129/129 places, 103/103 transitions.
[2023-03-17 11:43:09] [INFO ] Flatten gal took : 4 ms
[2023-03-17 11:43:09] [INFO ] Flatten gal took : 4 ms
[2023-03-17 11:43:09] [INFO ] Input system was already deterministic with 103 transitions.
Starting structural reductions in LTL mode, iteration 0 : 129/129 places, 103/103 transitions.
Applied a total of 0 rules in 1 ms. Remains 129 /129 variables (removed 0) and now considering 103/103 (removed 0) transitions.
[2023-03-17 11:43:09] [INFO ] Invariant cache hit.
[2023-03-17 11:43:09] [INFO ] Dead Transitions using invariants and state equation in 150 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 154 ms. Remains : 129/129 places, 103/103 transitions.
[2023-03-17 11:43:09] [INFO ] Flatten gal took : 3 ms
[2023-03-17 11:43:09] [INFO ] Flatten gal took : 21 ms
[2023-03-17 11:43:09] [INFO ] Input system was already deterministic with 103 transitions.
[2023-03-17 11:43:09] [INFO ] Flatten gal took : 4 ms
[2023-03-17 11:43:09] [INFO ] Flatten gal took : 4 ms
[2023-03-17 11:43:09] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-17 11:43:09] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 129 places, 103 transitions and 308 arcs took 1 ms.
Total runtime 5019 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT RefineWMG-PT-025026
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability
FORMULA RefineWMG-PT-025026-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-025026-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-025026-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-025026-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-025026-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-025026-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-025026-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-025026-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-025026-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-025026-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-025026-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-025026-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679053456079
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 20 (type EXCL) for 17 RefineWMG-PT-025026-CTLFireability-03
lola: time limit : 133 sec
lola: memory limit: 32 pages
lola: FINISHED task # 20 (type EXCL) for RefineWMG-PT-025026-CTLFireability-03
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 RefineWMG-PT-025026-CTLFireability-00
lola: time limit : 138 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 75 (type FNDP) for 39 RefineWMG-PT-025026-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 76 (type EQUN) for 39 RefineWMG-PT-025026-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 78 (type SRCH) for 39 RefineWMG-PT-025026-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 75 (type FNDP) for RefineWMG-PT-025026-CTLFireability-09
lola: result : true
lola: fired transitions : 25
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: CANCELED task # 76 (type EQUN) for RefineWMG-PT-025026-CTLFireability-09 (obsolete)
lola: CANCELED task # 78 (type SRCH) for RefineWMG-PT-025026-CTLFireability-09 (obsolete)
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 78 (type SRCH) for RefineWMG-PT-025026-CTLFireability-09
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
sara: try reading problem file /home/mcc/execution/375/CTLFireability-76.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 79 (type FNDP) for 6 RefineWMG-PT-025026-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 80 (type EQUN) for 6 RefineWMG-PT-025026-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 82 (type SRCH) for 6 RefineWMG-PT-025026-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 82 (type SRCH) for RefineWMG-PT-025026-CTLFireability-02
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 76 (type EQUN) for RefineWMG-PT-025026-CTLFireability-09
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 79 (type FNDP) for RefineWMG-PT-025026-CTLFireability-02
lola: result : true
lola: fired transitions : 25
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: CANCELED task # 80 (type EQUN) for RefineWMG-PT-025026-CTLFireability-02 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
sara: try reading problem file /home/mcc/execution/375/CTLFireability-80.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 80 (type EQUN) for RefineWMG-PT-025026-CTLFireability-02
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-025026-CTLFireability-09: CONJ false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-025026-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-02: DISJ 0 2 0 0 6 0 0 1
RefineWMG-PT-025026-CTLFireability-03: DISJ 0 1 0 0 3 0 0 0
RefineWMG-PT-025026-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-08: AFAG 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
RefineWMG-PT-025026-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
RefineWMG-PT-025026-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/200 14/32 RefineWMG-PT-025026-CTLFireability-00 2489583 m, 497916 m/sec, 5282383 t fired, .
Time elapsed: 5 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-025026-CTLFireability-09: CONJ false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-025026-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-02: DISJ 0 2 0 0 6 0 0 1
RefineWMG-PT-025026-CTLFireability-03: DISJ 0 1 0 0 3 0 0 0
RefineWMG-PT-025026-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-08: AFAG 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
RefineWMG-PT-025026-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
RefineWMG-PT-025026-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/200 27/32 RefineWMG-PT-025026-CTLFireability-00 4857300 m, 473543 m/sec, 10153425 t fired, .
Time elapsed: 10 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 1 (type EXCL) for RefineWMG-PT-025026-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-025026-CTLFireability-09: CONJ false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-025026-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-025026-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-02: DISJ 0 2 0 0 6 0 0 1
RefineWMG-PT-025026-CTLFireability-03: DISJ 0 1 0 0 3 0 0 0
RefineWMG-PT-025026-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-08: AFAG 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
RefineWMG-PT-025026-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
RefineWMG-PT-025026-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 15 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 72 (type EXCL) for 46 RefineWMG-PT-025026-CTLFireability-10
lola: time limit : 210 sec
lola: memory limit: 32 pages
lola: FINISHED task # 72 (type EXCL) for RefineWMG-PT-025026-CTLFireability-10
lola: result : true
lola: markings : 27
lola: fired transitions : 26
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 70 (type EXCL) for 69 RefineWMG-PT-025026-CTLFireability-15
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: FINISHED task # 70 (type EXCL) for RefineWMG-PT-025026-CTLFireability-15
lola: result : true
lola: markings : 701
lola: fired transitions : 726
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 67 (type EXCL) for 66 RefineWMG-PT-025026-CTLFireability-14
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: FINISHED task # 67 (type EXCL) for RefineWMG-PT-025026-CTLFireability-14
lola: result : true
lola: markings : 26
lola: fired transitions : 25
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 64 (type EXCL) for 63 RefineWMG-PT-025026-CTLFireability-13
lola: time limit : 256 sec
lola: memory limit: 32 pages
lola: FINISHED task # 64 (type EXCL) for RefineWMG-PT-025026-CTLFireability-13
lola: result : true
lola: markings : 26
lola: fired transitions : 77
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 61 (type EXCL) for 60 RefineWMG-PT-025026-CTLFireability-12
lola: time limit : 275 sec
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lola: FINISHED task # 61 (type EXCL) for RefineWMG-PT-025026-CTLFireability-12
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 58 (type EXCL) for 53 RefineWMG-PT-025026-CTLFireability-11
lola: time limit : 298 sec
lola: memory limit: 32 pages
lola: FINISHED task # 58 (type EXCL) for RefineWMG-PT-025026-CTLFireability-11
lola: result : true
lola: markings : 26
lola: fired transitions : 25
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 56 (type EXCL) for 53 RefineWMG-PT-025026-CTLFireability-11
lola: time limit : 325 sec
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lola: FINISHED task # 56 (type EXCL) for RefineWMG-PT-025026-CTLFireability-11
lola: result : true
lola: markings : 398
lola: fired transitions : 1100
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 49 (type EXCL) for 46 RefineWMG-PT-025026-CTLFireability-10
lola: time limit : 358 sec
lola: memory limit: 32 pages
lola: FINISHED task # 49 (type EXCL) for RefineWMG-PT-025026-CTLFireability-10
lola: result : false
lola: markings : 2065
lola: fired transitions : 3742
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 33 RefineWMG-PT-025026-CTLFireability-07
lola: time limit : 398 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for RefineWMG-PT-025026-CTLFireability-07
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 RefineWMG-PT-025026-CTLFireability-06
lola: time limit : 448 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-025026-CTLFireability-07: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-09: CONJ false findpath
RefineWMG-PT-025026-CTLFireability-10: DISJ false DISJ
RefineWMG-PT-025026-CTLFireability-11: CONJ true CONJ
RefineWMG-PT-025026-CTLFireability-12: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-13: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-14: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RefineWMG-PT-025026-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-02: DISJ 0 2 0 0 6 0 0 1
RefineWMG-PT-025026-CTLFireability-03: DISJ 0 1 0 0 3 0 0 0
RefineWMG-PT-025026-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-08: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 5/448 18/32 RefineWMG-PT-025026-CTLFireability-06 2993232 m, 598646 m/sec, 4547373 t fired, .
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lola: CANCELED task # 31 (type EXCL) for RefineWMG-PT-025026-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-025026-CTLFireability-07: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-09: CONJ false findpath
RefineWMG-PT-025026-CTLFireability-10: DISJ false DISJ
RefineWMG-PT-025026-CTLFireability-11: CONJ true CONJ
RefineWMG-PT-025026-CTLFireability-12: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-13: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-14: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RefineWMG-PT-025026-CTLFireability-02: DISJ 0 2 0 0 6 0 0 1
RefineWMG-PT-025026-CTLFireability-03: DISJ 0 1 0 0 3 0 0 0
RefineWMG-PT-025026-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-025026-CTLFireability-08: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: LAUNCH task # 28 (type EXCL) for 27 RefineWMG-PT-025026-CTLFireability-05
lola: time limit : 510 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-025026-CTLFireability-07: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-09: CONJ false findpath
RefineWMG-PT-025026-CTLFireability-10: DISJ false DISJ
RefineWMG-PT-025026-CTLFireability-11: CONJ true CONJ
RefineWMG-PT-025026-CTLFireability-12: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-13: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-14: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RefineWMG-PT-025026-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-02: DISJ 0 2 0 0 6 0 0 1
RefineWMG-PT-025026-CTLFireability-03: DISJ 0 1 0 0 3 0 0 0
RefineWMG-PT-025026-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-025026-CTLFireability-08: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 5/510 8/32 RefineWMG-PT-025026-CTLFireability-05 1385275 m, 277055 m/sec, 2104527 t fired, .
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RefineWMG-PT-025026-CTLFireability-07: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-09: CONJ false findpath
RefineWMG-PT-025026-CTLFireability-10: DISJ false DISJ
RefineWMG-PT-025026-CTLFireability-11: CONJ true CONJ
RefineWMG-PT-025026-CTLFireability-12: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-13: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-14: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-15: CTL true CTL model checker
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RefineWMG-PT-025026-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
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RefineWMG-PT-025026-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-025026-CTLFireability-08: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 10/510 16/32 RefineWMG-PT-025026-CTLFireability-05 2666024 m, 256149 m/sec, 4050261 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-025026-CTLFireability-07: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-09: CONJ false findpath
RefineWMG-PT-025026-CTLFireability-10: DISJ false DISJ
RefineWMG-PT-025026-CTLFireability-11: CONJ true CONJ
RefineWMG-PT-025026-CTLFireability-12: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-13: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-14: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RefineWMG-PT-025026-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-02: DISJ 0 2 0 0 6 0 0 1
RefineWMG-PT-025026-CTLFireability-03: DISJ 0 1 0 0 3 0 0 0
RefineWMG-PT-025026-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-025026-CTLFireability-08: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 15/510 23/32 RefineWMG-PT-025026-CTLFireability-05 3914784 m, 249752 m/sec, 5947421 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-025026-CTLFireability-07: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-09: CONJ false findpath
RefineWMG-PT-025026-CTLFireability-10: DISJ false DISJ
RefineWMG-PT-025026-CTLFireability-11: CONJ true CONJ
RefineWMG-PT-025026-CTLFireability-12: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-13: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-14: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RefineWMG-PT-025026-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-02: DISJ 0 2 0 0 6 0 0 1
RefineWMG-PT-025026-CTLFireability-03: DISJ 0 1 0 0 3 0 0 0
RefineWMG-PT-025026-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-025026-CTLFireability-08: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 20/510 30/32 RefineWMG-PT-025026-CTLFireability-05 5116166 m, 240276 m/sec, 7772606 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-025026-CTLFireability-07: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-09: CONJ false findpath
RefineWMG-PT-025026-CTLFireability-10: DISJ false DISJ
RefineWMG-PT-025026-CTLFireability-11: CONJ true CONJ
RefineWMG-PT-025026-CTLFireability-12: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-13: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-14: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RefineWMG-PT-025026-CTLFireability-02: DISJ 0 2 0 0 6 0 0 1
RefineWMG-PT-025026-CTLFireability-03: DISJ 0 1 0 0 3 0 0 0
RefineWMG-PT-025026-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-025026-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-025026-CTLFireability-08: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: LAUNCH task # 15 (type EXCL) for 6 RefineWMG-PT-025026-CTLFireability-02
lola: time limit : 591 sec
lola: memory limit: 32 pages
lola: FINISHED task # 15 (type EXCL) for RefineWMG-PT-025026-CTLFireability-02
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 RefineWMG-PT-025026-CTLFireability-01
lola: time limit : 710 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for RefineWMG-PT-025026-CTLFireability-01
lola: result : true
lola: markings : 1438
lola: fired transitions : 2694
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 83 (type EXCL) for 24 RefineWMG-PT-025026-CTLFireability-04
lola: time limit : 887 sec
lola: memory limit: 32 pages
lola: FINISHED task # 83 (type EXCL) for RefineWMG-PT-025026-CTLFireability-04
lola: result : true
lola: markings : 432
lola: fired transitions : 1044
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 37 (type EXCL) for 36 RefineWMG-PT-025026-CTLFireability-08
lola: time limit : 1183 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for RefineWMG-PT-025026-CTLFireability-08
lola: result : false
lola: markings : 7
lola: fired transitions : 14
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 73 (type EXCL) for 6 RefineWMG-PT-025026-CTLFireability-02
lola: time limit : 1775 sec
lola: memory limit: 32 pages
lola: FINISHED task # 73 (type EXCL) for RefineWMG-PT-025026-CTLFireability-02
lola: result : true
lola: markings : 218835
lola: fired transitions : 1209477
lola: time used : 1.000000
lola: memory pages used : 2
lola: LAUNCH task # 22 (type EXCL) for 17 RefineWMG-PT-025026-CTLFireability-03
lola: time limit : 3549 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-025026-CTLFireability-01: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-02: DISJ true LTL model checker
RefineWMG-PT-025026-CTLFireability-04: EFAG false tscc_search
RefineWMG-PT-025026-CTLFireability-07: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-08: AFAG false CTL model checker
RefineWMG-PT-025026-CTLFireability-09: CONJ false findpath
RefineWMG-PT-025026-CTLFireability-10: DISJ false DISJ
RefineWMG-PT-025026-CTLFireability-11: CONJ true CONJ
RefineWMG-PT-025026-CTLFireability-12: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-13: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-14: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-025026-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-025026-CTLFireability-03: DISJ 0 0 1 0 3 0 0 0
RefineWMG-PT-025026-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-025026-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 4/3549 13/32 RefineWMG-PT-025026-CTLFireability-03 2888552 m, 577710 m/sec, 10602786 t fired, .
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RefineWMG-PT-025026-CTLFireability-01: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-02: DISJ true LTL model checker
RefineWMG-PT-025026-CTLFireability-04: EFAG false tscc_search
RefineWMG-PT-025026-CTLFireability-07: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-08: AFAG false CTL model checker
RefineWMG-PT-025026-CTLFireability-09: CONJ false findpath
RefineWMG-PT-025026-CTLFireability-10: DISJ false DISJ
RefineWMG-PT-025026-CTLFireability-11: CONJ true CONJ
RefineWMG-PT-025026-CTLFireability-12: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-13: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-14: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-15: CTL true CTL model checker
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RefineWMG-PT-025026-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-025026-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
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22 CTL EXCL 9/3549 25/32 RefineWMG-PT-025026-CTLFireability-03 5905766 m, 603442 m/sec, 21675836 t fired, .
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lola: CANCELED task # 22 (type EXCL) for RefineWMG-PT-025026-CTLFireability-03 (memory limit exceeded)
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RefineWMG-PT-025026-CTLFireability-01: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-02: DISJ true LTL model checker
RefineWMG-PT-025026-CTLFireability-04: EFAG false tscc_search
RefineWMG-PT-025026-CTLFireability-07: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-08: AFAG false CTL model checker
RefineWMG-PT-025026-CTLFireability-09: CONJ false findpath
RefineWMG-PT-025026-CTLFireability-10: DISJ false DISJ
RefineWMG-PT-025026-CTLFireability-11: CONJ true CONJ
RefineWMG-PT-025026-CTLFireability-12: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-13: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-14: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-15: CTL true CTL model checker
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RefineWMG-PT-025026-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-025026-CTLFireability-00: CTL unknown AGGR
RefineWMG-PT-025026-CTLFireability-01: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-02: DISJ true LTL model checker
RefineWMG-PT-025026-CTLFireability-03: DISJ unknown DISJ
RefineWMG-PT-025026-CTLFireability-04: EFAG false tscc_search
RefineWMG-PT-025026-CTLFireability-05: CTL unknown AGGR
RefineWMG-PT-025026-CTLFireability-06: CTL unknown AGGR
RefineWMG-PT-025026-CTLFireability-07: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-08: AFAG false CTL model checker
RefineWMG-PT-025026-CTLFireability-09: CONJ false findpath
RefineWMG-PT-025026-CTLFireability-10: DISJ false DISJ
RefineWMG-PT-025026-CTLFireability-11: CONJ true CONJ
RefineWMG-PT-025026-CTLFireability-12: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-13: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-14: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-15: CTL true CTL model checker
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RefineWMG-PT-025026"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is RefineWMG-PT-025026, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r327-tall-167889199800618"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/RefineWMG-PT-025026.tgz
mv RefineWMG-PT-025026 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;