Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r327-tall-167889199800602.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...........................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is RefineWMG-PT-015016, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r327-tall-167889199800602
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 440K
-rw-r--r-- 1 mcc users 5.7K Feb 26 16:04 CTLCardinality.txt
-rw-r--r-- 1 mcc users 55K Feb 26 16:04 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.3K Feb 26 16:02 CTLFireability.txt
-rw-r--r-- 1 mcc users 35K Feb 26 16:02 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.9K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 16:43 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Feb 25 16:43 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 16:43 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:43 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 26 16:05 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 119K Feb 26 16:05 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.8K Feb 26 16:04 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 68K Feb 26 16:04 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:43 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:43 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 7 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 35K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RefineWMG-PT-015016-CTLFireability-00
FORMULA_NAME RefineWMG-PT-015016-CTLFireability-01
FORMULA_NAME RefineWMG-PT-015016-CTLFireability-02
FORMULA_NAME RefineWMG-PT-015016-CTLFireability-03
FORMULA_NAME RefineWMG-PT-015016-CTLFireability-04
FORMULA_NAME RefineWMG-PT-015016-CTLFireability-05
FORMULA_NAME RefineWMG-PT-015016-CTLFireability-06
FORMULA_NAME RefineWMG-PT-015016-CTLFireability-07
FORMULA_NAME RefineWMG-PT-015016-CTLFireability-08
FORMULA_NAME RefineWMG-PT-015016-CTLFireability-09
FORMULA_NAME RefineWMG-PT-015016-CTLFireability-10
FORMULA_NAME RefineWMG-PT-015016-CTLFireability-11
FORMULA_NAME RefineWMG-PT-015016-CTLFireability-12
FORMULA_NAME RefineWMG-PT-015016-CTLFireability-13
FORMULA_NAME RefineWMG-PT-015016-CTLFireability-14
FORMULA_NAME RefineWMG-PT-015016-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679053121148

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RefineWMG-PT-015016
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-17 11:38:42] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-17 11:38:42] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-17 11:38:42] [INFO ] Load time of PNML (sax parser for PT used): 30 ms
[2023-03-17 11:38:42] [INFO ] Transformed 79 places.
[2023-03-17 11:38:42] [INFO ] Transformed 63 transitions.
[2023-03-17 11:38:42] [INFO ] Parsed PT model containing 79 places and 63 transitions and 188 arcs in 85 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 8 ms.
Support contains 58 out of 79 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 79/79 places, 63/63 transitions.
Applied a total of 0 rules in 9 ms. Remains 79 /79 variables (removed 0) and now considering 63/63 (removed 0) transitions.
// Phase 1: matrix 63 rows 79 cols
[2023-03-17 11:38:42] [INFO ] Computed 32 place invariants in 9 ms
[2023-03-17 11:38:43] [INFO ] Dead Transitions using invariants and state equation in 477 ms found 0 transitions.
[2023-03-17 11:38:43] [INFO ] Invariant cache hit.
[2023-03-17 11:38:43] [INFO ] Implicit Places using invariants in 47 ms returned []
[2023-03-17 11:38:43] [INFO ] Invariant cache hit.
[2023-03-17 11:38:43] [INFO ] Implicit Places using invariants and state equation in 69 ms returned []
Implicit Place search using SMT with State Equation took 119 ms to find 0 implicit places.
[2023-03-17 11:38:43] [INFO ] Invariant cache hit.
[2023-03-17 11:38:43] [INFO ] Dead Transitions using invariants and state equation in 49 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 678 ms. Remains : 79/79 places, 63/63 transitions.
Support contains 58 out of 79 places after structural reductions.
[2023-03-17 11:38:43] [INFO ] Flatten gal took : 21 ms
[2023-03-17 11:38:43] [INFO ] Flatten gal took : 8 ms
[2023-03-17 11:38:43] [INFO ] Input system was already deterministic with 63 transitions.
Incomplete random walk after 10002 steps, including 2 resets, run finished after 127 ms. (steps per millisecond=78 ) properties (out of 49) seen :41
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=384 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 51 ms. (steps per millisecond=196 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 41 ms. (steps per millisecond=243 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=312 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=384 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=434 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=434 ) properties (out of 8) seen :0
Running SMT prover for 8 properties.
[2023-03-17 11:38:43] [INFO ] Invariant cache hit.
[2023-03-17 11:38:44] [INFO ] [Real]Absence check using 32 positive place invariants in 4 ms returned sat
[2023-03-17 11:38:44] [INFO ] After 138ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:8
[2023-03-17 11:38:44] [INFO ] [Nat]Absence check using 32 positive place invariants in 5 ms returned sat
[2023-03-17 11:38:44] [INFO ] After 104ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :8
[2023-03-17 11:38:44] [INFO ] After 199ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :8
Attempting to minimize the solution found.
Minimization took 57 ms.
[2023-03-17 11:38:44] [INFO ] After 321ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :8
Finished Parikh walk after 125 steps, including 0 resets, run visited all 8 properties in 9 ms. (steps per millisecond=13 )
Parikh walk visited 8 properties in 11 ms.
[2023-03-17 11:38:44] [INFO ] Flatten gal took : 10 ms
[2023-03-17 11:38:44] [INFO ] Flatten gal took : 13 ms
[2023-03-17 11:38:44] [INFO ] Input system was already deterministic with 63 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 79/79 places, 63/63 transitions.
Graph (trivial) has 39 edges and 79 vertex of which 26 / 79 are part of one of the 13 SCC in 2 ms
Free SCC test removed 13 places
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Reduce places removed 13 places and 0 transitions.
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Iterating post reduction 0 with 12 rules applied. Total rules applied 13 place count 53 transition count 38
Performed 13 Post agglomeration using F-continuation condition.Transition count delta: 13
Deduced a syphon composed of 13 places in 0 ms
Reduce places removed 26 places and 0 transitions.
Iterating global reduction 1 with 39 rules applied. Total rules applied 52 place count 27 transition count 25
Drop transitions removed 7 transitions
Trivial Post-agglo rules discarded 7 transitions
Performed 7 trivial Post agglomeration. Transition count delta: 7
Iterating post reduction 1 with 7 rules applied. Total rules applied 59 place count 27 transition count 18
Reduce places removed 7 places and 0 transitions.
Iterating post reduction 2 with 7 rules applied. Total rules applied 66 place count 20 transition count 18
Performed 3 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 3 Pre rules applied. Total rules applied 66 place count 20 transition count 15
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 3 with 6 rules applied. Total rules applied 72 place count 17 transition count 15
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 74 place count 16 transition count 14
Applied a total of 74 rules in 13 ms. Remains 16 /79 variables (removed 63) and now considering 14/63 (removed 49) transitions.
// Phase 1: matrix 14 rows 16 cols
[2023-03-17 11:38:44] [INFO ] Computed 6 place invariants in 0 ms
[2023-03-17 11:38:44] [INFO ] Dead Transitions using invariants and state equation in 19 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 33 ms. Remains : 16/79 places, 14/63 transitions.
[2023-03-17 11:38:44] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:38:44] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:38:44] [INFO ] Input system was already deterministic with 14 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 79/79 places, 63/63 transitions.
Graph (trivial) has 42 edges and 79 vertex of which 28 / 79 are part of one of the 14 SCC in 0 ms
Free SCC test removed 14 places
Ensure Unique test removed 14 transitions
Reduce isomorphic transitions removed 14 transitions.
Reduce places removed 14 places and 0 transitions.
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 0 with 13 rules applied. Total rules applied 14 place count 51 transition count 36
Performed 14 Post agglomeration using F-continuation condition.Transition count delta: 14
Deduced a syphon composed of 14 places in 0 ms
Reduce places removed 28 places and 0 transitions.
Iterating global reduction 1 with 42 rules applied. Total rules applied 56 place count 23 transition count 22
Drop transitions removed 11 transitions
Trivial Post-agglo rules discarded 11 transitions
Performed 11 trivial Post agglomeration. Transition count delta: 11
Iterating post reduction 1 with 11 rules applied. Total rules applied 67 place count 23 transition count 11
Reduce places removed 11 places and 0 transitions.
Iterating post reduction 2 with 11 rules applied. Total rules applied 78 place count 12 transition count 11
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 1 Pre rules applied. Total rules applied 78 place count 12 transition count 10
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 80 place count 11 transition count 10
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 82 place count 10 transition count 9
Applied a total of 82 rules in 8 ms. Remains 10 /79 variables (removed 69) and now considering 9/63 (removed 54) transitions.
// Phase 1: matrix 9 rows 10 cols
[2023-03-17 11:38:44] [INFO ] Computed 4 place invariants in 0 ms
[2023-03-17 11:38:44] [INFO ] Dead Transitions using invariants and state equation in 19 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 29 ms. Remains : 10/79 places, 9/63 transitions.
[2023-03-17 11:38:44] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:38:44] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:38:44] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 79/79 places, 63/63 transitions.
Graph (trivial) has 44 edges and 79 vertex of which 30 / 79 are part of one of the 15 SCC in 1 ms
Free SCC test removed 15 places
Ensure Unique test removed 15 transitions
Reduce isomorphic transitions removed 15 transitions.
Reduce places removed 15 places and 0 transitions.
Ensure Unique test removed 14 transitions
Reduce isomorphic transitions removed 14 transitions.
Iterating post reduction 0 with 14 rules applied. Total rules applied 15 place count 49 transition count 34
Performed 14 Post agglomeration using F-continuation condition.Transition count delta: 14
Deduced a syphon composed of 14 places in 0 ms
Reduce places removed 28 places and 0 transitions.
Iterating global reduction 1 with 42 rules applied. Total rules applied 57 place count 21 transition count 20
Drop transitions removed 12 transitions
Trivial Post-agglo rules discarded 12 transitions
Performed 12 trivial Post agglomeration. Transition count delta: 12
Iterating post reduction 1 with 12 rules applied. Total rules applied 69 place count 21 transition count 8
Reduce places removed 12 places and 0 transitions.
Iterating post reduction 2 with 12 rules applied. Total rules applied 81 place count 9 transition count 8
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 1 Pre rules applied. Total rules applied 81 place count 9 transition count 7
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 83 place count 8 transition count 7
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 85 place count 7 transition count 6
Applied a total of 85 rules in 7 ms. Remains 7 /79 variables (removed 72) and now considering 6/63 (removed 57) transitions.
// Phase 1: matrix 6 rows 7 cols
[2023-03-17 11:38:44] [INFO ] Computed 3 place invariants in 1 ms
[2023-03-17 11:38:44] [INFO ] Dead Transitions using invariants and state equation in 18 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 26 ms. Remains : 7/79 places, 6/63 transitions.
[2023-03-17 11:38:44] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:38:44] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:38:44] [INFO ] Input system was already deterministic with 6 transitions.
Finished random walk after 5 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=5 )
FORMULA RefineWMG-PT-015016-CTLFireability-02 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in SI_CTL mode, iteration 0 : 79/79 places, 63/63 transitions.
Graph (trivial) has 19 edges and 79 vertex of which 10 / 79 are part of one of the 5 SCC in 0 ms
Free SCC test removed 5 places
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Reduce places removed 5 places and 0 transitions.
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 0 with 4 rules applied. Total rules applied 5 place count 69 transition count 54
Performed 9 Post agglomeration using F-continuation condition.Transition count delta: 9
Deduced a syphon composed of 9 places in 0 ms
Reduce places removed 18 places and 0 transitions.
Iterating global reduction 1 with 27 rules applied. Total rules applied 32 place count 51 transition count 45
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 1 with 2 rules applied. Total rules applied 34 place count 51 transition count 43
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 36 place count 49 transition count 43
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 1 Pre rules applied. Total rules applied 36 place count 49 transition count 42
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 38 place count 48 transition count 42
Applied a total of 38 rules in 9 ms. Remains 48 /79 variables (removed 31) and now considering 42/63 (removed 21) transitions.
// Phase 1: matrix 42 rows 48 cols
[2023-03-17 11:38:44] [INFO ] Computed 18 place invariants in 1 ms
[2023-03-17 11:38:44] [INFO ] Dead Transitions using invariants and state equation in 44 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 53 ms. Remains : 48/79 places, 42/63 transitions.
[2023-03-17 11:38:44] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:38:44] [INFO ] Flatten gal took : 3 ms
[2023-03-17 11:38:44] [INFO ] Input system was already deterministic with 42 transitions.
Starting structural reductions in LTL mode, iteration 0 : 79/79 places, 63/63 transitions.
Applied a total of 0 rules in 2 ms. Remains 79 /79 variables (removed 0) and now considering 63/63 (removed 0) transitions.
// Phase 1: matrix 63 rows 79 cols
[2023-03-17 11:38:44] [INFO ] Computed 32 place invariants in 1 ms
[2023-03-17 11:38:44] [INFO ] Dead Transitions using invariants and state equation in 43 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 45 ms. Remains : 79/79 places, 63/63 transitions.
[2023-03-17 11:38:44] [INFO ] Flatten gal took : 4 ms
[2023-03-17 11:38:44] [INFO ] Flatten gal took : 3 ms
[2023-03-17 11:38:44] [INFO ] Input system was already deterministic with 63 transitions.
Starting structural reductions in LTL mode, iteration 0 : 79/79 places, 63/63 transitions.
Applied a total of 0 rules in 1 ms. Remains 79 /79 variables (removed 0) and now considering 63/63 (removed 0) transitions.
[2023-03-17 11:38:44] [INFO ] Invariant cache hit.
[2023-03-17 11:38:44] [INFO ] Dead Transitions using invariants and state equation in 53 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 56 ms. Remains : 79/79 places, 63/63 transitions.
[2023-03-17 11:38:44] [INFO ] Flatten gal took : 3 ms
[2023-03-17 11:38:44] [INFO ] Flatten gal took : 3 ms
[2023-03-17 11:38:44] [INFO ] Input system was already deterministic with 63 transitions.
Starting structural reductions in LTL mode, iteration 0 : 79/79 places, 63/63 transitions.
Applied a total of 0 rules in 1 ms. Remains 79 /79 variables (removed 0) and now considering 63/63 (removed 0) transitions.
[2023-03-17 11:38:44] [INFO ] Invariant cache hit.
[2023-03-17 11:38:44] [INFO ] Dead Transitions using invariants and state equation in 40 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 41 ms. Remains : 79/79 places, 63/63 transitions.
[2023-03-17 11:38:44] [INFO ] Flatten gal took : 3 ms
[2023-03-17 11:38:44] [INFO ] Flatten gal took : 4 ms
[2023-03-17 11:38:44] [INFO ] Input system was already deterministic with 63 transitions.
Starting structural reductions in LTL mode, iteration 0 : 79/79 places, 63/63 transitions.
Applied a total of 0 rules in 2 ms. Remains 79 /79 variables (removed 0) and now considering 63/63 (removed 0) transitions.
[2023-03-17 11:38:44] [INFO ] Invariant cache hit.
[2023-03-17 11:38:44] [INFO ] Dead Transitions using invariants and state equation in 37 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 40 ms. Remains : 79/79 places, 63/63 transitions.
[2023-03-17 11:38:44] [INFO ] Flatten gal took : 3 ms
[2023-03-17 11:38:44] [INFO ] Flatten gal took : 3 ms
[2023-03-17 11:38:44] [INFO ] Input system was already deterministic with 63 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 79/79 places, 63/63 transitions.
Graph (trivial) has 33 edges and 79 vertex of which 22 / 79 are part of one of the 11 SCC in 1 ms
Free SCC test removed 11 places
Ensure Unique test removed 11 transitions
Reduce isomorphic transitions removed 11 transitions.
Reduce places removed 11 places and 0 transitions.
Ensure Unique test removed 10 transitions
Reduce isomorphic transitions removed 10 transitions.
Iterating post reduction 0 with 10 rules applied. Total rules applied 11 place count 57 transition count 42
Performed 11 Post agglomeration using F-continuation condition.Transition count delta: 11
Deduced a syphon composed of 11 places in 0 ms
Reduce places removed 22 places and 0 transitions.
Iterating global reduction 1 with 33 rules applied. Total rules applied 44 place count 35 transition count 31
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded 5 transitions
Performed 5 trivial Post agglomeration. Transition count delta: 5
Iterating post reduction 1 with 5 rules applied. Total rules applied 49 place count 35 transition count 26
Reduce places removed 5 places and 0 transitions.
Iterating post reduction 2 with 5 rules applied. Total rules applied 54 place count 30 transition count 26
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 2 Pre rules applied. Total rules applied 54 place count 30 transition count 24
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 3 with 4 rules applied. Total rules applied 58 place count 28 transition count 24
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 60 place count 27 transition count 23
Applied a total of 60 rules in 6 ms. Remains 27 /79 variables (removed 52) and now considering 23/63 (removed 40) transitions.
// Phase 1: matrix 23 rows 27 cols
[2023-03-17 11:38:44] [INFO ] Computed 10 place invariants in 1 ms
[2023-03-17 11:38:44] [INFO ] Dead Transitions using invariants and state equation in 25 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 32 ms. Remains : 27/79 places, 23/63 transitions.
[2023-03-17 11:38:44] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:38:45] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:38:45] [INFO ] Input system was already deterministic with 23 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 79/79 places, 63/63 transitions.
Graph (trivial) has 44 edges and 79 vertex of which 30 / 79 are part of one of the 15 SCC in 1 ms
Free SCC test removed 15 places
Ensure Unique test removed 15 transitions
Reduce isomorphic transitions removed 15 transitions.
Reduce places removed 15 places and 0 transitions.
Ensure Unique test removed 14 transitions
Reduce isomorphic transitions removed 14 transitions.
Iterating post reduction 0 with 14 rules applied. Total rules applied 15 place count 49 transition count 34
Performed 14 Post agglomeration using F-continuation condition.Transition count delta: 14
Deduced a syphon composed of 14 places in 0 ms
Reduce places removed 28 places and 0 transitions.
Iterating global reduction 1 with 42 rules applied. Total rules applied 57 place count 21 transition count 20
Drop transitions removed 13 transitions
Trivial Post-agglo rules discarded 13 transitions
Performed 13 trivial Post agglomeration. Transition count delta: 13
Iterating post reduction 1 with 13 rules applied. Total rules applied 70 place count 21 transition count 7
Reduce places removed 13 places and 0 transitions.
Iterating post reduction 2 with 13 rules applied. Total rules applied 83 place count 8 transition count 7
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 1 Pre rules applied. Total rules applied 83 place count 8 transition count 6
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 85 place count 7 transition count 6
Applied a total of 85 rules in 5 ms. Remains 7 /79 variables (removed 72) and now considering 6/63 (removed 57) transitions.
// Phase 1: matrix 6 rows 7 cols
[2023-03-17 11:38:45] [INFO ] Computed 3 place invariants in 0 ms
[2023-03-17 11:38:45] [INFO ] Dead Transitions using invariants and state equation in 17 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 23 ms. Remains : 7/79 places, 6/63 transitions.
[2023-03-17 11:38:45] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:38:45] [INFO ] Flatten gal took : 0 ms
[2023-03-17 11:38:45] [INFO ] Input system was already deterministic with 6 transitions.
Finished random walk after 2 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=2 )
FORMULA RefineWMG-PT-015016-CTLFireability-09 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 79/79 places, 63/63 transitions.
Applied a total of 0 rules in 3 ms. Remains 79 /79 variables (removed 0) and now considering 63/63 (removed 0) transitions.
// Phase 1: matrix 63 rows 79 cols
[2023-03-17 11:38:45] [INFO ] Computed 32 place invariants in 5 ms
[2023-03-17 11:38:45] [INFO ] Dead Transitions using invariants and state equation in 45 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 49 ms. Remains : 79/79 places, 63/63 transitions.
[2023-03-17 11:38:45] [INFO ] Flatten gal took : 3 ms
[2023-03-17 11:38:45] [INFO ] Flatten gal took : 3 ms
[2023-03-17 11:38:45] [INFO ] Input system was already deterministic with 63 transitions.
Starting structural reductions in LTL mode, iteration 0 : 79/79 places, 63/63 transitions.
Applied a total of 0 rules in 2 ms. Remains 79 /79 variables (removed 0) and now considering 63/63 (removed 0) transitions.
[2023-03-17 11:38:45] [INFO ] Invariant cache hit.
[2023-03-17 11:38:45] [INFO ] Dead Transitions using invariants and state equation in 38 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 41 ms. Remains : 79/79 places, 63/63 transitions.
[2023-03-17 11:38:45] [INFO ] Flatten gal took : 3 ms
[2023-03-17 11:38:45] [INFO ] Flatten gal took : 3 ms
[2023-03-17 11:38:45] [INFO ] Input system was already deterministic with 63 transitions.
Starting structural reductions in LTL mode, iteration 0 : 79/79 places, 63/63 transitions.
Applied a total of 0 rules in 2 ms. Remains 79 /79 variables (removed 0) and now considering 63/63 (removed 0) transitions.
[2023-03-17 11:38:45] [INFO ] Invariant cache hit.
[2023-03-17 11:38:45] [INFO ] Dead Transitions using invariants and state equation in 41 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 43 ms. Remains : 79/79 places, 63/63 transitions.
[2023-03-17 11:38:45] [INFO ] Flatten gal took : 3 ms
[2023-03-17 11:38:45] [INFO ] Flatten gal took : 3 ms
[2023-03-17 11:38:45] [INFO ] Input system was already deterministic with 63 transitions.
Starting structural reductions in LTL mode, iteration 0 : 79/79 places, 63/63 transitions.
Applied a total of 0 rules in 1 ms. Remains 79 /79 variables (removed 0) and now considering 63/63 (removed 0) transitions.
[2023-03-17 11:38:45] [INFO ] Invariant cache hit.
[2023-03-17 11:38:45] [INFO ] Dead Transitions using invariants and state equation in 47 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 48 ms. Remains : 79/79 places, 63/63 transitions.
[2023-03-17 11:38:45] [INFO ] Flatten gal took : 3 ms
[2023-03-17 11:38:45] [INFO ] Flatten gal took : 3 ms
[2023-03-17 11:38:45] [INFO ] Input system was already deterministic with 63 transitions.
Starting structural reductions in LTL mode, iteration 0 : 79/79 places, 63/63 transitions.
Applied a total of 0 rules in 1 ms. Remains 79 /79 variables (removed 0) and now considering 63/63 (removed 0) transitions.
[2023-03-17 11:38:45] [INFO ] Invariant cache hit.
[2023-03-17 11:38:45] [INFO ] Dead Transitions using invariants and state equation in 42 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 45 ms. Remains : 79/79 places, 63/63 transitions.
[2023-03-17 11:38:45] [INFO ] Flatten gal took : 3 ms
[2023-03-17 11:38:45] [INFO ] Flatten gal took : 3 ms
[2023-03-17 11:38:45] [INFO ] Input system was already deterministic with 63 transitions.
Starting structural reductions in LTL mode, iteration 0 : 79/79 places, 63/63 transitions.
Applied a total of 0 rules in 1 ms. Remains 79 /79 variables (removed 0) and now considering 63/63 (removed 0) transitions.
[2023-03-17 11:38:45] [INFO ] Invariant cache hit.
[2023-03-17 11:38:45] [INFO ] Dead Transitions using invariants and state equation in 39 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 41 ms. Remains : 79/79 places, 63/63 transitions.
[2023-03-17 11:38:45] [INFO ] Flatten gal took : 3 ms
[2023-03-17 11:38:45] [INFO ] Flatten gal took : 3 ms
[2023-03-17 11:38:45] [INFO ] Input system was already deterministic with 63 transitions.
[2023-03-17 11:38:45] [INFO ] Flatten gal took : 9 ms
[2023-03-17 11:38:45] [INFO ] Flatten gal took : 3 ms
[2023-03-17 11:38:45] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-17 11:38:45] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 79 places, 63 transitions and 188 arcs took 0 ms.
Total runtime 2821 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT RefineWMG-PT-015016
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/376
CTLFireability

FORMULA RefineWMG-PT-015016-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RefineWMG-PT-015016-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RefineWMG-PT-015016-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RefineWMG-PT-015016-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RefineWMG-PT-015016-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RefineWMG-PT-015016-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679053286941

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/376/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/376/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/376/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 1 (type EXCL) for 0 RefineWMG-PT-015016-CTLFireability-00
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for RefineWMG-PT-015016-CTLFireability-00
lola: result : false
lola: markings : 34
lola: fired transitions : 70
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 19 (type EXCL) for 18 RefineWMG-PT-015016-CTLFireability-07
lola: time limit : 225 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-14: AXAG 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 5/276 16/32 RefineWMG-PT-015016-CTLFireability-07 3176884 m, 635376 m/sec, 4864571 t fired, .

Time elapsed: 5 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-14: AXAG 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 10/276 31/32 RefineWMG-PT-015016-CTLFireability-07 6210881 m, 606799 m/sec, 9510382 t fired, .

Time elapsed: 10 secs. Pages in use: 31
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 19 (type EXCL) for RefineWMG-PT-015016-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-14: AXAG 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 15 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 42 (type EXCL) for 36 RefineWMG-PT-015016-CTLFireability-14
lola: time limit : 298 sec
lola: memory limit: 32 pages
lola: FINISHED task # 42 (type EXCL) for RefineWMG-PT-015016-CTLFireability-14
lola: result : true
lola: markings : 17
lola: fired transitions : 16
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 40 (type EXCL) for 39 RefineWMG-PT-015016-CTLFireability-15
lola: time limit : 325 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-14: AXAG false state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 5/325 8/32 RefineWMG-PT-015016-CTLFireability-15 1361766 m, 272353 m/sec, 3938312 t fired, .

Time elapsed: 20 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-14: AXAG false state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 10/325 14/32 RefineWMG-PT-015016-CTLFireability-15 2560325 m, 239711 m/sec, 8160505 t fired, .

Time elapsed: 25 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-14: AXAG false state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 15/325 19/32 RefineWMG-PT-015016-CTLFireability-15 3592043 m, 206343 m/sec, 12835420 t fired, .

Time elapsed: 30 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-14: AXAG false state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 20/325 23/32 RefineWMG-PT-015016-CTLFireability-15 4592278 m, 200047 m/sec, 17367699 t fired, .

Time elapsed: 35 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-14: AXAG false state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 25/325 30/32 RefineWMG-PT-015016-CTLFireability-15 6054134 m, 292371 m/sec, 20526820 t fired, .

Time elapsed: 40 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 40 (type EXCL) for RefineWMG-PT-015016-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-14: AXAG false state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 45 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 34 (type EXCL) for 33 RefineWMG-PT-015016-CTLFireability-13
lola: time limit : 355 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-14: AXAG false state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 5/355 13/32 RefineWMG-PT-015016-CTLFireability-13 2375862 m, 475172 m/sec, 6013860 t fired, .

Time elapsed: 50 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-14: AXAG false state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 10/355 20/32 RefineWMG-PT-015016-CTLFireability-13 4035188 m, 331865 m/sec, 10214040 t fired, .

Time elapsed: 55 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-14: AXAG false state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 15/355 29/32 RefineWMG-PT-015016-CTLFireability-13 5657103 m, 324383 m/sec, 14319494 t fired, .

Time elapsed: 60 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 34 (type EXCL) for RefineWMG-PT-015016-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-14: AXAG false state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 65 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 31 (type EXCL) for 30 RefineWMG-PT-015016-CTLFireability-12
lola: time limit : 392 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-14: AXAG false state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 5/392 11/32 RefineWMG-PT-015016-CTLFireability-12 1940199 m, 388039 m/sec, 4573661 t fired, .

Time elapsed: 70 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-14: AXAG false state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 10/392 20/32 RefineWMG-PT-015016-CTLFireability-12 3780289 m, 368018 m/sec, 10721281 t fired, .

Time elapsed: 75 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-14: AXAG false state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 15/392 28/32 RefineWMG-PT-015016-CTLFireability-12 5587981 m, 361538 m/sec, 15733282 t fired, .

Time elapsed: 80 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 31 (type EXCL) for RefineWMG-PT-015016-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-14: AXAG false state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 85 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 28 (type EXCL) for 27 RefineWMG-PT-015016-CTLFireability-11
lola: time limit : 439 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-14: AXAG false state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 5/439 17/32 RefineWMG-PT-015016-CTLFireability-11 3328189 m, 665637 m/sec, 5096257 t fired, .

Time elapsed: 90 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 28 (type EXCL) for RefineWMG-PT-015016-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-14: AXAG false state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 95 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 25 (type EXCL) for 24 RefineWMG-PT-015016-CTLFireability-10
lola: time limit : 500 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for RefineWMG-PT-015016-CTLFireability-10
lola: result : false
lola: markings : 51
lola: fired transitions : 66
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 RefineWMG-PT-015016-CTLFireability-06
lola: time limit : 584 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for RefineWMG-PT-015016-CTLFireability-06
lola: result : true
lola: markings : 250
lola: fired transitions : 419
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 RefineWMG-PT-015016-CTLFireability-05
lola: time limit : 701 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-06: CTL true CTL model checker
RefineWMG-PT-015016-CTLFireability-10: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-14: AXAG false state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/701 16/32 RefineWMG-PT-015016-CTLFireability-05 3202565 m, 640513 m/sec, 6202669 t fired, .

Time elapsed: 100 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-06: CTL true CTL model checker
RefineWMG-PT-015016-CTLFireability-10: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-14: AXAG false state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 10/701 28/32 RefineWMG-PT-015016-CTLFireability-05 5761551 m, 511797 m/sec, 11203090 t fired, .

Time elapsed: 105 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 13 (type EXCL) for RefineWMG-PT-015016-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-06: CTL true CTL model checker
RefineWMG-PT-015016-CTLFireability-10: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-14: AXAG false state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 10 (type EXCL) for 9 RefineWMG-PT-015016-CTLFireability-04
lola: time limit : 872 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-06: CTL true CTL model checker
RefineWMG-PT-015016-CTLFireability-10: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-14: AXAG false state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/872 12/32 RefineWMG-PT-015016-CTLFireability-04 2241739 m, 448347 m/sec, 4823146 t fired, .

Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-06: CTL true CTL model checker
RefineWMG-PT-015016-CTLFireability-10: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-14: AXAG false state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 10/872 23/32 RefineWMG-PT-015016-CTLFireability-04 4525107 m, 456673 m/sec, 10688646 t fired, .

Time elapsed: 120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-06: CTL true CTL model checker
RefineWMG-PT-015016-CTLFireability-10: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-14: AXAG false state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 15/872 32/32 RefineWMG-PT-015016-CTLFireability-04 6506170 m, 396212 m/sec, 16509266 t fired, .

Time elapsed: 125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 10 (type EXCL) for RefineWMG-PT-015016-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-06: CTL true CTL model checker
RefineWMG-PT-015016-CTLFireability-10: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-14: AXAG false state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 130 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 4 (type EXCL) for 3 RefineWMG-PT-015016-CTLFireability-01
lola: time limit : 1156 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for RefineWMG-PT-015016-CTLFireability-01
lola: result : true
lola: markings : 132480
lola: fired transitions : 541740
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 RefineWMG-PT-015016-CTLFireability-08
lola: time limit : 1735 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for RefineWMG-PT-015016-CTLFireability-08
lola: result : false
lola: markings : 34
lola: fired transitions : 112
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 RefineWMG-PT-015016-CTLFireability-03
lola: time limit : 3470 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-01: AGEF true tscc_search
RefineWMG-PT-015016-CTLFireability-06: CTL true CTL model checker
RefineWMG-PT-015016-CTLFireability-08: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-10: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-14: AXAG false state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/3470 7/32 RefineWMG-PT-015016-CTLFireability-03 1565493 m, 313098 m/sec, 8659081 t fired, .

Time elapsed: 135 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-01: AGEF true tscc_search
RefineWMG-PT-015016-CTLFireability-06: CTL true CTL model checker
RefineWMG-PT-015016-CTLFireability-08: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-10: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-14: AXAG false state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/3470 13/32 RefineWMG-PT-015016-CTLFireability-03 3040316 m, 294964 m/sec, 16983750 t fired, .

Time elapsed: 140 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-01: AGEF true tscc_search
RefineWMG-PT-015016-CTLFireability-06: CTL true CTL model checker
RefineWMG-PT-015016-CTLFireability-08: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-10: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-14: AXAG false state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/3470 19/32 RefineWMG-PT-015016-CTLFireability-03 4420753 m, 276087 m/sec, 24619286 t fired, .

Time elapsed: 145 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-01: AGEF true tscc_search
RefineWMG-PT-015016-CTLFireability-06: CTL true CTL model checker
RefineWMG-PT-015016-CTLFireability-08: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-10: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-14: AXAG false state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/3470 25/32 RefineWMG-PT-015016-CTLFireability-03 5777964 m, 271442 m/sec, 32495122 t fired, .

Time elapsed: 150 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-01: AGEF true tscc_search
RefineWMG-PT-015016-CTLFireability-06: CTL true CTL model checker
RefineWMG-PT-015016-CTLFireability-08: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-10: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-14: AXAG false state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 25/3470 31/32 RefineWMG-PT-015016-CTLFireability-03 7206681 m, 285743 m/sec, 40397718 t fired, .

Time elapsed: 155 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 7 (type EXCL) for RefineWMG-PT-015016-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-01: AGEF true tscc_search
RefineWMG-PT-015016-CTLFireability-06: CTL true CTL model checker
RefineWMG-PT-015016-CTLFireability-08: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-10: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-14: AXAG false state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-015016-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-015016-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 160 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: Portfolio finished: no open tasks 14

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-015016-CTLFireability-00: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-01: AGEF true tscc_search
RefineWMG-PT-015016-CTLFireability-03: CTL unknown AGGR
RefineWMG-PT-015016-CTLFireability-04: CTL unknown AGGR
RefineWMG-PT-015016-CTLFireability-05: CTL unknown AGGR
RefineWMG-PT-015016-CTLFireability-06: CTL true CTL model checker
RefineWMG-PT-015016-CTLFireability-07: CTL unknown AGGR
RefineWMG-PT-015016-CTLFireability-08: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-10: CTL false CTL model checker
RefineWMG-PT-015016-CTLFireability-11: CTL unknown AGGR
RefineWMG-PT-015016-CTLFireability-12: CTL unknown AGGR
RefineWMG-PT-015016-CTLFireability-13: CTL unknown AGGR
RefineWMG-PT-015016-CTLFireability-14: AXAG false state space /EXEF
RefineWMG-PT-015016-CTLFireability-15: CTL unknown AGGR


Time elapsed: 160 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RefineWMG-PT-015016"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is RefineWMG-PT-015016, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r327-tall-167889199800602"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RefineWMG-PT-015016.tgz
mv RefineWMG-PT-015016 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;