About the Execution of LoLa+red for RefineWMG-PT-007007
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 3920.848 | 99998.00 | 96125.00 | 685.20 | TTTTFF??T?TTF?TF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r327-tall-167889199800562.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is RefineWMG-PT-007007, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r327-tall-167889199800562
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 500K
-rw-r--r-- 1 mcc users 7.8K Feb 26 16:00 CTLCardinality.txt
-rw-r--r-- 1 mcc users 91K Feb 26 16:00 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.3K Feb 26 15:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 49K Feb 26 15:58 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.9K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.1K Feb 25 16:43 LTLCardinality.txt
-rw-r--r-- 1 mcc users 20K Feb 25 16:43 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 16:43 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:43 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 26 16:01 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 127K Feb 26 16:01 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.1K Feb 26 16:00 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 84K Feb 26 16:00 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:43 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:43 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 7 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 18K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME RefineWMG-PT-007007-CTLFireability-00
FORMULA_NAME RefineWMG-PT-007007-CTLFireability-01
FORMULA_NAME RefineWMG-PT-007007-CTLFireability-02
FORMULA_NAME RefineWMG-PT-007007-CTLFireability-03
FORMULA_NAME RefineWMG-PT-007007-CTLFireability-04
FORMULA_NAME RefineWMG-PT-007007-CTLFireability-05
FORMULA_NAME RefineWMG-PT-007007-CTLFireability-06
FORMULA_NAME RefineWMG-PT-007007-CTLFireability-07
FORMULA_NAME RefineWMG-PT-007007-CTLFireability-08
FORMULA_NAME RefineWMG-PT-007007-CTLFireability-09
FORMULA_NAME RefineWMG-PT-007007-CTLFireability-10
FORMULA_NAME RefineWMG-PT-007007-CTLFireability-11
FORMULA_NAME RefineWMG-PT-007007-CTLFireability-12
FORMULA_NAME RefineWMG-PT-007007-CTLFireability-13
FORMULA_NAME RefineWMG-PT-007007-CTLFireability-14
FORMULA_NAME RefineWMG-PT-007007-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679052493042
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RefineWMG-PT-007007
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-17 11:28:14] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-17 11:28:14] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-17 11:28:14] [INFO ] Load time of PNML (sax parser for PT used): 25 ms
[2023-03-17 11:28:14] [INFO ] Transformed 39 places.
[2023-03-17 11:28:14] [INFO ] Transformed 31 transitions.
[2023-03-17 11:28:14] [INFO ] Parsed PT model containing 39 places and 31 transitions and 92 arcs in 86 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 10 ms.
Support contains 38 out of 39 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 39/39 places, 31/31 transitions.
Applied a total of 0 rules in 9 ms. Remains 39 /39 variables (removed 0) and now considering 31/31 (removed 0) transitions.
// Phase 1: matrix 31 rows 39 cols
[2023-03-17 11:28:14] [INFO ] Computed 16 place invariants in 6 ms
[2023-03-17 11:28:15] [INFO ] Dead Transitions using invariants and state equation in 458 ms found 0 transitions.
[2023-03-17 11:28:15] [INFO ] Invariant cache hit.
[2023-03-17 11:28:15] [INFO ] Implicit Places using invariants in 30 ms returned []
[2023-03-17 11:28:15] [INFO ] Invariant cache hit.
[2023-03-17 11:28:15] [INFO ] Implicit Places using invariants and state equation in 34 ms returned []
Implicit Place search using SMT with State Equation took 66 ms to find 0 implicit places.
[2023-03-17 11:28:15] [INFO ] Invariant cache hit.
[2023-03-17 11:28:15] [INFO ] Dead Transitions using invariants and state equation in 37 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 595 ms. Remains : 39/39 places, 31/31 transitions.
Support contains 38 out of 39 places after structural reductions.
[2023-03-17 11:28:15] [INFO ] Flatten gal took : 16 ms
[2023-03-17 11:28:15] [INFO ] Flatten gal took : 6 ms
[2023-03-17 11:28:15] [INFO ] Input system was already deterministic with 31 transitions.
Support contains 36 out of 39 places (down from 38) after GAL structural reductions.
Incomplete random walk after 10002 steps, including 2 resets, run finished after 91 ms. (steps per millisecond=109 ) properties (out of 45) seen :44
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=526 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-17 11:28:15] [INFO ] Invariant cache hit.
[2023-03-17 11:28:15] [INFO ] After 27ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0
Fused 1 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 1 atomic propositions for a total of 16 simplifications.
[2023-03-17 11:28:15] [INFO ] Flatten gal took : 4 ms
[2023-03-17 11:28:15] [INFO ] Flatten gal took : 3 ms
[2023-03-17 11:28:15] [INFO ] Input system was already deterministic with 31 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 39/39 places, 31/31 transitions.
Applied a total of 0 rules in 1 ms. Remains 39 /39 variables (removed 0) and now considering 31/31 (removed 0) transitions.
[2023-03-17 11:28:15] [INFO ] Invariant cache hit.
[2023-03-17 11:28:15] [INFO ] Dead Transitions using invariants and state equation in 38 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 39 ms. Remains : 39/39 places, 31/31 transitions.
[2023-03-17 11:28:15] [INFO ] Flatten gal took : 3 ms
[2023-03-17 11:28:15] [INFO ] Flatten gal took : 4 ms
[2023-03-17 11:28:15] [INFO ] Input system was already deterministic with 31 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 39/39 places, 31/31 transitions.
Graph (trivial) has 18 edges and 39 vertex of which 12 / 39 are part of one of the 6 SCC in 2 ms
Free SCC test removed 6 places
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Reduce places removed 6 places and 0 transitions.
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 0 with 5 rules applied. Total rules applied 6 place count 27 transition count 20
Performed 6 Post agglomeration using F-continuation condition.Transition count delta: 6
Deduced a syphon composed of 6 places in 1 ms
Reduce places removed 12 places and 0 transitions.
Iterating global reduction 1 with 18 rules applied. Total rules applied 24 place count 15 transition count 14
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded 3 transitions
Performed 3 trivial Post agglomeration. Transition count delta: 3
Iterating post reduction 1 with 3 rules applied. Total rules applied 27 place count 15 transition count 11
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 2 with 3 rules applied. Total rules applied 30 place count 12 transition count 11
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 1 Pre rules applied. Total rules applied 30 place count 12 transition count 10
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 32 place count 11 transition count 10
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 34 place count 10 transition count 9
Applied a total of 34 rules in 11 ms. Remains 10 /39 variables (removed 29) and now considering 9/31 (removed 22) transitions.
// Phase 1: matrix 9 rows 10 cols
[2023-03-17 11:28:15] [INFO ] Computed 4 place invariants in 0 ms
[2023-03-17 11:28:15] [INFO ] Dead Transitions using invariants and state equation in 28 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 39 ms. Remains : 10/39 places, 9/31 transitions.
[2023-03-17 11:28:15] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:28:15] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:28:15] [INFO ] Input system was already deterministic with 9 transitions.
Finished random walk after 38 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=38 )
FORMULA RefineWMG-PT-007007-CTLFireability-01 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 39/39 places, 31/31 transitions.
Applied a total of 0 rules in 0 ms. Remains 39 /39 variables (removed 0) and now considering 31/31 (removed 0) transitions.
// Phase 1: matrix 31 rows 39 cols
[2023-03-17 11:28:15] [INFO ] Computed 16 place invariants in 1 ms
[2023-03-17 11:28:15] [INFO ] Dead Transitions using invariants and state equation in 46 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 46 ms. Remains : 39/39 places, 31/31 transitions.
[2023-03-17 11:28:15] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:28:15] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:28:15] [INFO ] Input system was already deterministic with 31 transitions.
Starting structural reductions in LTL mode, iteration 0 : 39/39 places, 31/31 transitions.
Applied a total of 0 rules in 0 ms. Remains 39 /39 variables (removed 0) and now considering 31/31 (removed 0) transitions.
[2023-03-17 11:28:15] [INFO ] Invariant cache hit.
[2023-03-17 11:28:15] [INFO ] Dead Transitions using invariants and state equation in 36 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 37 ms. Remains : 39/39 places, 31/31 transitions.
[2023-03-17 11:28:15] [INFO ] Flatten gal took : 3 ms
[2023-03-17 11:28:15] [INFO ] Flatten gal took : 6 ms
[2023-03-17 11:28:15] [INFO ] Input system was already deterministic with 31 transitions.
Starting structural reductions in LTL mode, iteration 0 : 39/39 places, 31/31 transitions.
Applied a total of 0 rules in 0 ms. Remains 39 /39 variables (removed 0) and now considering 31/31 (removed 0) transitions.
[2023-03-17 11:28:15] [INFO ] Invariant cache hit.
[2023-03-17 11:28:15] [INFO ] Dead Transitions using invariants and state equation in 44 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 45 ms. Remains : 39/39 places, 31/31 transitions.
[2023-03-17 11:28:15] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:28:15] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:28:15] [INFO ] Input system was already deterministic with 31 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 39/39 places, 31/31 transitions.
Graph (trivial) has 8 edges and 39 vertex of which 4 / 39 are part of one of the 2 SCC in 0 ms
Free SCC test removed 2 places
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Reduce places removed 2 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 2 place count 35 transition count 28
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 8 places and 0 transitions.
Iterating global reduction 1 with 12 rules applied. Total rules applied 14 place count 27 transition count 24
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 1 with 2 Pre rules applied. Total rules applied 14 place count 27 transition count 22
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 1 with 4 rules applied. Total rules applied 18 place count 25 transition count 22
Applied a total of 18 rules in 3 ms. Remains 25 /39 variables (removed 14) and now considering 22/31 (removed 9) transitions.
// Phase 1: matrix 22 rows 25 cols
[2023-03-17 11:28:15] [INFO ] Computed 10 place invariants in 0 ms
[2023-03-17 11:28:15] [INFO ] Dead Transitions using invariants and state equation in 32 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 35 ms. Remains : 25/39 places, 22/31 transitions.
[2023-03-17 11:28:15] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:28:15] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:28:15] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in LTL mode, iteration 0 : 39/39 places, 31/31 transitions.
Applied a total of 0 rules in 0 ms. Remains 39 /39 variables (removed 0) and now considering 31/31 (removed 0) transitions.
// Phase 1: matrix 31 rows 39 cols
[2023-03-17 11:28:15] [INFO ] Computed 16 place invariants in 1 ms
[2023-03-17 11:28:16] [INFO ] Dead Transitions using invariants and state equation in 38 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 40 ms. Remains : 39/39 places, 31/31 transitions.
[2023-03-17 11:28:16] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:28:16] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:28:16] [INFO ] Input system was already deterministic with 31 transitions.
Starting structural reductions in LTL mode, iteration 0 : 39/39 places, 31/31 transitions.
Applied a total of 0 rules in 1 ms. Remains 39 /39 variables (removed 0) and now considering 31/31 (removed 0) transitions.
[2023-03-17 11:28:16] [INFO ] Invariant cache hit.
[2023-03-17 11:28:16] [INFO ] Dead Transitions using invariants and state equation in 33 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 34 ms. Remains : 39/39 places, 31/31 transitions.
[2023-03-17 11:28:16] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:28:16] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:28:16] [INFO ] Input system was already deterministic with 31 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 39/39 places, 31/31 transitions.
Graph (trivial) has 18 edges and 39 vertex of which 12 / 39 are part of one of the 6 SCC in 0 ms
Free SCC test removed 6 places
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Reduce places removed 6 places and 0 transitions.
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 0 with 5 rules applied. Total rules applied 6 place count 27 transition count 20
Performed 6 Post agglomeration using F-continuation condition.Transition count delta: 6
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 12 places and 0 transitions.
Iterating global reduction 1 with 18 rules applied. Total rules applied 24 place count 15 transition count 14
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded 4 transitions
Performed 4 trivial Post agglomeration. Transition count delta: 4
Iterating post reduction 1 with 4 rules applied. Total rules applied 28 place count 15 transition count 10
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 2 with 4 rules applied. Total rules applied 32 place count 11 transition count 10
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 1 Pre rules applied. Total rules applied 32 place count 11 transition count 9
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 34 place count 10 transition count 9
Applied a total of 34 rules in 4 ms. Remains 10 /39 variables (removed 29) and now considering 9/31 (removed 22) transitions.
// Phase 1: matrix 9 rows 10 cols
[2023-03-17 11:28:16] [INFO ] Computed 4 place invariants in 0 ms
[2023-03-17 11:28:16] [INFO ] Dead Transitions using invariants and state equation in 41 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 45 ms. Remains : 10/39 places, 9/31 transitions.
[2023-03-17 11:28:16] [INFO ] Flatten gal took : 0 ms
[2023-03-17 11:28:16] [INFO ] Flatten gal took : 0 ms
[2023-03-17 11:28:16] [INFO ] Input system was already deterministic with 9 transitions.
Finished random walk after 33 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=33 )
FORMULA RefineWMG-PT-007007-CTLFireability-08 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in SI_CTL mode, iteration 0 : 39/39 places, 31/31 transitions.
Graph (trivial) has 13 edges and 39 vertex of which 8 / 39 are part of one of the 4 SCC in 1 ms
Free SCC test removed 4 places
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Reduce places removed 4 places and 0 transitions.
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 4 place count 31 transition count 24
Performed 5 Post agglomeration using F-continuation condition.Transition count delta: 5
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 1 with 15 rules applied. Total rules applied 19 place count 21 transition count 19
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 1 with 1 rules applied. Total rules applied 20 place count 21 transition count 18
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 21 place count 20 transition count 18
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 2 Pre rules applied. Total rules applied 21 place count 20 transition count 16
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 3 with 4 rules applied. Total rules applied 25 place count 18 transition count 16
Applied a total of 25 rules in 4 ms. Remains 18 /39 variables (removed 21) and now considering 16/31 (removed 15) transitions.
// Phase 1: matrix 16 rows 18 cols
[2023-03-17 11:28:16] [INFO ] Computed 7 place invariants in 0 ms
[2023-03-17 11:28:16] [INFO ] Dead Transitions using invariants and state equation in 23 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 28 ms. Remains : 18/39 places, 16/31 transitions.
[2023-03-17 11:28:16] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:28:16] [INFO ] Flatten gal took : 0 ms
[2023-03-17 11:28:16] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 39/39 places, 31/31 transitions.
Applied a total of 0 rules in 0 ms. Remains 39 /39 variables (removed 0) and now considering 31/31 (removed 0) transitions.
// Phase 1: matrix 31 rows 39 cols
[2023-03-17 11:28:16] [INFO ] Computed 16 place invariants in 3 ms
[2023-03-17 11:28:16] [INFO ] Dead Transitions using invariants and state equation in 43 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 44 ms. Remains : 39/39 places, 31/31 transitions.
[2023-03-17 11:28:16] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:28:16] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:28:16] [INFO ] Input system was already deterministic with 31 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 39/39 places, 31/31 transitions.
Graph (trivial) has 17 edges and 39 vertex of which 10 / 39 are part of one of the 5 SCC in 1 ms
Free SCC test removed 5 places
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Reduce places removed 5 places and 0 transitions.
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 0 with 4 rules applied. Total rules applied 5 place count 29 transition count 22
Performed 7 Post agglomeration using F-continuation condition.Transition count delta: 7
Deduced a syphon composed of 7 places in 0 ms
Reduce places removed 14 places and 0 transitions.
Iterating global reduction 1 with 21 rules applied. Total rules applied 26 place count 15 transition count 15
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 1 with 2 rules applied. Total rules applied 28 place count 15 transition count 13
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 30 place count 13 transition count 13
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 2 Pre rules applied. Total rules applied 30 place count 13 transition count 11
Deduced a syphon composed of 2 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 3 with 4 rules applied. Total rules applied 34 place count 11 transition count 11
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 36 place count 10 transition count 10
Applied a total of 36 rules in 4 ms. Remains 10 /39 variables (removed 29) and now considering 10/31 (removed 21) transitions.
// Phase 1: matrix 10 rows 10 cols
[2023-03-17 11:28:16] [INFO ] Computed 4 place invariants in 0 ms
[2023-03-17 11:28:16] [INFO ] Dead Transitions using invariants and state equation in 23 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 28 ms. Remains : 10/39 places, 10/31 transitions.
[2023-03-17 11:28:16] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:28:16] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:28:16] [INFO ] Input system was already deterministic with 10 transitions.
Finished random walk after 63 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=31 )
FORMULA RefineWMG-PT-007007-CTLFireability-11 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 39/39 places, 31/31 transitions.
Applied a total of 0 rules in 1 ms. Remains 39 /39 variables (removed 0) and now considering 31/31 (removed 0) transitions.
// Phase 1: matrix 31 rows 39 cols
[2023-03-17 11:28:16] [INFO ] Computed 16 place invariants in 1 ms
[2023-03-17 11:28:16] [INFO ] Dead Transitions using invariants and state equation in 34 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 36 ms. Remains : 39/39 places, 31/31 transitions.
[2023-03-17 11:28:16] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:28:16] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:28:16] [INFO ] Input system was already deterministic with 31 transitions.
Starting structural reductions in LTL mode, iteration 0 : 39/39 places, 31/31 transitions.
Applied a total of 0 rules in 1 ms. Remains 39 /39 variables (removed 0) and now considering 31/31 (removed 0) transitions.
[2023-03-17 11:28:16] [INFO ] Invariant cache hit.
[2023-03-17 11:28:16] [INFO ] Dead Transitions using invariants and state equation in 29 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 31 ms. Remains : 39/39 places, 31/31 transitions.
[2023-03-17 11:28:16] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:28:16] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:28:16] [INFO ] Input system was already deterministic with 31 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 39/39 places, 31/31 transitions.
Graph (trivial) has 20 edges and 39 vertex of which 14 / 39 are part of one of the 7 SCC in 0 ms
Free SCC test removed 7 places
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Reduce places removed 7 places and 0 transitions.
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 0 with 6 rules applied. Total rules applied 7 place count 25 transition count 18
Performed 6 Post agglomeration using F-continuation condition.Transition count delta: 6
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 12 places and 0 transitions.
Iterating global reduction 1 with 18 rules applied. Total rules applied 25 place count 13 transition count 12
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded 5 transitions
Performed 5 trivial Post agglomeration. Transition count delta: 5
Iterating post reduction 1 with 5 rules applied. Total rules applied 30 place count 13 transition count 7
Reduce places removed 5 places and 0 transitions.
Iterating post reduction 2 with 5 rules applied. Total rules applied 35 place count 8 transition count 7
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 1 Pre rules applied. Total rules applied 35 place count 8 transition count 6
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 37 place count 7 transition count 6
Applied a total of 37 rules in 3 ms. Remains 7 /39 variables (removed 32) and now considering 6/31 (removed 25) transitions.
// Phase 1: matrix 6 rows 7 cols
[2023-03-17 11:28:16] [INFO ] Computed 3 place invariants in 0 ms
[2023-03-17 11:28:16] [INFO ] Dead Transitions using invariants and state equation in 15 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 19 ms. Remains : 7/39 places, 6/31 transitions.
[2023-03-17 11:28:16] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:28:16] [INFO ] Flatten gal took : 0 ms
[2023-03-17 11:28:16] [INFO ] Input system was already deterministic with 6 transitions.
Finished random walk after 4 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=4 )
FORMULA RefineWMG-PT-007007-CTLFireability-14 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in SI_CTL mode, iteration 0 : 39/39 places, 31/31 transitions.
Graph (trivial) has 18 edges and 39 vertex of which 12 / 39 are part of one of the 6 SCC in 0 ms
Free SCC test removed 6 places
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Reduce places removed 6 places and 0 transitions.
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 0 with 5 rules applied. Total rules applied 6 place count 27 transition count 20
Performed 6 Post agglomeration using F-continuation condition.Transition count delta: 6
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 12 places and 0 transitions.
Iterating global reduction 1 with 18 rules applied. Total rules applied 24 place count 15 transition count 14
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded 5 transitions
Performed 5 trivial Post agglomeration. Transition count delta: 5
Iterating post reduction 1 with 5 rules applied. Total rules applied 29 place count 15 transition count 9
Reduce places removed 5 places and 0 transitions.
Iterating post reduction 2 with 5 rules applied. Total rules applied 34 place count 10 transition count 9
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 36 place count 9 transition count 8
Applied a total of 36 rules in 2 ms. Remains 9 /39 variables (removed 30) and now considering 8/31 (removed 23) transitions.
// Phase 1: matrix 8 rows 9 cols
[2023-03-17 11:28:16] [INFO ] Computed 4 place invariants in 0 ms
[2023-03-17 11:28:16] [INFO ] Dead Transitions using invariants and state equation in 17 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 19 ms. Remains : 9/39 places, 8/31 transitions.
[2023-03-17 11:28:16] [INFO ] Flatten gal took : 0 ms
[2023-03-17 11:28:16] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:28:16] [INFO ] Input system was already deterministic with 8 transitions.
[2023-03-17 11:28:16] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:28:16] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:28:16] [INFO ] Export to MCC of 12 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-17 11:28:16] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 39 places, 31 transitions and 92 arcs took 0 ms.
Total runtime 1882 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT RefineWMG-PT-007007
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability
FORMULA RefineWMG-PT-007007-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-007007-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-007007-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-007007-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-007007-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-007007-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-007007-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-007007-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679052593040
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 7 (type EXCL) for 6 RefineWMG-PT-007007-CTLFireability-03
lola: time limit : 240 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 7 (type EXCL) for RefineWMG-PT-007007-CTLFireability-03
lola: result : true
lola: markings : 145
lola: fired transitions : 327
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 RefineWMG-PT-007007-CTLFireability-02
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 4 (type EXCL) for RefineWMG-PT-007007-CTLFireability-02
lola: result : true
lola: markings : 945530
lola: fired transitions : 2660715
lola: time used : 2.000000
lola: memory pages used : 4
lola: LAUNCH task # 31 (type EXCL) for 30 RefineWMG-PT-007007-CTLFireability-13
lola: time limit : 359 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-007007-CTLFireability-02: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-03: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-007007-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 3/359 6/32 RefineWMG-PT-007007-CTLFireability-13 1439226 m, 287845 m/sec, 2404937 t fired, .
Time elapsed: 5 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-007007-CTLFireability-02: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-03: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-007007-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 8/359 14/32 RefineWMG-PT-007007-CTLFireability-13 3473346 m, 406824 m/sec, 6834956 t fired, .
Time elapsed: 10 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-007007-CTLFireability-02: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-03: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-007007-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 13/359 18/32 RefineWMG-PT-007007-CTLFireability-13 4324613 m, 170253 m/sec, 14162531 t fired, .
Time elapsed: 15 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-007007-CTLFireability-02: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-03: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-007007-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 18/359 21/32 RefineWMG-PT-007007-CTLFireability-13 5079917 m, 151060 m/sec, 21543341 t fired, .
Time elapsed: 20 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-007007-CTLFireability-02: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-03: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-007007-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 23/359 27/32 RefineWMG-PT-007007-CTLFireability-13 6535440 m, 291104 m/sec, 27110127 t fired, .
Time elapsed: 25 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-007007-CTLFireability-02: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-03: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-007007-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 28/359 30/32 RefineWMG-PT-007007-CTLFireability-13 7393786 m, 171669 m/sec, 33832150 t fired, .
Time elapsed: 30 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 12
lola: CANCELED task # 31 (type EXCL) for RefineWMG-PT-007007-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-007007-CTLFireability-02: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-03: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-007007-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-007007-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 35 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
lola: LAUNCH task # 28 (type EXCL) for 27 RefineWMG-PT-007007-CTLFireability-12
lola: time limit : 396 sec
lola: memory limit: 32 pages
lola: FINISHED task # 28 (type EXCL) for RefineWMG-PT-007007-CTLFireability-12
lola: result : false
lola: markings : 97
lola: fired transitions : 338
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 24 RefineWMG-PT-007007-CTLFireability-10
lola: time limit : 445 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for RefineWMG-PT-007007-CTLFireability-10
lola: result : true
lola: markings : 146
lola: fired transitions : 235
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 RefineWMG-PT-007007-CTLFireability-07
lola: time limit : 509 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-007007-CTLFireability-02: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-03: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-10: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-007007-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-007007-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 5/509 11/32 RefineWMG-PT-007007-CTLFireability-07 2731475 m, 546295 m/sec, 8366338 t fired, .
Time elapsed: 40 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-007007-CTLFireability-02: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-03: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-10: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-007007-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-007007-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 10/509 21/32 RefineWMG-PT-007007-CTLFireability-07 5224746 m, 498654 m/sec, 16246124 t fired, .
Time elapsed: 45 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-007007-CTLFireability-02: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-03: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-10: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-007007-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-007007-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 15/509 31/32 RefineWMG-PT-007007-CTLFireability-07 7673300 m, 489710 m/sec, 24127626 t fired, .
Time elapsed: 50 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
lola: CANCELED task # 19 (type EXCL) for RefineWMG-PT-007007-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-007007-CTLFireability-02: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-03: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-10: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-007007-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-007007-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-007007-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 55 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
lola: LAUNCH task # 16 (type EXCL) for 15 RefineWMG-PT-007007-CTLFireability-06
lola: time limit : 590 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-007007-CTLFireability-02: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-03: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-10: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-007007-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-007007-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-007007-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 5/590 12/32 RefineWMG-PT-007007-CTLFireability-06 2861459 m, 572291 m/sec, 7592717 t fired, .
Time elapsed: 60 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-007007-CTLFireability-02: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-03: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-10: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-007007-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-007007-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-007007-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 10/590 23/32 RefineWMG-PT-007007-CTLFireability-06 5660413 m, 559790 m/sec, 14789211 t fired, .
Time elapsed: 65 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
lola: CANCELED task # 16 (type EXCL) for RefineWMG-PT-007007-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-007007-CTLFireability-02: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-03: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-10: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-007007-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-007007-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-007007-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-007007-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 70 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
lola: LAUNCH task # 10 (type EXCL) for 9 RefineWMG-PT-007007-CTLFireability-04
lola: time limit : 706 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for RefineWMG-PT-007007-CTLFireability-04
lola: result : false
lola: markings : 4298
lola: fired transitions : 21116
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 RefineWMG-PT-007007-CTLFireability-00
lola: time limit : 882 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for RefineWMG-PT-007007-CTLFireability-00
lola: result : true
lola: markings : 874
lola: fired transitions : 1685
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 36 (type EXCL) for 33 RefineWMG-PT-007007-CTLFireability-15
lola: time limit : 1176 sec
lola: memory limit: 32 pages
lola: FINISHED task # 36 (type EXCL) for RefineWMG-PT-007007-CTLFireability-15
lola: result : true
lola: markings : 9240
lola: fired transitions : 33486
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 RefineWMG-PT-007007-CTLFireability-09
lola: time limit : 1765 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-007007-CTLFireability-00: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-02: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-03: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-04: CTL false CTL model checker
RefineWMG-PT-007007-CTLFireability-10: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-12: CTL false CTL model checker
RefineWMG-PT-007007-CTLFireability-15: EFAG false tscc_search
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-007007-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-007007-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-007007-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 5/1765 9/32 RefineWMG-PT-007007-CTLFireability-09 2128679 m, 425735 m/sec, 7593456 t fired, .
Time elapsed: 75 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-007007-CTLFireability-00: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-02: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-03: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-04: CTL false CTL model checker
RefineWMG-PT-007007-CTLFireability-10: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-12: CTL false CTL model checker
RefineWMG-PT-007007-CTLFireability-15: EFAG false tscc_search
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-007007-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-007007-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-007007-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 10/1765 16/32 RefineWMG-PT-007007-CTLFireability-09 3901824 m, 354629 m/sec, 14816444 t fired, .
Time elapsed: 80 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-007007-CTLFireability-00: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-02: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-03: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-04: CTL false CTL model checker
RefineWMG-PT-007007-CTLFireability-10: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-12: CTL false CTL model checker
RefineWMG-PT-007007-CTLFireability-15: EFAG false tscc_search
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-007007-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-007007-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-007007-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 15/1765 23/32 RefineWMG-PT-007007-CTLFireability-09 5555926 m, 330820 m/sec, 21901281 t fired, .
Time elapsed: 85 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-007007-CTLFireability-00: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-02: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-03: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-04: CTL false CTL model checker
RefineWMG-PT-007007-CTLFireability-10: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-12: CTL false CTL model checker
RefineWMG-PT-007007-CTLFireability-15: EFAG false tscc_search
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-007007-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-007007-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-007007-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 20/1765 29/32 RefineWMG-PT-007007-CTLFireability-09 7109637 m, 310742 m/sec, 28852644 t fired, .
Time elapsed: 90 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
lola: CANCELED task # 22 (type EXCL) for RefineWMG-PT-007007-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-007007-CTLFireability-00: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-02: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-03: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-04: CTL false CTL model checker
RefineWMG-PT-007007-CTLFireability-10: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-12: CTL false CTL model checker
RefineWMG-PT-007007-CTLFireability-15: EFAG false tscc_search
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-007007-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-007007-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-007007-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-007007-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-007007-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 95 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
lola: LAUNCH task # 13 (type EXCL) for 12 RefineWMG-PT-007007-CTLFireability-05
lola: time limit : 3505 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for RefineWMG-PT-007007-CTLFireability-05
lola: result : false
lola: markings : 85896
lola: fired transitions : 306784
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 12
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-007007-CTLFireability-00: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-02: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-03: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-04: CTL false CTL model checker
RefineWMG-PT-007007-CTLFireability-05: CTL false CTL model checker
RefineWMG-PT-007007-CTLFireability-06: CTL unknown AGGR
RefineWMG-PT-007007-CTLFireability-07: CTL unknown AGGR
RefineWMG-PT-007007-CTLFireability-09: CTL unknown AGGR
RefineWMG-PT-007007-CTLFireability-10: CTL true CTL model checker
RefineWMG-PT-007007-CTLFireability-12: CTL false CTL model checker
RefineWMG-PT-007007-CTLFireability-13: CTL unknown AGGR
RefineWMG-PT-007007-CTLFireability-15: EFAG false tscc_search
Time elapsed: 95 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RefineWMG-PT-007007"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is RefineWMG-PT-007007, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r327-tall-167889199800562"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/RefineWMG-PT-007007.tgz
mv RefineWMG-PT-007007 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;