About the Execution of LoLa+red for RefineWMG-PT-005005
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 2000.292 | 49133.00 | 49394.00 | 534.20 | TTT?F?TTTFFFFFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r327-tall-167889199800546.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is RefineWMG-PT-005005, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r327-tall-167889199800546
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 460K
-rw-r--r-- 1 mcc users 6.4K Feb 26 15:51 CTLCardinality.txt
-rw-r--r-- 1 mcc users 71K Feb 26 15:51 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K Feb 26 15:49 CTLFireability.txt
-rw-r--r-- 1 mcc users 57K Feb 26 15:49 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.9K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:43 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:43 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 16:43 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:43 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.4K Feb 26 15:52 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 87K Feb 26 15:52 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.8K Feb 26 15:52 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 92K Feb 26 15:52 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:43 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:43 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 7 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 14K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME RefineWMG-PT-005005-CTLFireability-00
FORMULA_NAME RefineWMG-PT-005005-CTLFireability-01
FORMULA_NAME RefineWMG-PT-005005-CTLFireability-02
FORMULA_NAME RefineWMG-PT-005005-CTLFireability-03
FORMULA_NAME RefineWMG-PT-005005-CTLFireability-04
FORMULA_NAME RefineWMG-PT-005005-CTLFireability-05
FORMULA_NAME RefineWMG-PT-005005-CTLFireability-06
FORMULA_NAME RefineWMG-PT-005005-CTLFireability-07
FORMULA_NAME RefineWMG-PT-005005-CTLFireability-08
FORMULA_NAME RefineWMG-PT-005005-CTLFireability-09
FORMULA_NAME RefineWMG-PT-005005-CTLFireability-10
FORMULA_NAME RefineWMG-PT-005005-CTLFireability-11
FORMULA_NAME RefineWMG-PT-005005-CTLFireability-12
FORMULA_NAME RefineWMG-PT-005005-CTLFireability-13
FORMULA_NAME RefineWMG-PT-005005-CTLFireability-14
FORMULA_NAME RefineWMG-PT-005005-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679052290074
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RefineWMG-PT-005005
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-17 11:24:51] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-17 11:24:51] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-17 11:24:51] [INFO ] Load time of PNML (sax parser for PT used): 23 ms
[2023-03-17 11:24:51] [INFO ] Transformed 29 places.
[2023-03-17 11:24:51] [INFO ] Transformed 23 transitions.
[2023-03-17 11:24:51] [INFO ] Parsed PT model containing 29 places and 23 transitions and 68 arcs in 75 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 10 ms.
Initial state reduction rules removed 2 formulas.
FORMULA RefineWMG-PT-005005-CTLFireability-07 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA RefineWMG-PT-005005-CTLFireability-08 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 29 out of 29 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 29/29 places, 23/23 transitions.
Applied a total of 0 rules in 8 ms. Remains 29 /29 variables (removed 0) and now considering 23/23 (removed 0) transitions.
// Phase 1: matrix 23 rows 29 cols
[2023-03-17 11:24:51] [INFO ] Computed 12 place invariants in 8 ms
[2023-03-17 11:24:52] [INFO ] Dead Transitions using invariants and state equation in 375 ms found 0 transitions.
[2023-03-17 11:24:52] [INFO ] Invariant cache hit.
[2023-03-17 11:24:52] [INFO ] Implicit Places using invariants in 33 ms returned []
[2023-03-17 11:24:52] [INFO ] Invariant cache hit.
[2023-03-17 11:24:52] [INFO ] Implicit Places using invariants and state equation in 36 ms returned []
Implicit Place search using SMT with State Equation took 71 ms to find 0 implicit places.
[2023-03-17 11:24:52] [INFO ] Invariant cache hit.
[2023-03-17 11:24:52] [INFO ] Dead Transitions using invariants and state equation in 29 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 506 ms. Remains : 29/29 places, 23/23 transitions.
Support contains 29 out of 29 places after structural reductions.
[2023-03-17 11:24:52] [INFO ] Flatten gal took : 18 ms
[2023-03-17 11:24:52] [INFO ] Flatten gal took : 6 ms
[2023-03-17 11:24:52] [INFO ] Input system was already deterministic with 23 transitions.
Finished random walk after 3166 steps, including 0 resets, run visited all 40 properties in 52 ms. (steps per millisecond=60 )
[2023-03-17 11:24:52] [INFO ] Flatten gal took : 4 ms
[2023-03-17 11:24:52] [INFO ] Flatten gal took : 3 ms
[2023-03-17 11:24:52] [INFO ] Input system was already deterministic with 23 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 29/29 places, 23/23 transitions.
Graph (trivial) has 8 edges and 29 vertex of which 4 / 29 are part of one of the 2 SCC in 2 ms
Free SCC test removed 2 places
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Reduce places removed 2 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 2 place count 25 transition count 20
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 1 ms
Reduce places removed 8 places and 0 transitions.
Iterating global reduction 1 with 12 rules applied. Total rules applied 14 place count 17 transition count 16
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 1 with 1 rules applied. Total rules applied 15 place count 17 transition count 15
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 16 place count 16 transition count 15
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 1 Pre rules applied. Total rules applied 16 place count 16 transition count 14
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 18 place count 15 transition count 14
Applied a total of 18 rules in 9 ms. Remains 15 /29 variables (removed 14) and now considering 14/23 (removed 9) transitions.
// Phase 1: matrix 14 rows 15 cols
[2023-03-17 11:24:52] [INFO ] Computed 6 place invariants in 1 ms
[2023-03-17 11:24:52] [INFO ] Dead Transitions using invariants and state equation in 26 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 36 ms. Remains : 15/29 places, 14/23 transitions.
[2023-03-17 11:24:52] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:24:52] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:24:52] [INFO ] Input system was already deterministic with 14 transitions.
Starting structural reductions in LTL mode, iteration 0 : 29/29 places, 23/23 transitions.
Applied a total of 0 rules in 0 ms. Remains 29 /29 variables (removed 0) and now considering 23/23 (removed 0) transitions.
// Phase 1: matrix 23 rows 29 cols
[2023-03-17 11:24:52] [INFO ] Computed 12 place invariants in 0 ms
[2023-03-17 11:24:52] [INFO ] Dead Transitions using invariants and state equation in 32 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 32 ms. Remains : 29/29 places, 23/23 transitions.
[2023-03-17 11:24:52] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:24:52] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:24:52] [INFO ] Input system was already deterministic with 23 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 29/29 places, 23/23 transitions.
Graph (trivial) has 13 edges and 29 vertex of which 8 / 29 are part of one of the 4 SCC in 0 ms
Free SCC test removed 4 places
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Reduce places removed 4 places and 0 transitions.
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 4 place count 21 transition count 16
Performed 5 Post agglomeration using F-continuation condition.Transition count delta: 5
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 1 with 15 rules applied. Total rules applied 19 place count 11 transition count 11
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded 3 transitions
Performed 3 trivial Post agglomeration. Transition count delta: 3
Iterating post reduction 1 with 3 rules applied. Total rules applied 22 place count 11 transition count 8
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 2 with 3 rules applied. Total rules applied 25 place count 8 transition count 8
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 27 place count 7 transition count 7
Applied a total of 27 rules in 2 ms. Remains 7 /29 variables (removed 22) and now considering 7/23 (removed 16) transitions.
// Phase 1: matrix 7 rows 7 cols
[2023-03-17 11:24:52] [INFO ] Computed 3 place invariants in 1 ms
[2023-03-17 11:24:52] [INFO ] Dead Transitions using invariants and state equation in 27 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 31 ms. Remains : 7/29 places, 7/23 transitions.
[2023-03-17 11:24:52] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:24:52] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:24:52] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 29/29 places, 23/23 transitions.
Applied a total of 0 rules in 1 ms. Remains 29 /29 variables (removed 0) and now considering 23/23 (removed 0) transitions.
// Phase 1: matrix 23 rows 29 cols
[2023-03-17 11:24:52] [INFO ] Computed 12 place invariants in 0 ms
[2023-03-17 11:24:52] [INFO ] Dead Transitions using invariants and state equation in 42 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 44 ms. Remains : 29/29 places, 23/23 transitions.
[2023-03-17 11:24:52] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:24:52] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:24:52] [INFO ] Input system was already deterministic with 23 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 29/29 places, 23/23 transitions.
Graph (trivial) has 11 edges and 29 vertex of which 8 / 29 are part of one of the 4 SCC in 0 ms
Free SCC test removed 4 places
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Reduce places removed 4 places and 0 transitions.
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 4 place count 21 transition count 16
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 1 with 9 rules applied. Total rules applied 13 place count 15 transition count 13
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 1 with 1 rules applied. Total rules applied 14 place count 15 transition count 12
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 15 place count 14 transition count 12
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 2 Pre rules applied. Total rules applied 15 place count 14 transition count 10
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 3 with 4 rules applied. Total rules applied 19 place count 12 transition count 10
Applied a total of 19 rules in 3 ms. Remains 12 /29 variables (removed 17) and now considering 10/23 (removed 13) transitions.
// Phase 1: matrix 10 rows 12 cols
[2023-03-17 11:24:52] [INFO ] Computed 5 place invariants in 0 ms
[2023-03-17 11:24:52] [INFO ] Dead Transitions using invariants and state equation in 21 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 24 ms. Remains : 12/29 places, 10/23 transitions.
[2023-03-17 11:24:52] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:24:52] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:24:52] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 29/29 places, 23/23 transitions.
Applied a total of 0 rules in 0 ms. Remains 29 /29 variables (removed 0) and now considering 23/23 (removed 0) transitions.
// Phase 1: matrix 23 rows 29 cols
[2023-03-17 11:24:52] [INFO ] Computed 12 place invariants in 0 ms
[2023-03-17 11:24:52] [INFO ] Dead Transitions using invariants and state equation in 34 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 35 ms. Remains : 29/29 places, 23/23 transitions.
[2023-03-17 11:24:52] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:24:52] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:24:52] [INFO ] Input system was already deterministic with 23 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 29/29 places, 23/23 transitions.
Graph (trivial) has 3 edges and 29 vertex of which 2 / 29 are part of one of the 1 SCC in 0 ms
Free SCC test removed 1 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Reduce places removed 1 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 4 place count 25 transition count 21
Applied a total of 4 rules in 2 ms. Remains 25 /29 variables (removed 4) and now considering 21/23 (removed 2) transitions.
// Phase 1: matrix 21 rows 25 cols
[2023-03-17 11:24:52] [INFO ] Computed 10 place invariants in 1 ms
[2023-03-17 11:24:52] [INFO ] Dead Transitions using invariants and state equation in 35 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 39 ms. Remains : 25/29 places, 21/23 transitions.
[2023-03-17 11:24:52] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:24:52] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:24:52] [INFO ] Input system was already deterministic with 21 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 29/29 places, 23/23 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 27 transition count 22
Applied a total of 3 rules in 2 ms. Remains 27 /29 variables (removed 2) and now considering 22/23 (removed 1) transitions.
// Phase 1: matrix 22 rows 27 cols
[2023-03-17 11:24:52] [INFO ] Computed 11 place invariants in 1 ms
[2023-03-17 11:24:52] [INFO ] Dead Transitions using invariants and state equation in 31 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 33 ms. Remains : 27/29 places, 22/23 transitions.
[2023-03-17 11:24:52] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:24:52] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:24:52] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in LTL mode, iteration 0 : 29/29 places, 23/23 transitions.
Applied a total of 0 rules in 0 ms. Remains 29 /29 variables (removed 0) and now considering 23/23 (removed 0) transitions.
// Phase 1: matrix 23 rows 29 cols
[2023-03-17 11:24:52] [INFO ] Computed 12 place invariants in 0 ms
[2023-03-17 11:24:52] [INFO ] Dead Transitions using invariants and state equation in 26 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 27 ms. Remains : 29/29 places, 23/23 transitions.
[2023-03-17 11:24:52] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:24:52] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:24:52] [INFO ] Input system was already deterministic with 23 transitions.
Starting structural reductions in LTL mode, iteration 0 : 29/29 places, 23/23 transitions.
Applied a total of 0 rules in 0 ms. Remains 29 /29 variables (removed 0) and now considering 23/23 (removed 0) transitions.
[2023-03-17 11:24:52] [INFO ] Invariant cache hit.
[2023-03-17 11:24:52] [INFO ] Dead Transitions using invariants and state equation in 40 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 40 ms. Remains : 29/29 places, 23/23 transitions.
[2023-03-17 11:24:52] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:24:52] [INFO ] Flatten gal took : 8 ms
[2023-03-17 11:24:52] [INFO ] Input system was already deterministic with 23 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 29/29 places, 23/23 transitions.
Graph (trivial) has 14 edges and 29 vertex of which 10 / 29 are part of one of the 5 SCC in 0 ms
Free SCC test removed 5 places
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Reduce places removed 5 places and 0 transitions.
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 0 with 4 rules applied. Total rules applied 5 place count 19 transition count 14
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 8 places and 0 transitions.
Iterating global reduction 1 with 12 rules applied. Total rules applied 17 place count 11 transition count 10
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 1 with 2 rules applied. Total rules applied 19 place count 11 transition count 8
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 21 place count 9 transition count 8
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 1 Pre rules applied. Total rules applied 21 place count 9 transition count 7
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 23 place count 8 transition count 7
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 25 place count 7 transition count 6
Applied a total of 25 rules in 3 ms. Remains 7 /29 variables (removed 22) and now considering 6/23 (removed 17) transitions.
// Phase 1: matrix 6 rows 7 cols
[2023-03-17 11:24:52] [INFO ] Computed 3 place invariants in 0 ms
[2023-03-17 11:24:52] [INFO ] Dead Transitions using invariants and state equation in 17 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 21 ms. Remains : 7/29 places, 6/23 transitions.
[2023-03-17 11:24:52] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:24:52] [INFO ] Flatten gal took : 0 ms
[2023-03-17 11:24:52] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 29/29 places, 23/23 transitions.
Graph (trivial) has 5 edges and 29 vertex of which 2 / 29 are part of one of the 1 SCC in 0 ms
Free SCC test removed 1 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Reduce places removed 1 places and 0 transitions.
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 0 with 9 rules applied. Total rules applied 10 place count 21 transition count 19
Applied a total of 10 rules in 1 ms. Remains 21 /29 variables (removed 8) and now considering 19/23 (removed 4) transitions.
// Phase 1: matrix 19 rows 21 cols
[2023-03-17 11:24:52] [INFO ] Computed 8 place invariants in 1 ms
[2023-03-17 11:24:52] [INFO ] Dead Transitions using invariants and state equation in 40 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 42 ms. Remains : 21/29 places, 19/23 transitions.
[2023-03-17 11:24:52] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:24:52] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:24:52] [INFO ] Input system was already deterministic with 19 transitions.
Starting structural reductions in LTL mode, iteration 0 : 29/29 places, 23/23 transitions.
Applied a total of 0 rules in 1 ms. Remains 29 /29 variables (removed 0) and now considering 23/23 (removed 0) transitions.
// Phase 1: matrix 23 rows 29 cols
[2023-03-17 11:24:52] [INFO ] Computed 12 place invariants in 0 ms
[2023-03-17 11:24:52] [INFO ] Dead Transitions using invariants and state equation in 31 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 33 ms. Remains : 29/29 places, 23/23 transitions.
[2023-03-17 11:24:52] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:24:52] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:24:52] [INFO ] Input system was already deterministic with 23 transitions.
Starting structural reductions in LTL mode, iteration 0 : 29/29 places, 23/23 transitions.
Applied a total of 0 rules in 0 ms. Remains 29 /29 variables (removed 0) and now considering 23/23 (removed 0) transitions.
[2023-03-17 11:24:52] [INFO ] Invariant cache hit.
[2023-03-17 11:24:53] [INFO ] Dead Transitions using invariants and state equation in 32 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 32 ms. Remains : 29/29 places, 23/23 transitions.
[2023-03-17 11:24:53] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:24:53] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:24:53] [INFO ] Input system was already deterministic with 23 transitions.
[2023-03-17 11:24:53] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:24:53] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:24:53] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-17 11:24:53] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 29 places, 23 transitions and 68 arcs took 1 ms.
Total runtime 1563 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT RefineWMG-PT-005005
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/377
CTLFireability
FORMULA RefineWMG-PT-005005-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-005005-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-005005-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-005005-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-005005-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-005005-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-005005-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-005005-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-005005-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-005005-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-005005-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-005005-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679052339207
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/377/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/377/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/377/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 17 (type EXCL) for 16 RefineWMG-PT-005005-CTLFireability-04
lola: time limit : 180 sec
lola: memory limit: 32 pages
lola: FINISHED task # 17 (type EXCL) for RefineWMG-PT-005005-CTLFireability-04
lola: result : false
lola: markings : 42
lola: fired transitions : 142
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 32 (type EXCL) for 31 RefineWMG-PT-005005-CTLFireability-11
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: FINISHED task # 32 (type EXCL) for RefineWMG-PT-005005-CTLFireability-11
lola: result : false
lola: markings : 6
lola: fired transitions : 24
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: LAUNCH task # 29 (type EXCL) for 28 RefineWMG-PT-005005-CTLFireability-10
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: FINISHED task # 29 (type EXCL) for RefineWMG-PT-005005-CTLFireability-10
lola: result : false
lola: markings : 6
lola: fired transitions : 6
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 57 (type EXCL) for 37 RefineWMG-PT-005005-CTLFireability-13
lola: time limit : 225 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 55 (type FNDP) for 37 RefineWMG-PT-005005-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 56 (type EQUN) for 37 RefineWMG-PT-005005-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 58 (type SRCH) for 37 RefineWMG-PT-005005-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: FINISHED task # 58 (type SRCH) for RefineWMG-PT-005005-CTLFireability-13
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 55 (type FNDP) for RefineWMG-PT-005005-CTLFireability-13 (obsolete)
lola: CANCELED task # 56 (type EQUN) for RefineWMG-PT-005005-CTLFireability-13 (obsolete)
lola: CANCELED task # 57 (type EXCL) for RefineWMG-PT-005005-CTLFireability-13 (obsolete)
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 52 (type EXCL) for 51 RefineWMG-PT-005005-CTLFireability-15
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: FINISHED task # 55 (type FNDP) for RefineWMG-PT-005005-CTLFireability-13
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 52 (type EXCL) for RefineWMG-PT-005005-CTLFireability-15
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 26 (type EXCL) for 25 RefineWMG-PT-005005-CTLFireability-09
lola: time limit : 327 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for RefineWMG-PT-005005-CTLFireability-09
lola: result : false
lola: markings : 6
lola: fired transitions : 18
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: LAUNCH task # 14 (type EXCL) for 9 RefineWMG-PT-005005-CTLFireability-03
lola: time limit : 400 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: planning for (null) stopped (result already fixed).
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
sara: try reading problem file /home/mcc/execution/377/CTLFireability-56.sara.
lola: FINISHED task # 56 (type EQUN) for RefineWMG-PT-005005-CTLFireability-13
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-005005-CTLFireability-04: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-09: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-10: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-11: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-13: CONJ false search / frozen tokens
RefineWMG-PT-005005-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-005005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-005005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-005005-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-005005-CTLFireability-03: DISJ 0 1 1 0 2 0 0 0
RefineWMG-PT-005005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-005005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-005005-CTLFireability-12: F 0 1 0 0 1 0 0 0
RefineWMG-PT-005005-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 5/400 12/32 RefineWMG-PT-005005-CTLFireability-03 2763840 m, 552768 m/sec, 8030322 t fired, .
Time elapsed: 5 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-005005-CTLFireability-04: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-09: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-10: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-11: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-13: CONJ false search / frozen tokens
RefineWMG-PT-005005-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-005005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-005005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-005005-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-005005-CTLFireability-03: DISJ 0 1 1 0 2 0 0 0
RefineWMG-PT-005005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-005005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-005005-CTLFireability-12: F 0 1 0 0 1 0 0 0
RefineWMG-PT-005005-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 10/400 22/32 RefineWMG-PT-005005-CTLFireability-03 5383653 m, 523962 m/sec, 15974826 t fired, .
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RefineWMG-PT-005005-CTLFireability-04: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-09: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-10: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-11: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-13: CONJ false search / frozen tokens
RefineWMG-PT-005005-CTLFireability-15: CTL false CTL model checker
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RefineWMG-PT-005005-CTLFireability-03: DISJ 0 1 0 0 2 0 1 0
RefineWMG-PT-005005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-005005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-005005-CTLFireability-12: F 0 1 0 0 1 0 0 0
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lola: LAUNCH task # 49 (type EXCL) for 48 RefineWMG-PT-005005-CTLFireability-14
lola: time limit : 448 sec
lola: memory limit: 32 pages
lola: FINISHED task # 49 (type EXCL) for RefineWMG-PT-005005-CTLFireability-14
lola: result : false
lola: markings : 5
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 RefineWMG-PT-005005-CTLFireability-01
lola: time limit : 512 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for RefineWMG-PT-005005-CTLFireability-01
lola: result : true
lola: markings : 365458
lola: fired transitions : 1871157
lola: time used : 1.000000
lola: memory pages used : 2
lola: LAUNCH task # 60 (type EXCL) for 34 RefineWMG-PT-005005-CTLFireability-12
lola: time limit : 597 sec
lola: memory limit: 32 pages
lola: FINISHED task # 60 (type EXCL) for RefineWMG-PT-005005-CTLFireability-12
lola: result : true
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 59 (type EXCL) for 9 RefineWMG-PT-005005-CTLFireability-03
lola: time limit : 716 sec
lola: memory limit: 32 pages
lola: FINISHED task # 59 (type EXCL) for RefineWMG-PT-005005-CTLFireability-03
lola: result : false
lola: markings : 3
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 RefineWMG-PT-005005-CTLFireability-02
lola: time limit : 896 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for RefineWMG-PT-005005-CTLFireability-02
lola: result : true
lola: markings : 1296
lola: fired transitions : 8688
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 RefineWMG-PT-005005-CTLFireability-00
lola: time limit : 1194 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for RefineWMG-PT-005005-CTLFireability-00
lola: result : true
lola: markings : 700
lola: fired transitions : 3742
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 20 (type EXCL) for 19 RefineWMG-PT-005005-CTLFireability-05
lola: time limit : 1792 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-005005-CTLFireability-00: CTL true CTL model checker
RefineWMG-PT-005005-CTLFireability-01: CTL true CTL model checker
RefineWMG-PT-005005-CTLFireability-02: CTL true CTL model checker
RefineWMG-PT-005005-CTLFireability-04: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-09: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-10: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-11: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-12: F false state space / EG
RefineWMG-PT-005005-CTLFireability-13: CONJ false search / frozen tokens
RefineWMG-PT-005005-CTLFireability-14: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-005005-CTLFireability-03: DISJ 0 0 0 0 3 0 1 0
RefineWMG-PT-005005-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-005005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 4/1792 6/32 RefineWMG-PT-005005-CTLFireability-05 1409165 m, 281833 m/sec, 8801487 t fired, .
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RefineWMG-PT-005005-CTLFireability-00: CTL true CTL model checker
RefineWMG-PT-005005-CTLFireability-01: CTL true CTL model checker
RefineWMG-PT-005005-CTLFireability-02: CTL true CTL model checker
RefineWMG-PT-005005-CTLFireability-04: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-09: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-10: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-11: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-12: F false state space / EG
RefineWMG-PT-005005-CTLFireability-13: CONJ false search / frozen tokens
RefineWMG-PT-005005-CTLFireability-14: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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20 CTL EXCL 9/1792 13/32 RefineWMG-PT-005005-CTLFireability-05 3067218 m, 331610 m/sec, 19507154 t fired, .
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RefineWMG-PT-005005-CTLFireability-00: CTL true CTL model checker
RefineWMG-PT-005005-CTLFireability-01: CTL true CTL model checker
RefineWMG-PT-005005-CTLFireability-02: CTL true CTL model checker
RefineWMG-PT-005005-CTLFireability-04: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-09: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-10: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-11: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-12: F false state space / EG
RefineWMG-PT-005005-CTLFireability-13: CONJ false search / frozen tokens
RefineWMG-PT-005005-CTLFireability-14: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 14/1792 19/32 RefineWMG-PT-005005-CTLFireability-05 4636743 m, 313905 m/sec, 29847343 t fired, .
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RefineWMG-PT-005005-CTLFireability-00: CTL true CTL model checker
RefineWMG-PT-005005-CTLFireability-01: CTL true CTL model checker
RefineWMG-PT-005005-CTLFireability-02: CTL true CTL model checker
RefineWMG-PT-005005-CTLFireability-04: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-09: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-10: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-11: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-12: F false state space / EG
RefineWMG-PT-005005-CTLFireability-13: CONJ false search / frozen tokens
RefineWMG-PT-005005-CTLFireability-14: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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20 CTL EXCL 19/1792 25/32 RefineWMG-PT-005005-CTLFireability-05 6122790 m, 297209 m/sec, 39975851 t fired, .
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RefineWMG-PT-005005-CTLFireability-00: CTL true CTL model checker
RefineWMG-PT-005005-CTLFireability-01: CTL true CTL model checker
RefineWMG-PT-005005-CTLFireability-02: CTL true CTL model checker
RefineWMG-PT-005005-CTLFireability-04: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-09: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-10: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-11: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-12: F false state space / EG
RefineWMG-PT-005005-CTLFireability-13: CONJ false search / frozen tokens
RefineWMG-PT-005005-CTLFireability-14: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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20 CTL EXCL 24/1792 31/32 RefineWMG-PT-005005-CTLFireability-05 7530943 m, 281630 m/sec, 49836361 t fired, .
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RefineWMG-PT-005005-CTLFireability-00: CTL true CTL model checker
RefineWMG-PT-005005-CTLFireability-01: CTL true CTL model checker
RefineWMG-PT-005005-CTLFireability-02: CTL true CTL model checker
RefineWMG-PT-005005-CTLFireability-04: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-09: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-10: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-11: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-12: F false state space / EG
RefineWMG-PT-005005-CTLFireability-13: CONJ false search / frozen tokens
RefineWMG-PT-005005-CTLFireability-14: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-005005-CTLFireability-03: DISJ 0 0 0 0 3 0 1 0
RefineWMG-PT-005005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
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lola: result : true
lola: markings : 1
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-005005-CTLFireability-00: CTL true CTL model checker
RefineWMG-PT-005005-CTLFireability-01: CTL true CTL model checker
RefineWMG-PT-005005-CTLFireability-02: CTL true CTL model checker
RefineWMG-PT-005005-CTLFireability-03: DISJ unknown DISJ
RefineWMG-PT-005005-CTLFireability-04: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-05: CTL unknown AGGR
RefineWMG-PT-005005-CTLFireability-06: CTL true CTL model checker
RefineWMG-PT-005005-CTLFireability-09: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-10: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-11: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-12: F false state space / EG
RefineWMG-PT-005005-CTLFireability-13: CONJ false search / frozen tokens
RefineWMG-PT-005005-CTLFireability-14: CTL false CTL model checker
RefineWMG-PT-005005-CTLFireability-15: CTL false CTL model checker
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RefineWMG-PT-005005"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is RefineWMG-PT-005005, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r327-tall-167889199800546"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/RefineWMG-PT-005005.tgz
mv RefineWMG-PT-005005 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;