About the Execution of LoLa+red for Referendum-PT-0100
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 2033.319 | 397739.00 | 386440.00 | 1320.00 | F?T??T??TTFFFFFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r327-tall-167889199700498.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is Referendum-PT-0100, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r327-tall-167889199700498
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 3.7M
-rw-r--r-- 1 mcc users 120K Feb 26 17:35 CTLCardinality.txt
-rw-r--r-- 1 mcc users 628K Feb 26 17:35 CTLCardinality.xml
-rw-r--r-- 1 mcc users 41K Feb 26 17:30 CTLFireability.txt
-rw-r--r-- 1 mcc users 309K Feb 26 17:30 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.8K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 59K Feb 25 16:42 LTLCardinality.txt
-rw-r--r-- 1 mcc users 212K Feb 25 16:42 LTLCardinality.xml
-rw-r--r-- 1 mcc users 19K Feb 25 16:42 LTLFireability.txt
-rw-r--r-- 1 mcc users 106K Feb 25 16:42 LTLFireability.xml
-rw-r--r-- 1 mcc users 158K Feb 26 17:44 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 802K Feb 26 17:44 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 129K Feb 26 17:38 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 986K Feb 26 17:38 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 25 16:42 UpperBounds.txt
-rw-r--r-- 1 mcc users 27K Feb 25 16:42 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 113K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME Referendum-PT-0100-CTLFireability-00
FORMULA_NAME Referendum-PT-0100-CTLFireability-01
FORMULA_NAME Referendum-PT-0100-CTLFireability-02
FORMULA_NAME Referendum-PT-0100-CTLFireability-03
FORMULA_NAME Referendum-PT-0100-CTLFireability-04
FORMULA_NAME Referendum-PT-0100-CTLFireability-05
FORMULA_NAME Referendum-PT-0100-CTLFireability-06
FORMULA_NAME Referendum-PT-0100-CTLFireability-07
FORMULA_NAME Referendum-PT-0100-CTLFireability-08
FORMULA_NAME Referendum-PT-0100-CTLFireability-09
FORMULA_NAME Referendum-PT-0100-CTLFireability-10
FORMULA_NAME Referendum-PT-0100-CTLFireability-11
FORMULA_NAME Referendum-PT-0100-CTLFireability-12
FORMULA_NAME Referendum-PT-0100-CTLFireability-13
FORMULA_NAME Referendum-PT-0100-CTLFireability-14
FORMULA_NAME Referendum-PT-0100-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679050139995
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Referendum-PT-0100
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-17 10:49:01] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-17 10:49:01] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-17 10:49:01] [INFO ] Load time of PNML (sax parser for PT used): 48 ms
[2023-03-17 10:49:01] [INFO ] Transformed 301 places.
[2023-03-17 10:49:01] [INFO ] Transformed 201 transitions.
[2023-03-17 10:49:01] [INFO ] Found NUPN structural information;
[2023-03-17 10:49:01] [INFO ] Parsed PT model containing 301 places and 201 transitions and 501 arcs in 107 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 23 ms.
Support contains 101 out of 301 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 301/301 places, 201/201 transitions.
Reduce places removed 200 places and 0 transitions.
Ensure Unique test removed 100 transitions
Reduce isomorphic transitions removed 100 transitions.
Iterating post reduction 0 with 300 rules applied. Total rules applied 300 place count 101 transition count 101
Applied a total of 300 rules in 10 ms. Remains 101 /301 variables (removed 200) and now considering 101/201 (removed 100) transitions.
// Phase 1: matrix 101 rows 101 cols
[2023-03-17 10:49:01] [INFO ] Computed 0 place invariants in 8 ms
[2023-03-17 10:49:02] [INFO ] Implicit Places using invariants in 360 ms returned []
[2023-03-17 10:49:02] [INFO ] Invariant cache hit.
[2023-03-17 10:49:02] [INFO ] Implicit Places using invariants and state equation in 81 ms returned []
Implicit Place search using SMT with State Equation took 464 ms to find 0 implicit places.
[2023-03-17 10:49:02] [INFO ] Invariant cache hit.
[2023-03-17 10:49:02] [INFO ] Dead Transitions using invariants and state equation in 71 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 101/301 places, 101/201 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 546 ms. Remains : 101/301 places, 101/201 transitions.
Support contains 101 out of 101 places after structural reductions.
[2023-03-17 10:49:02] [INFO ] Flatten gal took : 52 ms
[2023-03-17 10:49:02] [INFO ] Flatten gal took : 32 ms
[2023-03-17 10:49:02] [INFO ] Input system was already deterministic with 101 transitions.
Incomplete random walk after 10000 steps, including 98 resets, run finished after 300 ms. (steps per millisecond=33 ) properties (out of 40) seen :37
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 56 ms. (steps per millisecond=178 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 42 ms. (steps per millisecond=238 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 91 ms. (steps per millisecond=109 ) properties (out of 3) seen :0
Running SMT prover for 3 properties.
[2023-03-17 10:49:03] [INFO ] Invariant cache hit.
[2023-03-17 10:49:03] [INFO ] After 262ms SMT Verify possible using all constraints in real domain returned unsat :3 sat :0
Fused 3 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 3 atomic propositions for a total of 16 simplifications.
[2023-03-17 10:49:03] [INFO ] Flatten gal took : 15 ms
[2023-03-17 10:49:03] [INFO ] Flatten gal took : 17 ms
[2023-03-17 10:49:04] [INFO ] Input system was already deterministic with 101 transitions.
Computed a total of 101 stabilizing places and 101 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 101 transition count 101
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 4 formulas.
FORMULA Referendum-PT-0100-CTLFireability-08 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Starting structural reductions in LTL mode, iteration 0 : 101/101 places, 101/101 transitions.
Discarding 99 places :
Symmetric choice reduction at 0 with 99 rule applications. Total rules 99 place count 2 transition count 2
Iterating global reduction 0 with 99 rules applied. Total rules applied 198 place count 2 transition count 2
Applied a total of 198 rules in 4 ms. Remains 2 /101 variables (removed 99) and now considering 2/101 (removed 99) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 2/101 places, 2/101 transitions.
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 1 ms
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 0 ms
[2023-03-17 10:49:04] [INFO ] Input system was already deterministic with 2 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 101/101 places, 101/101 transitions.
Applied a total of 0 rules in 4 ms. Remains 101 /101 variables (removed 0) and now considering 101/101 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 101/101 places, 101/101 transitions.
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 6 ms
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 7 ms
[2023-03-17 10:49:04] [INFO ] Input system was already deterministic with 101 transitions.
Starting structural reductions in LTL mode, iteration 0 : 101/101 places, 101/101 transitions.
Applied a total of 0 rules in 1 ms. Remains 101 /101 variables (removed 0) and now considering 101/101 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 101/101 places, 101/101 transitions.
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 7 ms
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 11 ms
[2023-03-17 10:49:04] [INFO ] Input system was already deterministic with 101 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 101/101 places, 101/101 transitions.
Applied a total of 0 rules in 2 ms. Remains 101 /101 variables (removed 0) and now considering 101/101 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 101/101 places, 101/101 transitions.
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 5 ms
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 6 ms
[2023-03-17 10:49:04] [INFO ] Input system was already deterministic with 101 transitions.
Starting structural reductions in LTL mode, iteration 0 : 101/101 places, 101/101 transitions.
Applied a total of 0 rules in 1 ms. Remains 101 /101 variables (removed 0) and now considering 101/101 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 101/101 places, 101/101 transitions.
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 14 ms
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 8 ms
[2023-03-17 10:49:04] [INFO ] Input system was already deterministic with 101 transitions.
Starting structural reductions in LTL mode, iteration 0 : 101/101 places, 101/101 transitions.
Applied a total of 0 rules in 1 ms. Remains 101 /101 variables (removed 0) and now considering 101/101 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 101/101 places, 101/101 transitions.
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 8 ms
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 6 ms
[2023-03-17 10:49:04] [INFO ] Input system was already deterministic with 101 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 101/101 places, 101/101 transitions.
Applied a total of 0 rules in 2 ms. Remains 101 /101 variables (removed 0) and now considering 101/101 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 101/101 places, 101/101 transitions.
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 4 ms
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 5 ms
[2023-03-17 10:49:04] [INFO ] Input system was already deterministic with 101 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 101/101 places, 101/101 transitions.
Applied a total of 0 rules in 2 ms. Remains 101 /101 variables (removed 0) and now considering 101/101 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 101/101 places, 101/101 transitions.
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 4 ms
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 5 ms
[2023-03-17 10:49:04] [INFO ] Input system was already deterministic with 101 transitions.
Starting structural reductions in LTL mode, iteration 0 : 101/101 places, 101/101 transitions.
Discarding 97 places :
Symmetric choice reduction at 0 with 97 rule applications. Total rules 97 place count 4 transition count 4
Iterating global reduction 0 with 97 rules applied. Total rules applied 194 place count 4 transition count 4
Applied a total of 194 rules in 2 ms. Remains 4 /101 variables (removed 97) and now considering 4/101 (removed 97) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 4/101 places, 4/101 transitions.
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 0 ms
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 0 ms
[2023-03-17 10:49:04] [INFO ] Input system was already deterministic with 4 transitions.
Starting structural reductions in LTL mode, iteration 0 : 101/101 places, 101/101 transitions.
Discarding 84 places :
Symmetric choice reduction at 0 with 84 rule applications. Total rules 84 place count 17 transition count 17
Iterating global reduction 0 with 84 rules applied. Total rules applied 168 place count 17 transition count 17
Applied a total of 168 rules in 2 ms. Remains 17 /101 variables (removed 84) and now considering 17/101 (removed 84) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 17/101 places, 17/101 transitions.
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 1 ms
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 1 ms
[2023-03-17 10:49:04] [INFO ] Input system was already deterministic with 17 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 101/101 places, 101/101 transitions.
Graph (complete) has 100 edges and 101 vertex of which 5 are kept as prefixes of interest. Removing 96 places using SCC suffix rule.1 ms
Discarding 96 places :
Also discarding 96 output transitions
Drop transitions removed 96 transitions
Applied a total of 1 rules in 2 ms. Remains 5 /101 variables (removed 96) and now considering 5/101 (removed 96) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 5/101 places, 5/101 transitions.
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 0 ms
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 1 ms
[2023-03-17 10:49:04] [INFO ] Input system was already deterministic with 5 transitions.
Starting structural reductions in LTL mode, iteration 0 : 101/101 places, 101/101 transitions.
Discarding 92 places :
Symmetric choice reduction at 0 with 92 rule applications. Total rules 92 place count 9 transition count 9
Iterating global reduction 0 with 92 rules applied. Total rules applied 184 place count 9 transition count 9
Applied a total of 184 rules in 1 ms. Remains 9 /101 variables (removed 92) and now considering 9/101 (removed 92) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/101 places, 9/101 transitions.
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 0 ms
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 1 ms
[2023-03-17 10:49:04] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in LTL mode, iteration 0 : 101/101 places, 101/101 transitions.
Discarding 98 places :
Symmetric choice reduction at 0 with 98 rule applications. Total rules 98 place count 3 transition count 3
Iterating global reduction 0 with 98 rules applied. Total rules applied 196 place count 3 transition count 3
Applied a total of 196 rules in 1 ms. Remains 3 /101 variables (removed 98) and now considering 3/101 (removed 98) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 3/101 places, 3/101 transitions.
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 0 ms
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 0 ms
[2023-03-17 10:49:04] [INFO ] Input system was already deterministic with 3 transitions.
Starting structural reductions in LTL mode, iteration 0 : 101/101 places, 101/101 transitions.
Discarding 95 places :
Symmetric choice reduction at 0 with 95 rule applications. Total rules 95 place count 6 transition count 6
Iterating global reduction 0 with 95 rules applied. Total rules applied 190 place count 6 transition count 6
Applied a total of 190 rules in 2 ms. Remains 6 /101 variables (removed 95) and now considering 6/101 (removed 95) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 6/101 places, 6/101 transitions.
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 0 ms
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 1 ms
[2023-03-17 10:49:04] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 101/101 places, 101/101 transitions.
Discarding 99 places :
Symmetric choice reduction at 0 with 99 rule applications. Total rules 99 place count 2 transition count 2
Iterating global reduction 0 with 99 rules applied. Total rules applied 198 place count 2 transition count 2
Applied a total of 198 rules in 1 ms. Remains 2 /101 variables (removed 99) and now considering 2/101 (removed 99) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 2/101 places, 2/101 transitions.
[2023-03-17 10:49:04] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 1 ms
FORMULA Referendum-PT-0100-CTLFireability-15 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 0 ms
[2023-03-17 10:49:04] [INFO ] Input system was already deterministic with 2 transitions.
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 17 ms
[2023-03-17 10:49:04] [INFO ] Flatten gal took : 14 ms
[2023-03-17 10:49:04] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 21 ms.
[2023-03-17 10:49:04] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 101 places, 101 transitions and 201 arcs took 0 ms.
Total runtime 3193 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT Referendum-PT-0100
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/372
CTLFireability
FORMULA Referendum-PT-0100-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Referendum-PT-0100-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Referendum-PT-0100-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Referendum-PT-0100-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Referendum-PT-0100-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Referendum-PT-0100-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Referendum-PT-0100-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Referendum-PT-0100-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Referendum-PT-0100-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679050537734
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/372/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/372/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/372/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Referendum-PT-0100-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Referendum-PT-0100-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Referendum-PT-0100-CTLFireability-04: CONJ 0 0 0 0 7 0 1 0
Referendum-PT-0100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Referendum-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 80/3303 29/32 Referendum-PT-0100-CTLFireability-01 4967564 m, 57685 m/sec, 79187321 t fired, .
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Referendum-PT-0100-CTLFireability-00: CTL false CTL model checker
Referendum-PT-0100-CTLFireability-02: CTL true CTL model checker
Referendum-PT-0100-CTLFireability-05: CTL true CTL model checker
Referendum-PT-0100-CTLFireability-09: CTL true CTL model checker
Referendum-PT-0100-CTLFireability-10: CTL false CTL model checker
Referendum-PT-0100-CTLFireability-11: CTL false CTL model checker
Referendum-PT-0100-CTLFireability-12: CTL false CTL model checker
Referendum-PT-0100-CTLFireability-13: CTL false CTL model checker
Referendum-PT-0100-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Referendum-PT-0100-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Referendum-PT-0100-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Referendum-PT-0100-CTLFireability-04: CONJ 0 0 0 0 7 0 1 0
Referendum-PT-0100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 85/3303 30/32 Referendum-PT-0100-CTLFireability-01 5238021 m, 54091 m/sec, 83787494 t fired, .
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Referendum-PT-0100-CTLFireability-00: CTL false CTL model checker
Referendum-PT-0100-CTLFireability-02: CTL true CTL model checker
Referendum-PT-0100-CTLFireability-05: CTL true CTL model checker
Referendum-PT-0100-CTLFireability-09: CTL true CTL model checker
Referendum-PT-0100-CTLFireability-10: CTL false CTL model checker
Referendum-PT-0100-CTLFireability-11: CTL false CTL model checker
Referendum-PT-0100-CTLFireability-12: CTL false CTL model checker
Referendum-PT-0100-CTLFireability-13: CTL false CTL model checker
Referendum-PT-0100-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Referendum-PT-0100-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Referendum-PT-0100-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Referendum-PT-0100-CTLFireability-04: CONJ 0 0 0 0 7 0 1 0
Referendum-PT-0100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Referendum-PT-0100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 90/3303 32/32 Referendum-PT-0100-CTLFireability-01 5530787 m, 58553 m/sec, 88470086 t fired, .
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Referendum-PT-0100-CTLFireability-00: CTL false CTL model checker
Referendum-PT-0100-CTLFireability-02: CTL true CTL model checker
Referendum-PT-0100-CTLFireability-05: CTL true CTL model checker
Referendum-PT-0100-CTLFireability-09: CTL true CTL model checker
Referendum-PT-0100-CTLFireability-10: CTL false CTL model checker
Referendum-PT-0100-CTLFireability-11: CTL false CTL model checker
Referendum-PT-0100-CTLFireability-12: CTL false CTL model checker
Referendum-PT-0100-CTLFireability-13: CTL false CTL model checker
Referendum-PT-0100-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Referendum-PT-0100-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Referendum-PT-0100-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Referendum-PT-0100-CTLFireability-04: CONJ 0 0 0 0 7 0 1 0
Referendum-PT-0100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Referendum-PT-0100-CTLFireability-00: CTL false CTL model checker
Referendum-PT-0100-CTLFireability-01: CTL unknown AGGR
Referendum-PT-0100-CTLFireability-02: CTL true CTL model checker
Referendum-PT-0100-CTLFireability-03: CTL unknown AGGR
Referendum-PT-0100-CTLFireability-04: CONJ unknown CONJ
Referendum-PT-0100-CTLFireability-05: CTL true CTL model checker
Referendum-PT-0100-CTLFireability-06: CTL unknown AGGR
Referendum-PT-0100-CTLFireability-07: CTL unknown AGGR
Referendum-PT-0100-CTLFireability-09: CTL true CTL model checker
Referendum-PT-0100-CTLFireability-10: CTL false CTL model checker
Referendum-PT-0100-CTLFireability-11: CTL false CTL model checker
Referendum-PT-0100-CTLFireability-12: CTL false CTL model checker
Referendum-PT-0100-CTLFireability-13: CTL false CTL model checker
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Referendum-PT-0100"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is Referendum-PT-0100, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r327-tall-167889199700498"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/Referendum-PT-0100.tgz
mv Referendum-PT-0100 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;