fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r327-tall-167889199600394
Last Updated
May 14, 2023

About the Execution of LoLa+red for Railroad-PT-100

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
12532.676 3600000.00 839843.00 12756.30 TTFT?F?TFFTTT?TT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r327-tall-167889199600394.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is Railroad-PT-100, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r327-tall-167889199600394
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 5.6M
-rw-r--r-- 1 mcc users 5.8K Feb 25 22:34 CTLCardinality.txt
-rw-r--r-- 1 mcc users 51K Feb 25 22:34 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.7K Feb 25 22:33 CTLFireability.txt
-rw-r--r-- 1 mcc users 34K Feb 25 22:33 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.0K Feb 25 16:42 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 16:42 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 16:42 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 16:42 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 22:38 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 110K Feb 25 22:38 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 22:36 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 79K Feb 25 22:36 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:42 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:42 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 5.2M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Railroad-PT-100-CTLFireability-00
FORMULA_NAME Railroad-PT-100-CTLFireability-01
FORMULA_NAME Railroad-PT-100-CTLFireability-02
FORMULA_NAME Railroad-PT-100-CTLFireability-03
FORMULA_NAME Railroad-PT-100-CTLFireability-04
FORMULA_NAME Railroad-PT-100-CTLFireability-05
FORMULA_NAME Railroad-PT-100-CTLFireability-06
FORMULA_NAME Railroad-PT-100-CTLFireability-07
FORMULA_NAME Railroad-PT-100-CTLFireability-08
FORMULA_NAME Railroad-PT-100-CTLFireability-09
FORMULA_NAME Railroad-PT-100-CTLFireability-10
FORMULA_NAME Railroad-PT-100-CTLFireability-11
FORMULA_NAME Railroad-PT-100-CTLFireability-12
FORMULA_NAME Railroad-PT-100-CTLFireability-13
FORMULA_NAME Railroad-PT-100-CTLFireability-14
FORMULA_NAME Railroad-PT-100-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679047826933

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Railroad-PT-100
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-17 10:10:28] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-17 10:10:28] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-17 10:10:28] [INFO ] Load time of PNML (sax parser for PT used): 332 ms
[2023-03-17 10:10:28] [INFO ] Transformed 1018 places.
[2023-03-17 10:10:28] [INFO ] Transformed 10506 transitions.
[2023-03-17 10:10:28] [INFO ] Found NUPN structural information;
[2023-03-17 10:10:28] [INFO ] Parsed PT model containing 1018 places and 10506 transitions and 62728 arcs in 508 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Deduced a syphon composed of 301 places in 106 ms
Reduce places removed 301 places and 100 transitions.
FORMULA Railroad-PT-100-CTLFireability-01 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 88 out of 717 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 717/717 places, 10406/10406 transitions.
Ensure Unique test removed 102 places
Iterating post reduction 0 with 102 rules applied. Total rules applied 102 place count 615 transition count 10406
Applied a total of 102 rules in 158 ms. Remains 615 /717 variables (removed 102) and now considering 10406/10406 (removed 0) transitions.
// Phase 1: matrix 10406 rows 615 cols
[2023-03-17 10:10:29] [INFO ] Invariants computation overflowed in 58 ms
[2023-03-17 10:10:30] [INFO ] Implicit Places using invariants in 845 ms returned []
Implicit Place search using SMT only with invariants took 871 ms to find 0 implicit places.
// Phase 1: matrix 10406 rows 615 cols
[2023-03-17 10:10:30] [INFO ] Invariants computation overflowed in 37 ms
[2023-03-17 10:10:33] [INFO ] Dead Transitions using invariants and state equation in 3037 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 615/717 places, 10406/10406 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4070 ms. Remains : 615/717 places, 10406/10406 transitions.
Support contains 88 out of 615 places after structural reductions.
[2023-03-17 10:10:34] [INFO ] Flatten gal took : 609 ms
[2023-03-17 10:10:34] [INFO ] Flatten gal took : 445 ms
[2023-03-17 10:10:35] [INFO ] Input system was already deterministic with 10406 transitions.
Support contains 87 out of 615 places (down from 88) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 795 ms. (steps per millisecond=12 ) properties (out of 45) seen :7
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 38) seen :0
Running SMT prover for 38 properties.
// Phase 1: matrix 10406 rows 615 cols
[2023-03-17 10:10:37] [INFO ] Invariants computation overflowed in 29 ms
[2023-03-17 10:10:46] [INFO ] After 9474ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0 real:37
[2023-03-17 10:11:03] [INFO ] After 15510ms SMT Verify possible using state equation in natural domain returned unsat :4 sat :34
[2023-03-17 10:11:04] [INFO ] Deduced a trap composed of 101 places in 168 ms of which 23 ms to minimize.
[2023-03-17 10:11:04] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 596 ms
[2023-03-17 10:11:11] [INFO ] After 24323ms SMT Verify possible using trap constraints in natural domain returned unsat :4 sat :34
Attempting to minimize the solution found.
Minimization took 3 ms.
[2023-03-17 10:11:11] [INFO ] After 25064ms SMT Verify possible using all constraints in natural domain returned unsat :4 sat :34
Fused 38 Parikh solutions to 34 different solutions.
Parikh walk visited 32 properties in 12691 ms.
Support contains 4 out of 615 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 615/615 places, 10406/10406 transitions.
Performed 98 Post agglomeration using F-continuation condition.Transition count delta: 98
Deduced a syphon composed of 98 places in 27 ms
Reduce places removed 98 places and 0 transitions.
Iterating global reduction 0 with 196 rules applied. Total rules applied 196 place count 517 transition count 10308
Applied a total of 196 rules in 5837 ms. Remains 517 /615 variables (removed 98) and now considering 10308/10406 (removed 98) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 5840 ms. Remains : 517/615 places, 10308/10406 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 334 ms. (steps per millisecond=29 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 47 ms. (steps per millisecond=212 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 40 ms. (steps per millisecond=250 ) properties (out of 2) seen :0
Interrupted probabilistic random walk after 184427 steps, run timeout after 3001 ms. (steps per millisecond=61 ) properties seen :{}
Probabilistic random walk after 184427 steps, saw 178468 distinct states, run finished after 3003 ms. (steps per millisecond=61 ) properties seen :0
Running SMT prover for 2 properties.
// Phase 1: matrix 10308 rows 517 cols
[2023-03-17 10:11:34] [INFO ] Invariants computation overflowed in 20 ms
[2023-03-17 10:11:36] [INFO ] After 2455ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-17 10:11:39] [INFO ] After 2703ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-17 10:11:39] [INFO ] After 3398ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 369 ms.
[2023-03-17 10:11:40] [INFO ] After 3864ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
Parikh walk visited 0 properties in 70 ms.
Support contains 4 out of 517 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 517/517 places, 10308/10308 transitions.
Applied a total of 0 rules in 5567 ms. Remains 517 /517 variables (removed 0) and now considering 10308/10308 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 5568 ms. Remains : 517/517 places, 10308/10308 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 517/517 places, 10308/10308 transitions.
Applied a total of 0 rules in 5510 ms. Remains 517 /517 variables (removed 0) and now considering 10308/10308 (removed 0) transitions.
// Phase 1: matrix 10308 rows 517 cols
[2023-03-17 10:11:51] [INFO ] Invariants computation overflowed in 24 ms
[2023-03-17 10:11:52] [INFO ] Implicit Places using invariants in 857 ms returned []
Implicit Place search using SMT only with invariants took 859 ms to find 0 implicit places.
// Phase 1: matrix 10308 rows 517 cols
[2023-03-17 10:11:52] [INFO ] Invariants computation overflowed in 17 ms
[2023-03-17 10:11:55] [INFO ] Dead Transitions using invariants and state equation in 2811 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 9182 ms. Remains : 517/517 places, 10308/10308 transitions.
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 2 Pre rules applied. Total rules applied 0 place count 517 transition count 10306
Deduced a syphon composed of 2 places in 25 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 4 rules applied. Total rules applied 4 place count 515 transition count 10306
Performed 98 Post agglomeration using F-continuation condition.Transition count delta: 98
Deduced a syphon composed of 98 places in 28 ms
Reduce places removed 196 places and 0 transitions.
Iterating global reduction 0 with 294 rules applied. Total rules applied 298 place count 319 transition count 10208
Applied a total of 298 rules in 253 ms. Remains 319 /517 variables (removed 198) and now considering 10208/10308 (removed 100) transitions.
Running SMT prover for 2 properties.
// Phase 1: matrix 10208 rows 319 cols
[2023-03-17 10:11:55] [INFO ] Invariants computation overflowed in 15 ms
[2023-03-17 10:11:57] [INFO ] After 2179ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-17 10:11:59] [INFO ] After 1992ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-17 10:12:00] [INFO ] After 2691ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 349 ms.
[2023-03-17 10:12:00] [INFO ] After 3124ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
Successfully simplified 4 atomic propositions for a total of 15 simplifications.
[2023-03-17 10:12:01] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-17 10:12:01] [INFO ] Flatten gal took : 306 ms
FORMULA Railroad-PT-100-CTLFireability-00 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-17 10:12:01] [INFO ] Flatten gal took : 337 ms
[2023-03-17 10:12:02] [INFO ] Input system was already deterministic with 10406 transitions.
Support contains 70 out of 615 places (down from 71) after GAL structural reductions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 615/615 places, 10406/10406 transitions.
Applied a total of 0 rules in 73 ms. Remains 615 /615 variables (removed 0) and now considering 10406/10406 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 75 ms. Remains : 615/615 places, 10406/10406 transitions.
[2023-03-17 10:12:02] [INFO ] Flatten gal took : 297 ms
[2023-03-17 10:12:02] [INFO ] Flatten gal took : 328 ms
[2023-03-17 10:12:03] [INFO ] Input system was already deterministic with 10406 transitions.
Starting structural reductions in LTL mode, iteration 0 : 615/615 places, 10406/10406 transitions.
Applied a total of 0 rules in 52 ms. Remains 615 /615 variables (removed 0) and now considering 10406/10406 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 53 ms. Remains : 615/615 places, 10406/10406 transitions.
[2023-03-17 10:12:03] [INFO ] Flatten gal took : 301 ms
[2023-03-17 10:12:04] [INFO ] Flatten gal took : 328 ms
[2023-03-17 10:12:04] [INFO ] Input system was already deterministic with 10406 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 615/615 places, 10406/10406 transitions.
Performed 91 Post agglomeration using F-continuation condition.Transition count delta: 91
Deduced a syphon composed of 91 places in 25 ms
Reduce places removed 91 places and 0 transitions.
Iterating global reduction 0 with 182 rules applied. Total rules applied 182 place count 524 transition count 10315
Applied a total of 182 rules in 7016 ms. Remains 524 /615 variables (removed 91) and now considering 10315/10406 (removed 91) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 7018 ms. Remains : 524/615 places, 10315/10406 transitions.
[2023-03-17 10:12:12] [INFO ] Flatten gal took : 297 ms
[2023-03-17 10:12:12] [INFO ] Flatten gal took : 321 ms
[2023-03-17 10:12:13] [INFO ] Input system was already deterministic with 10315 transitions.
Starting structural reductions in LTL mode, iteration 0 : 615/615 places, 10406/10406 transitions.
Applied a total of 0 rules in 49 ms. Remains 615 /615 variables (removed 0) and now considering 10406/10406 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 50 ms. Remains : 615/615 places, 10406/10406 transitions.
[2023-03-17 10:12:13] [INFO ] Flatten gal took : 296 ms
[2023-03-17 10:12:13] [INFO ] Flatten gal took : 326 ms
[2023-03-17 10:12:14] [INFO ] Input system was already deterministic with 10406 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 615/615 places, 10406/10406 transitions.
Performed 96 Post agglomeration using F-continuation condition.Transition count delta: 96
Deduced a syphon composed of 96 places in 24 ms
Reduce places removed 96 places and 0 transitions.
Iterating global reduction 0 with 192 rules applied. Total rules applied 192 place count 519 transition count 10310
Applied a total of 192 rules in 6370 ms. Remains 519 /615 variables (removed 96) and now considering 10310/10406 (removed 96) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6372 ms. Remains : 519/615 places, 10310/10406 transitions.
[2023-03-17 10:12:21] [INFO ] Flatten gal took : 287 ms
[2023-03-17 10:12:21] [INFO ] Flatten gal took : 322 ms
[2023-03-17 10:12:22] [INFO ] Input system was already deterministic with 10310 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 615/615 places, 10406/10406 transitions.
Performed 98 Post agglomeration using F-continuation condition.Transition count delta: 98
Deduced a syphon composed of 98 places in 24 ms
Reduce places removed 98 places and 0 transitions.
Iterating global reduction 0 with 196 rules applied. Total rules applied 196 place count 517 transition count 10308
Applied a total of 196 rules in 6531 ms. Remains 517 /615 variables (removed 98) and now considering 10308/10406 (removed 98) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6531 ms. Remains : 517/615 places, 10308/10406 transitions.
[2023-03-17 10:12:28] [INFO ] Flatten gal took : 317 ms
[2023-03-17 10:12:29] [INFO ] Flatten gal took : 360 ms
[2023-03-17 10:12:30] [INFO ] Input system was already deterministic with 10308 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 295 ms. (steps per millisecond=33 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 41 ms. (steps per millisecond=243 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 276002 steps, run timeout after 3001 ms. (steps per millisecond=91 ) properties seen :{}
Probabilistic random walk after 276002 steps, saw 266389 distinct states, run finished after 3002 ms. (steps per millisecond=91 ) properties seen :0
Running SMT prover for 1 properties.
// Phase 1: matrix 10308 rows 517 cols
[2023-03-17 10:12:33] [INFO ] Invariants computation overflowed in 19 ms
[2023-03-17 10:12:36] [INFO ] After 2550ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-17 10:12:38] [INFO ] After 2405ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-17 10:12:39] [INFO ] After 2866ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 220 ms.
[2023-03-17 10:12:39] [INFO ] After 3212ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Finished Parikh walk after 166 steps, including 2 resets, run visited all 1 properties in 8 ms. (steps per millisecond=20 )
FORMULA Railroad-PT-100-CTLFireability-07 TRUE TECHNIQUES TOPOLOGICAL PARIKH_WALK
Parikh walk visited 1 properties in 8 ms.
Starting structural reductions in LTL mode, iteration 0 : 615/615 places, 10406/10406 transitions.
Applied a total of 0 rules in 50 ms. Remains 615 /615 variables (removed 0) and now considering 10406/10406 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 51 ms. Remains : 615/615 places, 10406/10406 transitions.
[2023-03-17 10:12:39] [INFO ] Flatten gal took : 301 ms
[2023-03-17 10:12:39] [INFO ] Flatten gal took : 332 ms
[2023-03-17 10:12:40] [INFO ] Input system was already deterministic with 10406 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 615/615 places, 10406/10406 transitions.
Performed 99 Post agglomeration using F-continuation condition.Transition count delta: 99
Deduced a syphon composed of 99 places in 24 ms
Reduce places removed 99 places and 0 transitions.
Iterating global reduction 0 with 198 rules applied. Total rules applied 198 place count 516 transition count 10307
Applied a total of 198 rules in 6001 ms. Remains 516 /615 variables (removed 99) and now considering 10307/10406 (removed 99) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6002 ms. Remains : 516/615 places, 10307/10406 transitions.
[2023-03-17 10:12:46] [INFO ] Flatten gal took : 302 ms
[2023-03-17 10:12:47] [INFO ] Flatten gal took : 329 ms
[2023-03-17 10:12:47] [INFO ] Input system was already deterministic with 10307 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 329 ms. (steps per millisecond=30 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 56 ms. (steps per millisecond=178 ) properties (out of 1) seen :0
Finished probabilistic random walk after 26331 steps, run visited all 1 properties in 257 ms. (steps per millisecond=102 )
Probabilistic random walk after 26331 steps, saw 25637 distinct states, run finished after 258 ms. (steps per millisecond=102 ) properties seen :1
FORMULA Railroad-PT-100-CTLFireability-09 FALSE TECHNIQUES TOPOLOGICAL PROBABILISTIC_WALK
Starting structural reductions in LTL mode, iteration 0 : 615/615 places, 10406/10406 transitions.
Applied a total of 0 rules in 51 ms. Remains 615 /615 variables (removed 0) and now considering 10406/10406 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 51 ms. Remains : 615/615 places, 10406/10406 transitions.
[2023-03-17 10:12:48] [INFO ] Flatten gal took : 318 ms
[2023-03-17 10:12:49] [INFO ] Flatten gal took : 364 ms
[2023-03-17 10:12:49] [INFO ] Input system was already deterministic with 10406 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 615/615 places, 10406/10406 transitions.
Performed 99 Post agglomeration using F-continuation condition.Transition count delta: 99
Deduced a syphon composed of 99 places in 25 ms
Reduce places removed 99 places and 0 transitions.
Iterating global reduction 0 with 198 rules applied. Total rules applied 198 place count 516 transition count 10307
Applied a total of 198 rules in 5982 ms. Remains 516 /615 variables (removed 99) and now considering 10307/10406 (removed 99) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5982 ms. Remains : 516/615 places, 10307/10406 transitions.
[2023-03-17 10:12:56] [INFO ] Flatten gal took : 292 ms
[2023-03-17 10:12:56] [INFO ] Flatten gal took : 318 ms
[2023-03-17 10:12:57] [INFO ] Input system was already deterministic with 10307 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 615/615 places, 10406/10406 transitions.
Performed 99 Post agglomeration using F-continuation condition.Transition count delta: 99
Deduced a syphon composed of 99 places in 25 ms
Reduce places removed 99 places and 0 transitions.
Iterating global reduction 0 with 198 rules applied. Total rules applied 198 place count 516 transition count 10307
Applied a total of 198 rules in 5989 ms. Remains 516 /615 variables (removed 99) and now considering 10307/10406 (removed 99) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5989 ms. Remains : 516/615 places, 10307/10406 transitions.
[2023-03-17 10:13:03] [INFO ] Flatten gal took : 289 ms
[2023-03-17 10:13:03] [INFO ] Flatten gal took : 321 ms
[2023-03-17 10:13:04] [INFO ] Input system was already deterministic with 10307 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 265 ms. (steps per millisecond=37 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 38 ms. (steps per millisecond=263 ) properties (out of 1) seen :0
Finished probabilistic random walk after 22846 steps, run visited all 1 properties in 208 ms. (steps per millisecond=109 )
Probabilistic random walk after 22846 steps, saw 22221 distinct states, run finished after 209 ms. (steps per millisecond=109 ) properties seen :1
FORMULA Railroad-PT-100-CTLFireability-12 TRUE TECHNIQUES TOPOLOGICAL PROBABILISTIC_WALK
Starting structural reductions in LTL mode, iteration 0 : 615/615 places, 10406/10406 transitions.
Applied a total of 0 rules in 47 ms. Remains 615 /615 variables (removed 0) and now considering 10406/10406 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 47 ms. Remains : 615/615 places, 10406/10406 transitions.
[2023-03-17 10:13:05] [INFO ] Flatten gal took : 331 ms
[2023-03-17 10:13:05] [INFO ] Flatten gal took : 307 ms
[2023-03-17 10:13:06] [INFO ] Input system was already deterministic with 10406 transitions.
Starting structural reductions in LTL mode, iteration 0 : 615/615 places, 10406/10406 transitions.
Applied a total of 0 rules in 48 ms. Remains 615 /615 variables (removed 0) and now considering 10406/10406 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 48 ms. Remains : 615/615 places, 10406/10406 transitions.
[2023-03-17 10:13:06] [INFO ] Flatten gal took : 290 ms
[2023-03-17 10:13:07] [INFO ] Flatten gal took : 376 ms
[2023-03-17 10:13:07] [INFO ] Input system was already deterministic with 10406 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 615/615 places, 10406/10406 transitions.
Performed 99 Post agglomeration using F-continuation condition.Transition count delta: 99
Deduced a syphon composed of 99 places in 25 ms
Reduce places removed 99 places and 0 transitions.
Iterating global reduction 0 with 198 rules applied. Total rules applied 198 place count 516 transition count 10307
Applied a total of 198 rules in 5957 ms. Remains 516 /615 variables (removed 99) and now considering 10307/10406 (removed 99) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5958 ms. Remains : 516/615 places, 10307/10406 transitions.
[2023-03-17 10:13:13] [INFO ] Flatten gal took : 288 ms
[2023-03-17 10:13:14] [INFO ] Flatten gal took : 322 ms
[2023-03-17 10:13:14] [INFO ] Input system was already deterministic with 10307 transitions.
[2023-03-17 10:13:15] [INFO ] Flatten gal took : 322 ms
[2023-03-17 10:13:15] [INFO ] Flatten gal took : 323 ms
[2023-03-17 10:13:15] [INFO ] Export to MCC of 11 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-17 10:13:15] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 615 places, 10406 transitions and 61923 arcs took 58 ms.
Total runtime 167212 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT Railroad-PT-100
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA Railroad-PT-100-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-100-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-100-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-100-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-100-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-100-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-100-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-100-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 3605720 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16087108 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 38 (type SKEL/SRCH) for 13 Railroad-PT-100-CTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 38 (type SKEL/SRCH) for Railroad-PT-100-CTLFireability-05
lola: result : true
lola: markings : 197
lola: fired transitions : 196
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: LAUNCH INITIAL
lola: LAUNCH task # 20 (type CNST) for 19 Railroad-PT-100-CTLFireability-08
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 20 (type CNST) for Railroad-PT-100-CTLFireability-08
lola: result : false
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
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Railroad-PT-100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
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Railroad-PT-100-CTLFireability-15: EG 0 1 0 0 1 0 0 0

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Railroad-PT-100-CTLFireability-05: AXAG false state space /EXEF
Railroad-PT-100-CTLFireability-08: INITIAL false preprocessing
Railroad-PT-100-CTLFireability-10: CTL true CTL model checker
Railroad-PT-100-CTLFireability-11: CTL true CTL model checker
Railroad-PT-100-CTLFireability-14: CTL true CTL model checker
Railroad-PT-100-CTLFireability-15: EG true state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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Railroad-PT-100-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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Railroad-PT-100-CTLFireability-02: CTL false CTL model checker
Railroad-PT-100-CTLFireability-03: DISJ true CTL model checker
Railroad-PT-100-CTLFireability-05: AXAG false state space /EXEF
Railroad-PT-100-CTLFireability-08: INITIAL false preprocessing
Railroad-PT-100-CTLFireability-10: CTL true CTL model checker
Railroad-PT-100-CTLFireability-11: CTL true CTL model checker
Railroad-PT-100-CTLFireability-14: CTL true CTL model checker
Railroad-PT-100-CTLFireability-15: EG true state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Railroad-PT-100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
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FINAL RESULTS
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Railroad-PT-100-CTLFireability-02: CTL false CTL model checker
Railroad-PT-100-CTLFireability-03: DISJ true CTL model checker
Railroad-PT-100-CTLFireability-04: CTL unknown AGGR
Railroad-PT-100-CTLFireability-05: AXAG false state space /EXEF
Railroad-PT-100-CTLFireability-06: CTL unknown AGGR
Railroad-PT-100-CTLFireability-08: INITIAL false preprocessing
Railroad-PT-100-CTLFireability-10: CTL true CTL model checker
Railroad-PT-100-CTLFireability-11: CTL true CTL model checker
Railroad-PT-100-CTLFireability-13: CTL unknown AGGR
Railroad-PT-100-CTLFireability-14: CTL true CTL model checker
Railroad-PT-100-CTLFireability-15: EG true state space / EG


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Railroad-PT-100"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is Railroad-PT-100, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r327-tall-167889199600394"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/Railroad-PT-100.tgz
mv Railroad-PT-100 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;