About the Execution of LoLa+red for Railroad-PT-010
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 682.376 | 91168.00 | 97866.00 | 680.10 | FTTFFFFFTFTTFFTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r327-tall-167889199500370.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is Railroad-PT-010, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r327-tall-167889199500370
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 604K
-rw-r--r-- 1 mcc users 9.0K Feb 25 22:26 CTLCardinality.txt
-rw-r--r-- 1 mcc users 98K Feb 25 22:26 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.9K Feb 25 22:25 CTLFireability.txt
-rw-r--r-- 1 mcc users 47K Feb 25 22:25 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.2K Feb 25 16:41 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:41 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 16:41 LTLFireability.txt
-rw-r--r-- 1 mcc users 14K Feb 25 16:41 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Feb 25 22:27 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 148K Feb 25 22:27 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 22:27 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 81K Feb 25 22:27 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:41 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:41 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 82K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME Railroad-PT-010-CTLFireability-00
FORMULA_NAME Railroad-PT-010-CTLFireability-01
FORMULA_NAME Railroad-PT-010-CTLFireability-02
FORMULA_NAME Railroad-PT-010-CTLFireability-03
FORMULA_NAME Railroad-PT-010-CTLFireability-04
FORMULA_NAME Railroad-PT-010-CTLFireability-05
FORMULA_NAME Railroad-PT-010-CTLFireability-06
FORMULA_NAME Railroad-PT-010-CTLFireability-07
FORMULA_NAME Railroad-PT-010-CTLFireability-08
FORMULA_NAME Railroad-PT-010-CTLFireability-09
FORMULA_NAME Railroad-PT-010-CTLFireability-10
FORMULA_NAME Railroad-PT-010-CTLFireability-11
FORMULA_NAME Railroad-PT-010-CTLFireability-12
FORMULA_NAME Railroad-PT-010-CTLFireability-13
FORMULA_NAME Railroad-PT-010-CTLFireability-14
FORMULA_NAME Railroad-PT-010-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679044689230
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Railroad-PT-010
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-17 09:18:10] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-17 09:18:10] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-17 09:18:10] [INFO ] Load time of PNML (sax parser for PT used): 43 ms
[2023-03-17 09:18:10] [INFO ] Transformed 118 places.
[2023-03-17 09:18:10] [INFO ] Transformed 156 transitions.
[2023-03-17 09:18:10] [INFO ] Found NUPN structural information;
[2023-03-17 09:18:10] [INFO ] Parsed PT model containing 118 places and 156 transitions and 898 arcs in 103 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Initial state reduction rules removed 2 formulas.
Deduced a syphon composed of 31 places in 1 ms
Reduce places removed 31 places and 10 transitions.
FORMULA Railroad-PT-010-CTLFireability-12 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA Railroad-PT-010-CTLFireability-13 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA Railroad-PT-010-CTLFireability-15 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 52 out of 87 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 87/87 places, 146/146 transitions.
Ensure Unique test removed 6 places
Iterating post reduction 0 with 6 rules applied. Total rules applied 6 place count 81 transition count 146
Applied a total of 6 rules in 206 ms. Remains 81 /87 variables (removed 6) and now considering 146/146 (removed 0) transitions.
// Phase 1: matrix 146 rows 81 cols
[2023-03-17 09:18:11] [INFO ] Computed 35 place invariants in 21 ms
[2023-03-17 09:18:11] [INFO ] Implicit Places using invariants in 204 ms returned [41, 46, 47, 48, 58, 69, 72, 77]
Discarding 8 places :
Implicit Place search using SMT only with invariants took 228 ms to find 8 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 73/87 places, 146/146 transitions.
Applied a total of 0 rules in 2 ms. Remains 73 /73 variables (removed 0) and now considering 146/146 (removed 0) transitions.
Finished structural reductions in LTL mode , in 2 iterations and 437 ms. Remains : 73/87 places, 146/146 transitions.
Support contains 52 out of 73 places after structural reductions.
[2023-03-17 09:18:11] [INFO ] Flatten gal took : 36 ms
[2023-03-17 09:18:11] [INFO ] Flatten gal took : 16 ms
[2023-03-17 09:18:11] [INFO ] Input system was already deterministic with 146 transitions.
Support contains 51 out of 73 places (down from 52) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 408 ms. (steps per millisecond=24 ) properties (out of 51) seen :45
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 38 ms. (steps per millisecond=263 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=370 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=400 ) properties (out of 6) seen :0
Running SMT prover for 6 properties.
// Phase 1: matrix 146 rows 73 cols
[2023-03-17 09:18:12] [INFO ] Computed 27 place invariants in 7 ms
[2023-03-17 09:18:12] [INFO ] [Real]Absence check using 18 positive place invariants in 3 ms returned sat
[2023-03-17 09:18:12] [INFO ] [Real]Absence check using 18 positive and 9 generalized place invariants in 2 ms returned sat
[2023-03-17 09:18:12] [INFO ] After 75ms SMT Verify possible using all constraints in real domain returned unsat :6 sat :0
Fused 6 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 6 atomic propositions for a total of 13 simplifications.
[2023-03-17 09:18:12] [INFO ] Flatten gal took : 11 ms
[2023-03-17 09:18:12] [INFO ] Flatten gal took : 13 ms
[2023-03-17 09:18:12] [INFO ] Input system was already deterministic with 146 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 73/73 places, 146/146 transitions.
Ensure Unique test removed 6 places
Performed 4 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 4 Pre rules applied. Total rules applied 0 place count 67 transition count 142
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 0 with 8 rules applied. Total rules applied 8 place count 63 transition count 142
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 10 place count 62 transition count 141
Applied a total of 10 rules in 25 ms. Remains 62 /73 variables (removed 11) and now considering 141/146 (removed 5) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 25 ms. Remains : 62/73 places, 141/146 transitions.
[2023-03-17 09:18:12] [INFO ] Flatten gal took : 9 ms
[2023-03-17 09:18:12] [INFO ] Flatten gal took : 9 ms
[2023-03-17 09:18:12] [INFO ] Input system was already deterministic with 141 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 73/73 places, 146/146 transitions.
Ensure Unique test removed 6 places
Performed 4 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 4 Pre rules applied. Total rules applied 0 place count 67 transition count 142
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 0 with 8 rules applied. Total rules applied 8 place count 63 transition count 142
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 4 rules applied. Total rules applied 12 place count 61 transition count 140
Applied a total of 12 rules in 16 ms. Remains 61 /73 variables (removed 12) and now considering 140/146 (removed 6) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 16 ms. Remains : 61/73 places, 140/146 transitions.
[2023-03-17 09:18:12] [INFO ] Flatten gal took : 8 ms
[2023-03-17 09:18:12] [INFO ] Flatten gal took : 10 ms
[2023-03-17 09:18:12] [INFO ] Input system was already deterministic with 140 transitions.
Starting structural reductions in LTL mode, iteration 0 : 73/73 places, 146/146 transitions.
Ensure Unique test removed 5 places
Iterating post reduction 0 with 5 rules applied. Total rules applied 5 place count 68 transition count 146
Applied a total of 5 rules in 2 ms. Remains 68 /73 variables (removed 5) and now considering 146/146 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 68/73 places, 146/146 transitions.
[2023-03-17 09:18:12] [INFO ] Flatten gal took : 10 ms
[2023-03-17 09:18:12] [INFO ] Flatten gal took : 10 ms
[2023-03-17 09:18:12] [INFO ] Input system was already deterministic with 146 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 73/73 places, 146/146 transitions.
Ensure Unique test removed 6 places
Performed 5 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 5 Pre rules applied. Total rules applied 0 place count 67 transition count 141
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 0 with 10 rules applied. Total rules applied 10 place count 62 transition count 141
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 12 place count 61 transition count 140
Applied a total of 12 rules in 15 ms. Remains 61 /73 variables (removed 12) and now considering 140/146 (removed 6) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 15 ms. Remains : 61/73 places, 140/146 transitions.
[2023-03-17 09:18:12] [INFO ] Flatten gal took : 7 ms
[2023-03-17 09:18:12] [INFO ] Flatten gal took : 8 ms
[2023-03-17 09:18:12] [INFO ] Input system was already deterministic with 140 transitions.
Starting structural reductions in LTL mode, iteration 0 : 73/73 places, 146/146 transitions.
Ensure Unique test removed 4 places
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 69 transition count 146
Applied a total of 4 rules in 2 ms. Remains 69 /73 variables (removed 4) and now considering 146/146 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 69/73 places, 146/146 transitions.
[2023-03-17 09:18:12] [INFO ] Flatten gal took : 8 ms
[2023-03-17 09:18:12] [INFO ] Flatten gal took : 9 ms
[2023-03-17 09:18:12] [INFO ] Input system was already deterministic with 146 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 73/73 places, 146/146 transitions.
Ensure Unique test removed 6 places
Performed 5 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 5 Pre rules applied. Total rules applied 0 place count 67 transition count 141
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 0 with 10 rules applied. Total rules applied 10 place count 62 transition count 141
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Deduced a syphon composed of 3 places in 1 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 0 with 6 rules applied. Total rules applied 16 place count 59 transition count 138
Applied a total of 16 rules in 12 ms. Remains 59 /73 variables (removed 14) and now considering 138/146 (removed 8) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 12 ms. Remains : 59/73 places, 138/146 transitions.
[2023-03-17 09:18:12] [INFO ] Flatten gal took : 7 ms
[2023-03-17 09:18:12] [INFO ] Flatten gal took : 13 ms
[2023-03-17 09:18:12] [INFO ] Input system was already deterministic with 138 transitions.
Starting structural reductions in LTL mode, iteration 0 : 73/73 places, 146/146 transitions.
Ensure Unique test removed 5 places
Iterating post reduction 0 with 5 rules applied. Total rules applied 5 place count 68 transition count 146
Applied a total of 5 rules in 2 ms. Remains 68 /73 variables (removed 5) and now considering 146/146 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 68/73 places, 146/146 transitions.
[2023-03-17 09:18:12] [INFO ] Flatten gal took : 7 ms
[2023-03-17 09:18:12] [INFO ] Flatten gal took : 8 ms
[2023-03-17 09:18:12] [INFO ] Input system was already deterministic with 146 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 73/73 places, 146/146 transitions.
Ensure Unique test removed 5 places
Performed 5 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 5 Pre rules applied. Total rules applied 0 place count 68 transition count 141
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 0 with 10 rules applied. Total rules applied 10 place count 63 transition count 141
Performed 6 Post agglomeration using F-continuation condition.Transition count delta: 6
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 0 with 12 rules applied. Total rules applied 22 place count 57 transition count 135
Applied a total of 22 rules in 9 ms. Remains 57 /73 variables (removed 16) and now considering 135/146 (removed 11) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 9 ms. Remains : 57/73 places, 135/146 transitions.
[2023-03-17 09:18:12] [INFO ] Flatten gal took : 5 ms
[2023-03-17 09:18:12] [INFO ] Flatten gal took : 6 ms
[2023-03-17 09:18:12] [INFO ] Input system was already deterministic with 135 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 73/73 places, 146/146 transitions.
Ensure Unique test removed 6 places
Performed 5 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 5 Pre rules applied. Total rules applied 0 place count 67 transition count 141
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 0 with 10 rules applied. Total rules applied 10 place count 62 transition count 141
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 0 with 8 rules applied. Total rules applied 18 place count 58 transition count 137
Applied a total of 18 rules in 10 ms. Remains 58 /73 variables (removed 15) and now considering 137/146 (removed 9) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 10 ms. Remains : 58/73 places, 137/146 transitions.
[2023-03-17 09:18:12] [INFO ] Flatten gal took : 6 ms
[2023-03-17 09:18:12] [INFO ] Flatten gal took : 6 ms
[2023-03-17 09:18:12] [INFO ] Input system was already deterministic with 137 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 73/73 places, 146/146 transitions.
Ensure Unique test removed 5 places
Performed 6 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 6 Pre rules applied. Total rules applied 0 place count 68 transition count 140
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 0 with 12 rules applied. Total rules applied 12 place count 62 transition count 140
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 14 place count 61 transition count 139
Applied a total of 14 rules in 9 ms. Remains 61 /73 variables (removed 12) and now considering 139/146 (removed 7) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 9 ms. Remains : 61/73 places, 139/146 transitions.
[2023-03-17 09:18:12] [INFO ] Flatten gal took : 5 ms
[2023-03-17 09:18:12] [INFO ] Flatten gal took : 7 ms
[2023-03-17 09:18:12] [INFO ] Input system was already deterministic with 139 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 73/73 places, 146/146 transitions.
Ensure Unique test removed 6 places
Performed 3 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 3 Pre rules applied. Total rules applied 0 place count 67 transition count 143
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 0 with 6 rules applied. Total rules applied 6 place count 64 transition count 143
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 4 rules applied. Total rules applied 10 place count 62 transition count 141
Applied a total of 10 rules in 8 ms. Remains 62 /73 variables (removed 11) and now considering 141/146 (removed 5) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 9 ms. Remains : 62/73 places, 141/146 transitions.
[2023-03-17 09:18:12] [INFO ] Flatten gal took : 6 ms
[2023-03-17 09:18:12] [INFO ] Flatten gal took : 7 ms
[2023-03-17 09:18:12] [INFO ] Input system was already deterministic with 141 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 73/73 places, 146/146 transitions.
Ensure Unique test removed 6 places
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 2 Pre rules applied. Total rules applied 0 place count 67 transition count 144
Deduced a syphon composed of 2 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 4 rules applied. Total rules applied 4 place count 65 transition count 144
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 0 with 8 rules applied. Total rules applied 12 place count 61 transition count 140
Applied a total of 12 rules in 9 ms. Remains 61 /73 variables (removed 12) and now considering 140/146 (removed 6) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 9 ms. Remains : 61/73 places, 140/146 transitions.
[2023-03-17 09:18:12] [INFO ] Flatten gal took : 6 ms
[2023-03-17 09:18:12] [INFO ] Flatten gal took : 6 ms
[2023-03-17 09:18:12] [INFO ] Input system was already deterministic with 140 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 73/73 places, 146/146 transitions.
Ensure Unique test removed 5 places
Performed 3 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 3 Pre rules applied. Total rules applied 0 place count 68 transition count 143
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 0 with 6 rules applied. Total rules applied 6 place count 65 transition count 143
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 0 with 6 rules applied. Total rules applied 12 place count 62 transition count 140
Applied a total of 12 rules in 8 ms. Remains 62 /73 variables (removed 11) and now considering 140/146 (removed 6) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 8 ms. Remains : 62/73 places, 140/146 transitions.
[2023-03-17 09:18:12] [INFO ] Flatten gal took : 8 ms
[2023-03-17 09:18:12] [INFO ] Flatten gal took : 6 ms
[2023-03-17 09:18:12] [INFO ] Input system was already deterministic with 140 transitions.
[2023-03-17 09:18:12] [INFO ] Flatten gal took : 8 ms
[2023-03-17 09:18:12] [INFO ] Flatten gal took : 7 ms
[2023-03-17 09:18:12] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 17 ms.
[2023-03-17 09:18:12] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 73 places, 146 transitions and 800 arcs took 1 ms.
Total runtime 2385 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT Railroad-PT-010
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/362
CTLFireability
FORMULA Railroad-PT-010-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679044780398
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/362/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/362/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/362/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:284
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
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lola: Created skeleton in 0.000000 secs.
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lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 7 (type EXCL) for 6 Railroad-PT-010-CTLFireability-02
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 44 (type FNDP) for 33 Railroad-PT-010-CTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 45 (type EQUN) for 33 Railroad-PT-010-CTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 47 (type SRCH) for 33 Railroad-PT-010-CTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 47 (type SRCH) for Railroad-PT-010-CTLFireability-11
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 44 (type FNDP) for Railroad-PT-010-CTLFireability-11
lola: result : true
lola: fired transitions : 11
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 45 (type EQUN) for Railroad-PT-010-CTLFireability-11 (obsolete)
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 45 (type EQUN) for Railroad-PT-010-CTLFireability-11
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:666
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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Railroad-PT-010-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
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Railroad-PT-010-CTLFireability-08: SP ECTL 0 1 0 0 1 0 0 0
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Railroad-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-11: CONJ 0 1 0 0 5 0 0 1
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/276 4/32 Railroad-PT-010-CTLFireability-02 962187 m, 192437 m/sec, 3661620 t fired, .
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Railroad-PT-010-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
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7 CTL EXCL 10/276 6/32 Railroad-PT-010-CTLFireability-02 1453747 m, 98312 m/sec, 8013822 t fired, .
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7 CTL EXCL 15/276 8/32 Railroad-PT-010-CTLFireability-02 1820365 m, 73323 m/sec, 12102507 t fired, .
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7 CTL EXCL 20/276 9/32 Railroad-PT-010-CTLFireability-02 2037886 m, 43504 m/sec, 15959623 t fired, .
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Railroad-PT-010-CTLFireability-08: SP ECTL 0 1 0 0 1 0 0 0
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7 CTL EXCL 25/276 9/32 Railroad-PT-010-CTLFireability-02 2038166 m, 56 m/sec, 19469707 t fired, .
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lola: FINISHED task # 7 (type EXCL) for Railroad-PT-010-CTLFireability-02
lola: result : true
lola: markings : 2038166
lola: fired transitions : 21875336
lola: time used : 28.000000
lola: memory pages used : 9
lola: LAUNCH task # 19 (type EXCL) for 18 Railroad-PT-010-CTLFireability-06
lola: time limit : 297 sec
lola: memory limit: 32 pages
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Railroad-PT-010-CTLFireability-05: EFEG 0 1 0 0 1 0 0 0
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19 CTL EXCL 2/297 2/32 Railroad-PT-010-CTLFireability-06 412216 m, 82443 m/sec, 1313830 t fired, .
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19 CTL EXCL 12/297 7/32 Railroad-PT-010-CTLFireability-06 1668366 m, 95632 m/sec, 9184847 t fired, .
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Railroad-PT-010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Railroad-PT-010"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is Railroad-PT-010, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r327-tall-167889199500370"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/Railroad-PT-010.tgz
mv Railroad-PT-010 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;