Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r327-tall-167889199400250.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is RERS2020-PT-pb105, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r327-tall-167889199400250
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 87M
-rw-r--r-- 1 mcc users 7.7K Feb 26 08:50 CTLCardinality.txt
-rw-r--r-- 1 mcc users 82K Feb 26 08:50 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.9K Feb 26 08:43 CTLFireability.txt
-rw-r--r-- 1 mcc users 47K Feb 26 08:43 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:40 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:40 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K Feb 25 16:40 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:40 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.1K Feb 26 09:00 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 89K Feb 26 09:00 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.3K Feb 26 08:57 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 59K Feb 26 08:57 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:40 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:40 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 86M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RERS2020-PT-pb105-CTLFireability-00
FORMULA_NAME RERS2020-PT-pb105-CTLFireability-01
FORMULA_NAME RERS2020-PT-pb105-CTLFireability-02
FORMULA_NAME RERS2020-PT-pb105-CTLFireability-03
FORMULA_NAME RERS2020-PT-pb105-CTLFireability-04
FORMULA_NAME RERS2020-PT-pb105-CTLFireability-05
FORMULA_NAME RERS2020-PT-pb105-CTLFireability-06
FORMULA_NAME RERS2020-PT-pb105-CTLFireability-07
FORMULA_NAME RERS2020-PT-pb105-CTLFireability-08
FORMULA_NAME RERS2020-PT-pb105-CTLFireability-09
FORMULA_NAME RERS2020-PT-pb105-CTLFireability-10
FORMULA_NAME RERS2020-PT-pb105-CTLFireability-11
FORMULA_NAME RERS2020-PT-pb105-CTLFireability-12
FORMULA_NAME RERS2020-PT-pb105-CTLFireability-13
FORMULA_NAME RERS2020-PT-pb105-CTLFireability-14
FORMULA_NAME RERS2020-PT-pb105-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679023845455

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RERS2020-PT-pb105
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-17 03:30:47] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-17 03:30:47] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-17 03:30:49] [INFO ] Load time of PNML (sax parser for PT used): 2416 ms
[2023-03-17 03:30:49] [INFO ] Transformed 1982 places.
[2023-03-17 03:30:50] [INFO ] Transformed 153412 transitions.
[2023-03-17 03:30:50] [INFO ] Found NUPN structural information;
[2023-03-17 03:30:50] [INFO ] Parsed PT model containing 1982 places and 153412 transitions and 610156 arcs in 2977 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 33 ms.
Ensure Unique test removed 3773 transitions
Reduce redundant transitions removed 3773 transitions.
Support contains 184 out of 1982 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 1982/1982 places, 149639/149639 transitions.
Ensure Unique test removed 10 places
Reduce places removed 11 places and 0 transitions.
Iterating post reduction 0 with 11 rules applied. Total rules applied 11 place count 1971 transition count 149639
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 14 place count 1968 transition count 149588
Iterating global reduction 1 with 3 rules applied. Total rules applied 17 place count 1968 transition count 149588
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 1 with 3 rules applied. Total rules applied 20 place count 1968 transition count 149585
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 21 place count 1967 transition count 149583
Iterating global reduction 2 with 1 rules applied. Total rules applied 22 place count 1967 transition count 149583
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 23 place count 1967 transition count 149582
Applied a total of 23 rules in 1668 ms. Remains 1967 /1982 variables (removed 15) and now considering 149582/149639 (removed 57) transitions.
[2023-03-17 03:30:52] [INFO ] Flow matrix only has 105319 transitions (discarded 44263 similar events)
// Phase 1: matrix 105319 rows 1967 cols
[2023-03-17 03:30:53] [INFO ] Computed 10 place invariants in 606 ms
[2023-03-17 03:31:01] [INFO ] Implicit Places using invariants in 8304 ms returned []
Implicit Place search using SMT only with invariants took 8331 ms to find 0 implicit places.
[2023-03-17 03:31:01] [INFO ] Flow matrix only has 105319 transitions (discarded 44263 similar events)
[2023-03-17 03:31:01] [INFO ] Invariant cache hit.
[2023-03-17 03:31:31] [INFO ] Performed 82600/149582 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-17 03:31:55] [INFO ] Dead Transitions using invariants and state equation in 53972 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 1967/1982 places, 149582/149639 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 63989 ms. Remains : 1967/1982 places, 149582/149639 transitions.
Support contains 184 out of 1967 places after structural reductions.
[2023-03-17 03:31:59] [INFO ] Flatten gal took : 3724 ms
[2023-03-17 03:32:03] [INFO ] Flatten gal took : 3388 ms
[2023-03-17 03:32:10] [INFO ] Input system was already deterministic with 149582 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1331 ms. (steps per millisecond=7 ) properties (out of 78) seen :4
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 74) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=30 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 159 ms. (steps per millisecond=6 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 73) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 73) seen :0
Interrupted probabilistic random walk after 9646 steps, run timeout after 6001 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 9646 steps, saw 7125 distinct states, run finished after 6004 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 73 properties.
[2023-03-17 03:32:20] [INFO ] Flow matrix only has 105319 transitions (discarded 44263 similar events)
[2023-03-17 03:32:20] [INFO ] Invariant cache hit.
[2023-03-17 03:32:22] [INFO ] After 2428ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:73
[2023-03-17 03:32:25] [INFO ] [Nat]Absence check using 10 positive place invariants in 12 ms returned sat
[2023-03-17 03:32:47] [INFO ] After 20853ms SMT Verify possible using state equation in natural domain returned unsat :5 sat :49
[2023-03-17 03:32:49] [INFO ] State equation strengthened by 5248 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-17 03:32:49] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-17 03:32:49] [INFO ] After 26213ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:73
Fused 73 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 151 out of 1967 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1967/1967 places, 149582/149582 transitions.
Graph (trivial) has 1582 edges and 1967 vertex of which 109 / 1967 are part of one of the 41 SCC in 27 ms
Free SCC test removed 68 places
Drop transitions removed 3829 transitions
Ensure Unique test removed 462 transitions
Reduce isomorphic transitions removed 4291 transitions.
Graph (complete) has 126304 edges and 1899 vertex of which 1898 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.116 ms
Discarding 1 places :
Also discarding 0 output transitions
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded 5 transitions
Performed 5 trivial Post agglomeration. Transition count delta: 5
Iterating post reduction 0 with 6 rules applied. Total rules applied 8 place count 1898 transition count 145285
Reduce places removed 5 places and 0 transitions.
Iterating post reduction 1 with 5 rules applied. Total rules applied 13 place count 1893 transition count 145285
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 2 Pre rules applied. Total rules applied 13 place count 1893 transition count 145283
Deduced a syphon composed of 2 places in 67 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 4 rules applied. Total rules applied 17 place count 1891 transition count 145283
Discarding 7 places :
Symmetric choice reduction at 2 with 7 rule applications. Total rules 24 place count 1884 transition count 145276
Iterating global reduction 2 with 7 rules applied. Total rules applied 31 place count 1884 transition count 145276
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 2 with 7 rules applied. Total rules applied 38 place count 1884 transition count 145269
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 44 place count 1878 transition count 145257
Iterating global reduction 3 with 6 rules applied. Total rules applied 50 place count 1878 transition count 145257
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 3 with 6 rules applied. Total rules applied 56 place count 1878 transition count 145251
Discarding 3 places :
Symmetric choice reduction at 4 with 3 rule applications. Total rules 59 place count 1875 transition count 145245
Iterating global reduction 4 with 3 rules applied. Total rules applied 62 place count 1875 transition count 145245
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 4 with 3 rules applied. Total rules applied 65 place count 1875 transition count 145242
Performed 26 Post agglomeration using F-continuation condition.Transition count delta: 26
Deduced a syphon composed of 26 places in 65 ms
Reduce places removed 26 places and 0 transitions.
Iterating global reduction 5 with 52 rules applied. Total rules applied 117 place count 1849 transition count 145216
Drop transitions removed 6 transitions
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 5 with 7 rules applied. Total rules applied 124 place count 1849 transition count 145209
Performed 27 Post agglomeration using F-continuation condition.Transition count delta: -95
Deduced a syphon composed of 27 places in 65 ms
Reduce places removed 27 places and 0 transitions.
Iterating global reduction 6 with 54 rules applied. Total rules applied 178 place count 1822 transition count 145304
Drop transitions removed 4 transitions
Ensure Unique test removed 19 transitions
Reduce isomorphic transitions removed 23 transitions.
Iterating post reduction 6 with 23 rules applied. Total rules applied 201 place count 1822 transition count 145281
Free-agglomeration rule applied 18 times with reduction of 2 identical transitions.
Iterating global reduction 7 with 18 rules applied. Total rules applied 219 place count 1822 transition count 145261
Reduce places removed 18 places and 0 transitions.
Drop transitions removed 8 transitions
Ensure Unique test removed 533 transitions
Reduce isomorphic transitions removed 541 transitions.
Iterating post reduction 7 with 559 rules applied. Total rules applied 778 place count 1804 transition count 144720
Free-agglomeration rule (complex) applied 117 times with reduction of 2647 identical transitions.
Iterating global reduction 8 with 117 rules applied. Total rules applied 895 place count 1804 transition count 170019
Reduce places removed 117 places and 0 transitions.
Drop transitions removed 133 transitions
Ensure Unique test removed 6556 transitions
Reduce isomorphic transitions removed 6689 transitions.
Iterating post reduction 8 with 6806 rules applied. Total rules applied 7701 place count 1687 transition count 163330
Applied a total of 7701 rules in 8738 ms. Remains 1687 /1967 variables (removed 280) and now considering 163330/149582 (removed -13748) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 8744 ms. Remains : 1687/1967 places, 163330/149582 transitions.
Incomplete random walk after 10000 steps, including 3 resets, run finished after 1348 ms. (steps per millisecond=7 ) properties (out of 68) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 67) seen :0
Interrupted probabilistic random walk after 8594 steps, run timeout after 6005 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 8594 steps, saw 7106 distinct states, run finished after 6006 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 67 properties.
[2023-03-17 03:33:06] [INFO ] Flow matrix only has 120565 transitions (discarded 42765 similar events)
// Phase 1: matrix 120565 rows 1687 cols
[2023-03-17 03:33:07] [INFO ] Computed 10 place invariants in 678 ms
[2023-03-17 03:33:08] [INFO ] After 1845ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:67
[2023-03-17 03:33:10] [INFO ] [Nat]Absence check using 10 positive place invariants in 13 ms returned sat
[2023-03-17 03:33:33] [INFO ] After 21582ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :66
[2023-03-17 03:33:35] [INFO ] State equation strengthened by 5987 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-17 03:33:35] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-17 03:33:35] [INFO ] After 26093ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:67
Fused 67 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 149 out of 1687 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1687/1687 places, 163330/163330 transitions.
Applied a total of 0 rules in 763 ms. Remains 1687 /1687 variables (removed 0) and now considering 163330/163330 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 764 ms. Remains : 1687/1687 places, 163330/163330 transitions.
Incomplete random walk after 10000 steps, including 4 resets, run finished after 1525 ms. (steps per millisecond=6 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 89 ms. (steps per millisecond=11 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 67) seen :0
Interrupted probabilistic random walk after 7786 steps, run timeout after 6001 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 7786 steps, saw 6415 distinct states, run finished after 6001 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 67 properties.
[2023-03-17 03:33:44] [INFO ] Flow matrix only has 120565 transitions (discarded 42765 similar events)
[2023-03-17 03:33:44] [INFO ] Invariant cache hit.
[2023-03-17 03:33:46] [INFO ] After 1905ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:67
[2023-03-17 03:33:48] [INFO ] [Nat]Absence check using 10 positive place invariants in 13 ms returned sat
[2023-03-17 03:34:11] [INFO ] After 21565ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :66
[2023-03-17 03:34:13] [INFO ] State equation strengthened by 5987 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-17 03:34:13] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-17 03:34:13] [INFO ] After 26869ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:67
Fused 67 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 149 out of 1687 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1687/1687 places, 163330/163330 transitions.
Applied a total of 0 rules in 945 ms. Remains 1687 /1687 variables (removed 0) and now considering 163330/163330 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 946 ms. Remains : 1687/1687 places, 163330/163330 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1687/1687 places, 163330/163330 transitions.
Applied a total of 0 rules in 794 ms. Remains 1687 /1687 variables (removed 0) and now considering 163330/163330 (removed 0) transitions.
[2023-03-17 03:34:15] [INFO ] Flow matrix only has 120565 transitions (discarded 42765 similar events)
[2023-03-17 03:34:15] [INFO ] Invariant cache hit.
[2023-03-17 03:34:22] [INFO ] Implicit Places using invariants in 7405 ms returned []
Implicit Place search using SMT only with invariants took 7406 ms to find 0 implicit places.
[2023-03-17 03:34:22] [INFO ] Flow matrix only has 120565 transitions (discarded 42765 similar events)
[2023-03-17 03:34:22] [INFO ] Invariant cache hit.
[2023-03-17 03:34:52] [INFO ] Performed 91277/163330 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-17 03:35:16] [INFO ] Dead Transitions using invariants and state equation in 54048 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 62267 ms. Remains : 1687/1687 places, 163330/163330 transitions.
Successfully simplified 5 atomic propositions for a total of 16 simplifications.
FORMULA RERS2020-PT-pb105-CTLFireability-01 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-17 03:35:20] [INFO ] Flatten gal took : 3441 ms
[2023-03-17 03:35:24] [INFO ] Flatten gal took : 3707 ms
[2023-03-17 03:35:33] [INFO ] Input system was already deterministic with 149582 transitions.
Support contains 138 out of 1967 places (down from 144) after GAL structural reductions.
Computed a total of 188 stabilizing places and 32921 stable transitions
Graph (complete) has 144489 edges and 1967 vertex of which 1966 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.461 ms
Starting structural reductions in LTL mode, iteration 0 : 1967/1967 places, 149582/149582 transitions.
Applied a total of 0 rules in 223 ms. Remains 1967 /1967 variables (removed 0) and now considering 149582/149582 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 225 ms. Remains : 1967/1967 places, 149582/149582 transitions.
[2023-03-17 03:35:37] [INFO ] Flatten gal took : 3043 ms
[2023-03-17 03:35:41] [INFO ] Flatten gal took : 3571 ms
[2023-03-17 03:35:47] [INFO ] Input system was already deterministic with 149582 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1967/1967 places, 149582/149582 transitions.
Graph (trivial) has 1666 edges and 1967 vertex of which 115 / 1967 are part of one of the 43 SCC in 5 ms
Free SCC test removed 72 places
Ensure Unique test removed 586 transitions
Reduce isomorphic transitions removed 586 transitions.
Graph (complete) has 143614 edges and 1895 vertex of which 1894 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.125 ms
Discarding 1 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 2 rules applied. Total rules applied 4 place count 1893 transition count 148992
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 6 place count 1891 transition count 148992
Performed 3 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 3 Pre rules applied. Total rules applied 6 place count 1891 transition count 148989
Deduced a syphon composed of 3 places in 61 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 2 with 6 rules applied. Total rules applied 12 place count 1888 transition count 148989
Discarding 6 places :
Symmetric choice reduction at 2 with 6 rule applications. Total rules 18 place count 1882 transition count 148977
Iterating global reduction 2 with 6 rules applied. Total rules applied 24 place count 1882 transition count 148977
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 2 with 6 rules applied. Total rules applied 30 place count 1882 transition count 148971
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 36 place count 1876 transition count 148959
Iterating global reduction 3 with 6 rules applied. Total rules applied 42 place count 1876 transition count 148959
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 3 with 6 rules applied. Total rules applied 48 place count 1876 transition count 148953
Discarding 3 places :
Symmetric choice reduction at 4 with 3 rule applications. Total rules 51 place count 1873 transition count 148947
Iterating global reduction 4 with 3 rules applied. Total rules applied 54 place count 1873 transition count 148947
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 4 with 3 rules applied. Total rules applied 57 place count 1873 transition count 148944
Performed 10 Post agglomeration using F-continuation condition.Transition count delta: 10
Deduced a syphon composed of 10 places in 61 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 5 with 20 rules applied. Total rules applied 77 place count 1863 transition count 148934
Applied a total of 77 rules in 4680 ms. Remains 1863 /1967 variables (removed 104) and now considering 148934/149582 (removed 648) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4684 ms. Remains : 1863/1967 places, 148934/149582 transitions.
[2023-03-17 03:35:55] [INFO ] Flatten gal took : 3037 ms
[2023-03-17 03:35:59] [INFO ] Flatten gal took : 3511 ms
[2023-03-17 03:36:05] [INFO ] Input system was already deterministic with 148934 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1398 ms. (steps per millisecond=7 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 157 ms. (steps per millisecond=63 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 3633 steps, run timeout after 3004 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 3633 steps, saw 2811 distinct states, run finished after 3004 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-17 03:36:10] [INFO ] Flow matrix only has 104664 transitions (discarded 44270 similar events)
// Phase 1: matrix 104664 rows 1863 cols
[2023-03-17 03:36:11] [INFO ] Computed 10 place invariants in 443 ms
[2023-03-17 03:36:11] [INFO ] After 196ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-17 03:36:11] [INFO ] [Nat]Absence check using 10 positive place invariants in 11 ms returned sat
[2023-03-17 03:36:36] [INFO ] After 25025ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 0 ms.
Support contains 2 out of 1863 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1863/1863 places, 148934/148934 transitions.
Drop transitions removed 3747 transitions
Reduce isomorphic transitions removed 3747 transitions.
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded 3 transitions
Performed 3 trivial Post agglomeration. Transition count delta: 3
Iterating post reduction 0 with 3750 rules applied. Total rules applied 3750 place count 1863 transition count 145184
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 1 with 3 rules applied. Total rules applied 3753 place count 1860 transition count 145184
Performed 17 Post agglomeration using F-continuation condition.Transition count delta: 17
Deduced a syphon composed of 17 places in 70 ms
Reduce places removed 17 places and 0 transitions.
Iterating global reduction 2 with 34 rules applied. Total rules applied 3787 place count 1843 transition count 145167
Drop transitions removed 4 transitions
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 2 with 6 rules applied. Total rules applied 3793 place count 1843 transition count 145161
Performed 28 Post agglomeration using F-continuation condition.Transition count delta: -96
Deduced a syphon composed of 28 places in 71 ms
Reduce places removed 28 places and 0 transitions.
Iterating global reduction 3 with 56 rules applied. Total rules applied 3849 place count 1815 transition count 145257
Drop transitions removed 4 transitions
Ensure Unique test removed 19 transitions
Reduce isomorphic transitions removed 23 transitions.
Iterating post reduction 3 with 23 rules applied. Total rules applied 3872 place count 1815 transition count 145234
Free-agglomeration rule applied 25 times with reduction of 6 identical transitions.
Iterating global reduction 4 with 25 rules applied. Total rules applied 3897 place count 1815 transition count 145203
Reduce places removed 25 places and 0 transitions.
Drop transitions removed 8 transitions
Ensure Unique test removed 578 transitions
Reduce isomorphic transitions removed 586 transitions.
Iterating post reduction 4 with 611 rules applied. Total rules applied 4508 place count 1790 transition count 144617
Free-agglomeration rule applied 3 times.
Iterating global reduction 5 with 3 rules applied. Total rules applied 4511 place count 1790 transition count 144614
Reduce places removed 3 places and 0 transitions.
Ensure Unique test removed 53 transitions
Reduce isomorphic transitions removed 53 transitions.
Iterating post reduction 5 with 56 rules applied. Total rules applied 4567 place count 1787 transition count 144561
Free-agglomeration rule applied 3 times.
Iterating global reduction 6 with 3 rules applied. Total rules applied 4570 place count 1787 transition count 144558
Reduce places removed 3 places and 0 transitions.
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 6 with 6 rules applied. Total rules applied 4576 place count 1784 transition count 144555
Free-agglomeration rule applied 1 times.
Iterating global reduction 7 with 1 rules applied. Total rules applied 4577 place count 1784 transition count 144554
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 7 with 1 rules applied. Total rules applied 4578 place count 1783 transition count 144554
Free-agglomeration rule (complex) applied 116 times with reduction of 3658 identical transitions.
Iterating global reduction 8 with 116 rules applied. Total rules applied 4694 place count 1783 transition count 172995
Reduce places removed 116 places and 0 transitions.
Drop transitions removed 138 transitions
Ensure Unique test removed 7636 transitions
Reduce isomorphic transitions removed 7774 transitions.
Iterating post reduction 8 with 7890 rules applied. Total rules applied 12584 place count 1667 transition count 165221
Applied a total of 12584 rules in 9669 ms. Remains 1667 /1863 variables (removed 196) and now considering 165221/148934 (removed -16287) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 9675 ms. Remains : 1667/1863 places, 165221/148934 transitions.
Interrupted random walk after 295855 steps, including 0 resets, run timeout after 30001 ms. (steps per millisecond=9 ) properties seen 0
Interrupted Best-First random walk after 562831 steps, including 1 resets, run timeout after 5001 ms. (steps per millisecond=112 ) properties seen 0
Interrupted probabilistic random walk after 157205 steps, run timeout after 105006 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 157205 steps, saw 126753 distinct states, run finished after 105006 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-17 03:39:06] [INFO ] Flow matrix only has 122274 transitions (discarded 42947 similar events)
// Phase 1: matrix 122274 rows 1667 cols
[2023-03-17 03:39:06] [INFO ] Computed 10 place invariants in 638 ms
[2023-03-17 03:39:07] [INFO ] After 182ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-17 03:39:07] [INFO ] [Nat]Absence check using 10 positive place invariants in 12 ms returned sat
[2023-03-17 03:39:44] [INFO ] After 37425ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-17 03:39:46] [INFO ] State equation strengthened by 6068 read => feed constraints.
[2023-03-17 03:40:06] [INFO ] After 19776ms SMT Verify possible using 6068 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-17 03:40:21] [INFO ] Deduced a trap composed of 24 places in 13192 ms of which 6 ms to minimize.
[2023-03-17 03:40:36] [INFO ] Deduced a trap composed of 143 places in 13248 ms of which 2 ms to minimize.
[2023-03-17 03:40:51] [INFO ] Deduced a trap composed of 28 places in 13638 ms of which 3 ms to minimize.
[2023-03-17 03:41:06] [INFO ] Deduced a trap composed of 221 places in 13547 ms of which 3 ms to minimize.
[2023-03-17 03:41:20] [INFO ] Deduced a trap composed of 134 places in 12965 ms of which 2 ms to minimize.
[2023-03-17 03:41:35] [INFO ] Deduced a trap composed of 29 places in 13111 ms of which 2 ms to minimize.
[2023-03-17 03:41:49] [INFO ] Deduced a trap composed of 219 places in 12725 ms of which 1 ms to minimize.
[2023-03-17 03:42:03] [INFO ] Deduced a trap composed of 218 places in 12710 ms of which 2 ms to minimize.
[2023-03-17 03:42:18] [INFO ] Deduced a trap composed of 115 places in 12947 ms of which 2 ms to minimize.
[2023-03-17 03:42:33] [INFO ] Deduced a trap composed of 245 places in 13159 ms of which 2 ms to minimize.
[2023-03-17 03:42:35] [INFO ] Trap strengthening (SAT) tested/added 11/10 trap constraints in 148696 ms
[2023-03-17 03:42:36] [INFO ] After 169511ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 1612 ms.
[2023-03-17 03:42:37] [INFO ] After 210796ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 0 ms.
Support contains 2 out of 1667 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1667/1667 places, 165221/165221 transitions.
Applied a total of 0 rules in 719 ms. Remains 1667 /1667 variables (removed 0) and now considering 165221/165221 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 719 ms. Remains : 1667/1667 places, 165221/165221 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1667/1667 places, 165221/165221 transitions.
Applied a total of 0 rules in 719 ms. Remains 1667 /1667 variables (removed 0) and now considering 165221/165221 (removed 0) transitions.
[2023-03-17 03:42:39] [INFO ] Flow matrix only has 122274 transitions (discarded 42947 similar events)
[2023-03-17 03:42:39] [INFO ] Invariant cache hit.
[2023-03-17 03:42:47] [INFO ] Implicit Places using invariants in 8612 ms returned []
Implicit Place search using SMT only with invariants took 8619 ms to find 0 implicit places.
[2023-03-17 03:42:47] [INFO ] Flow matrix only has 122274 transitions (discarded 42947 similar events)
[2023-03-17 03:42:47] [INFO ] Invariant cache hit.
[2023-03-17 03:43:18] [INFO ] Performed 93757/165221 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-17 03:43:40] [INFO ] Dead Transitions using invariants and state equation in 52196 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 61548 ms. Remains : 1667/1667 places, 165221/165221 transitions.
Incomplete random walk after 100000 steps, including 3 resets, run finished after 10934 ms. (steps per millisecond=9 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-17 03:43:51] [INFO ] Flow matrix only has 122274 transitions (discarded 42947 similar events)
[2023-03-17 03:43:51] [INFO ] Invariant cache hit.
[2023-03-17 03:43:51] [INFO ] [Real]Absence check using 10 positive place invariants in 8 ms returned sat
[2023-03-17 03:44:27] [INFO ] After 36255ms SMT Verify possible using state equation in real domain returned unsat :0 sat :2
[2023-03-17 03:44:30] [INFO ] State equation strengthened by 6068 read => feed constraints.
[2023-03-17 03:44:47] [INFO ] After 17262ms SMT Verify possible using 6068 Read/Feed constraints in real domain returned unsat :0 sat :2
[2023-03-17 03:45:01] [INFO ] Deduced a trap composed of 24 places in 12861 ms of which 2 ms to minimize.
[2023-03-17 03:45:16] [INFO ] Deduced a trap composed of 28 places in 12646 ms of which 2 ms to minimize.
[2023-03-17 03:45:29] [INFO ] Deduced a trap composed of 47 places in 12011 ms of which 1 ms to minimize.
[2023-03-17 03:45:43] [INFO ] Deduced a trap composed of 88 places in 12642 ms of which 2 ms to minimize.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.refineWithTraps(DeadlockTester.java:1255)
at fr.lip6.move.gal.structural.smt.DeadlockTester.refineResultsWithTraps(DeadlockTester.java:736)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:656)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:215)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositions(AtomicReducerSR.java:267)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:46)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:225)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:669)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-17 03:45:43] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-17 03:45:43] [INFO ] After 112508ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Interrupted random walk after 247361 steps, including 0 resets, run timeout after 30001 ms. (steps per millisecond=8 ) properties seen 0
Interrupted Best-First random walk after 452397 steps, including 1 resets, run timeout after 5001 ms. (steps per millisecond=90 ) properties seen 0
Interrupted probabilistic random walk after 133116 steps, run timeout after 105008 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 133116 steps, saw 107140 distinct states, run finished after 105008 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-17 03:48:03] [INFO ] Flow matrix only has 122274 transitions (discarded 42947 similar events)
[2023-03-17 03:48:04] [INFO ] Invariant cache hit.
[2023-03-17 03:48:04] [INFO ] After 174ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-17 03:48:04] [INFO ] [Nat]Absence check using 10 positive place invariants in 11 ms returned sat
[2023-03-17 03:48:43] [INFO ] After 38796ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-17 03:48:44] [INFO ] State equation strengthened by 6068 read => feed constraints.
[2023-03-17 03:49:09] [INFO ] After 25686ms SMT Verify possible using 6068 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-17 03:49:25] [INFO ] Deduced a trap composed of 24 places in 14121 ms of which 2 ms to minimize.
[2023-03-17 03:49:42] [INFO ] Deduced a trap composed of 143 places in 15086 ms of which 2 ms to minimize.
[2023-03-17 03:49:58] [INFO ] Deduced a trap composed of 28 places in 14381 ms of which 2 ms to minimize.
[2023-03-17 03:50:13] [INFO ] Deduced a trap composed of 221 places in 13696 ms of which 3 ms to minimize.
[2023-03-17 03:50:30] [INFO ] Deduced a trap composed of 134 places in 15010 ms of which 2 ms to minimize.
[2023-03-17 03:50:45] [INFO ] Deduced a trap composed of 29 places in 13830 ms of which 2 ms to minimize.
[2023-03-17 03:51:00] [INFO ] Deduced a trap composed of 219 places in 13394 ms of which 2 ms to minimize.
[2023-03-17 03:51:16] [INFO ] Deduced a trap composed of 218 places in 14138 ms of which 2 ms to minimize.
[2023-03-17 03:51:30] [INFO ] Deduced a trap composed of 115 places in 12577 ms of which 2 ms to minimize.
[2023-03-17 03:51:45] [INFO ] Deduced a trap composed of 245 places in 13582 ms of which 2 ms to minimize.
[2023-03-17 03:51:49] [INFO ] Trap strengthening (SAT) tested/added 11/10 trap constraints in 159458 ms
[2023-03-17 03:51:49] [INFO ] After 185227ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 21 ms.
[2023-03-17 03:51:49] [INFO ] After 225310ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 0 ms.
Support contains 2 out of 1667 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1667/1667 places, 165221/165221 transitions.
Applied a total of 0 rules in 763 ms. Remains 1667 /1667 variables (removed 0) and now considering 165221/165221 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 763 ms. Remains : 1667/1667 places, 165221/165221 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1667/1667 places, 165221/165221 transitions.
Applied a total of 0 rules in 759 ms. Remains 1667 /1667 variables (removed 0) and now considering 165221/165221 (removed 0) transitions.
[2023-03-17 03:51:51] [INFO ] Flow matrix only has 122274 transitions (discarded 42947 similar events)
[2023-03-17 03:51:51] [INFO ] Invariant cache hit.
[2023-03-17 03:51:59] [INFO ] Implicit Places using invariants in 8881 ms returned []
Implicit Place search using SMT only with invariants took 8882 ms to find 0 implicit places.
[2023-03-17 03:51:59] [INFO ] Flow matrix only has 122274 transitions (discarded 42947 similar events)
[2023-03-17 03:51:59] [INFO ] Invariant cache hit.
[2023-03-17 03:52:30] [INFO ] Performed 93106/165221 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-17 03:52:52] [INFO ] Dead Transitions using invariants and state equation in 52351 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 62008 ms. Remains : 1667/1667 places, 165221/165221 transitions.
Incomplete random walk after 100000 steps, including 2 resets, run finished after 10405 ms. (steps per millisecond=9 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-17 03:53:02] [INFO ] Flow matrix only has 122274 transitions (discarded 42947 similar events)
[2023-03-17 03:53:02] [INFO ] Invariant cache hit.
[2023-03-17 03:53:03] [INFO ] [Real]Absence check using 10 positive place invariants in 7 ms returned sat
[2023-03-17 03:53:48] [INFO ] After 45477ms SMT Verify possible using state equation in real domain returned unsat :0 sat :2
[2023-03-17 03:53:49] [INFO ] State equation strengthened by 6068 read => feed constraints.
[2023-03-17 03:54:08] [INFO ] After 19037ms SMT Verify possible using 6068 Read/Feed constraints in real domain returned unsat :0 sat :2
[2023-03-17 03:54:24] [INFO ] Deduced a trap composed of 24 places in 14081 ms of which 2 ms to minimize.
[2023-03-17 03:54:41] [INFO ] Deduced a trap composed of 28 places in 14775 ms of which 2 ms to minimize.
[2023-03-17 03:54:54] [INFO ] Deduced a trap composed of 47 places in 12294 ms of which 12 ms to minimize.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.refineWithTraps(DeadlockTester.java:1255)
at fr.lip6.move.gal.structural.smt.DeadlockTester.refineResultsWithTraps(DeadlockTester.java:736)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:656)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:215)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositions(AtomicReducerSR.java:267)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:253)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:669)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-17 03:54:54] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-17 03:54:54] [INFO ] After 111938ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Incomplete random walk after 10000 steps, including 2 resets, run finished after 897 ms. (steps per millisecond=11 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 101 ms. (steps per millisecond=99 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 4483 steps, run timeout after 3002 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 4483 steps, saw 3718 distinct states, run finished after 3003 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-17 03:54:59] [INFO ] Flow matrix only has 122274 transitions (discarded 42947 similar events)
[2023-03-17 03:54:59] [INFO ] Invariant cache hit.
[2023-03-17 03:54:59] [INFO ] After 157ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-17 03:54:59] [INFO ] [Nat]Absence check using 10 positive place invariants in 9 ms returned sat
[2023-03-17 03:55:24] [INFO ] After 25023ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 0 ms.
Support contains 1 out of 1667 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1667/1667 places, 165221/165221 transitions.
Applied a total of 0 rules in 747 ms. Remains 1667 /1667 variables (removed 0) and now considering 165221/165221 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 751 ms. Remains : 1667/1667 places, 165221/165221 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1151 ms. (steps per millisecond=8 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 109 ms. (steps per millisecond=91 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 3848 steps, run timeout after 3003 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 3848 steps, saw 3196 distinct states, run finished after 3003 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-17 03:55:29] [INFO ] Flow matrix only has 122274 transitions (discarded 42947 similar events)
[2023-03-17 03:55:29] [INFO ] Invariant cache hit.
[2023-03-17 03:55:29] [INFO ] After 168ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-17 03:55:29] [INFO ] [Nat]Absence check using 10 positive place invariants in 12 ms returned sat
[2023-03-17 03:55:54] [INFO ] After 25022ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 0 ms.
Support contains 1 out of 1667 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1667/1667 places, 165221/165221 transitions.
Applied a total of 0 rules in 810 ms. Remains 1667 /1667 variables (removed 0) and now considering 165221/165221 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 811 ms. Remains : 1667/1667 places, 165221/165221 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1667/1667 places, 165221/165221 transitions.
Applied a total of 0 rules in 707 ms. Remains 1667 /1667 variables (removed 0) and now considering 165221/165221 (removed 0) transitions.
[2023-03-17 03:55:56] [INFO ] Flow matrix only has 122274 transitions (discarded 42947 similar events)
[2023-03-17 03:55:56] [INFO ] Invariant cache hit.
[2023-03-17 03:56:05] [INFO ] Implicit Places using invariants in 9009 ms returned []
Implicit Place search using SMT only with invariants took 9010 ms to find 0 implicit places.
[2023-03-17 03:56:05] [INFO ] Flow matrix only has 122274 transitions (discarded 42947 similar events)
[2023-03-17 03:56:05] [INFO ] Invariant cache hit.
[2023-03-17 03:56:35] [INFO ] Performed 90809/165221 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-17 03:56:58] [INFO ] Dead Transitions using invariants and state equation in 53488 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 63227 ms. Remains : 1667/1667 places, 165221/165221 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1750 ms. (steps per millisecond=5 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 100 ms. (steps per millisecond=100 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 4512 steps, run timeout after 3001 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 4512 steps, saw 3741 distinct states, run finished after 3001 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-17 03:57:04] [INFO ] Flow matrix only has 122274 transitions (discarded 42947 similar events)
[2023-03-17 03:57:04] [INFO ] Invariant cache hit.
[2023-03-17 03:57:04] [INFO ] After 167ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-17 03:57:04] [INFO ] [Nat]Absence check using 10 positive place invariants in 11 ms returned sat
[2023-03-17 03:57:29] [INFO ] After 25017ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 0 ms.
Support contains 1 out of 1667 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1667/1667 places, 165221/165221 transitions.
Applied a total of 0 rules in 730 ms. Remains 1667 /1667 variables (removed 0) and now considering 165221/165221 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 734 ms. Remains : 1667/1667 places, 165221/165221 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1029 ms. (steps per millisecond=9 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 133 ms. (steps per millisecond=75 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 4189 steps, run timeout after 3002 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 4189 steps, saw 3480 distinct states, run finished after 3002 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-17 03:57:34] [INFO ] Flow matrix only has 122274 transitions (discarded 42947 similar events)
[2023-03-17 03:57:34] [INFO ] Invariant cache hit.
[2023-03-17 03:57:34] [INFO ] After 163ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-17 03:57:34] [INFO ] [Nat]Absence check using 10 positive place invariants in 10 ms returned sat
[2023-03-17 03:57:59] [INFO ] After 25023ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 0 ms.
Support contains 1 out of 1667 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1667/1667 places, 165221/165221 transitions.
Applied a total of 0 rules in 822 ms. Remains 1667 /1667 variables (removed 0) and now considering 165221/165221 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 822 ms. Remains : 1667/1667 places, 165221/165221 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1667/1667 places, 165221/165221 transitions.
Applied a total of 0 rules in 738 ms. Remains 1667 /1667 variables (removed 0) and now considering 165221/165221 (removed 0) transitions.
[2023-03-17 03:58:01] [INFO ] Flow matrix only has 122274 transitions (discarded 42947 similar events)
[2023-03-17 03:58:01] [INFO ] Invariant cache hit.
[2023-03-17 03:58:10] [INFO ] Implicit Places using invariants in 8844 ms returned []
Implicit Place search using SMT only with invariants took 8845 ms to find 0 implicit places.
[2023-03-17 03:58:10] [INFO ] Flow matrix only has 122274 transitions (discarded 42947 similar events)
[2023-03-17 03:58:10] [INFO ] Invariant cache hit.
[2023-03-17 03:58:40] [INFO ] Performed 90407/165221 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-17 03:59:04] [INFO ] Dead Transitions using invariants and state equation in 54386 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 63984 ms. Remains : 1667/1667 places, 165221/165221 transitions.
Graph (trivial) has 49645 edges and 1667 vertex of which 1435 / 1667 are part of one of the 192 SCC in 8 ms
Free SCC test removed 1243 places
Drop transitions removed 71062 transitions
Ensure Unique test removed 81477 transitions
Reduce isomorphic transitions removed 152539 transitions.
Graph (complete) has 9078 edges and 424 vertex of which 403 are kept as prefixes of interest. Removing 21 places using SCC suffix rule.6 ms
Discarding 21 places :
Also discarding 8 output transitions
Drop transitions removed 8 transitions
Drop transitions removed 56 transitions
Ensure Unique test removed 364 transitions
Reduce isomorphic transitions removed 420 transitions.
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded 4 transitions
Performed 4 trivial Post agglomeration. Transition count delta: 4
Iterating post reduction 0 with 424 rules applied. Total rules applied 426 place count 403 transition count 12250
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 430 place count 399 transition count 12250
Discarding 7 places :
Symmetric choice reduction at 2 with 7 rule applications. Total rules 437 place count 392 transition count 12237
Iterating global reduction 2 with 7 rules applied. Total rules applied 444 place count 392 transition count 12237
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 447 place count 389 transition count 12222
Iterating global reduction 2 with 3 rules applied. Total rules applied 450 place count 389 transition count 12222
Performed 7 Post agglomeration using F-continuation condition.Transition count delta: 7
Deduced a syphon composed of 7 places in 2 ms
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 2 with 14 rules applied. Total rules applied 464 place count 382 transition count 12215
Ensure Unique test removed 123 transitions
Reduce isomorphic transitions removed 123 transitions.
Iterating post reduction 2 with 123 rules applied. Total rules applied 587 place count 382 transition count 12092
Drop transitions removed 5875 transitions
Redundant transition composition rules discarded 5875 transitions
Iterating global reduction 3 with 5875 rules applied. Total rules applied 6462 place count 382 transition count 6217
Reduce places removed 4 places and 0 transitions.
Drop transitions removed 10 transitions
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 16 transitions.
Graph (complete) has 5422 edges and 378 vertex of which 341 are kept as prefixes of interest. Removing 37 places using SCC suffix rule.2 ms
Discarding 37 places :
Also discarding 17 output transitions
Drop transitions removed 17 transitions
Iterating post reduction 3 with 21 rules applied. Total rules applied 6483 place count 341 transition count 6184
Drop transitions removed 731 transitions
Ensure Unique test removed 18 transitions
Reduce isomorphic transitions removed 749 transitions.
Iterating post reduction 4 with 749 rules applied. Total rules applied 7232 place count 341 transition count 5435
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 1 Pre rules applied. Total rules applied 7232 place count 341 transition count 5434
Deduced a syphon composed of 1 places in 2 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 5 with 2 rules applied. Total rules applied 7234 place count 340 transition count 5434
Discarding 11 places :
Symmetric choice reduction at 5 with 11 rule applications. Total rules 7245 place count 329 transition count 5414
Iterating global reduction 5 with 11 rules applied. Total rules applied 7256 place count 329 transition count 5414
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 5 with 2 rules applied. Total rules applied 7258 place count 329 transition count 5412
Discarding 2 places :
Symmetric choice reduction at 6 with 2 rule applications. Total rules 7260 place count 327 transition count 5408
Iterating global reduction 6 with 2 rules applied. Total rules applied 7262 place count 327 transition count 5408
Discarding 1 places :
Symmetric choice reduction at 6 with 1 rule applications. Total rules 7263 place count 326 transition count 5407
Iterating global reduction 6 with 1 rules applied. Total rules applied 7264 place count 326 transition count 5407
Performed 5 Post agglomeration using F-continuation condition.Transition count delta: 5
Deduced a syphon composed of 5 places in 1 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 6 with 10 rules applied. Total rules applied 7274 place count 321 transition count 5402
Drop transitions removed 36 transitions
Redundant transition composition rules discarded 36 transitions
Iterating global reduction 6 with 36 rules applied. Total rules applied 7310 place count 321 transition count 5366
Free-agglomeration rule applied 11 times.
Iterating global reduction 6 with 11 rules applied. Total rules applied 7321 place count 321 transition count 5355
Reduce places removed 11 places and 0 transitions.
Ensure Unique test removed 14 transitions
Reduce isomorphic transitions removed 14 transitions.
Iterating post reduction 6 with 25 rules applied. Total rules applied 7346 place count 310 transition count 5341
Drop transitions removed 122 transitions
Redundant transition composition rules discarded 122 transitions
Iterating global reduction 7 with 122 rules applied. Total rules applied 7468 place count 310 transition count 5219
Free-agglomeration rule applied 11 times.
Iterating global reduction 7 with 11 rules applied. Total rules applied 7479 place count 310 transition count 5208
Reduce places removed 11 places and 0 transitions.
Ensure Unique test removed 29 transitions
Reduce isomorphic transitions removed 29 transitions.
Iterating post reduction 7 with 40 rules applied. Total rules applied 7519 place count 299 transition count 5179
Drop transitions removed 76 transitions
Redundant transition composition rules discarded 76 transitions
Iterating global reduction 8 with 76 rules applied. Total rules applied 7595 place count 299 transition count 5103
Free-agglomeration rule applied 3 times.
Iterating global reduction 8 with 3 rules applied. Total rules applied 7598 place count 299 transition count 5100
Reduce places removed 3 places and 0 transitions.
Ensure Unique test removed 14 transitions
Reduce isomorphic transitions removed 14 transitions.
Iterating post reduction 8 with 17 rules applied. Total rules applied 7615 place count 296 transition count 5086
Drop transitions removed 24 transitions
Redundant transition composition rules discarded 24 transitions
Iterating global reduction 9 with 24 rules applied. Total rules applied 7639 place count 296 transition count 5062
Free-agglomeration rule (complex) applied 13 times with reduction of 216 identical transitions.
Iterating global reduction 9 with 13 rules applied. Total rules applied 7652 place count 296 transition count 5565
Reduce places removed 13 places and 0 transitions.
Ensure Unique test removed 278 transitions
Reduce isomorphic transitions removed 278 transitions.
Iterating post reduction 9 with 291 rules applied. Total rules applied 7943 place count 283 transition count 5287
Drop transitions removed 158 transitions
Redundant transition composition rules discarded 158 transitions
Iterating global reduction 10 with 158 rules applied. Total rules applied 8101 place count 283 transition count 5129
Partial Free-agglomeration rule applied 107 times.
Drop transitions removed 107 transitions
Iterating global reduction 10 with 107 rules applied. Total rules applied 8208 place count 283 transition count 5129
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 10 with 4 rules applied. Total rules applied 8212 place count 283 transition count 5125
Discarding 3 places :
Symmetric choice reduction at 11 with 3 rule applications. Total rules 8215 place count 280 transition count 5122
Iterating global reduction 11 with 3 rules applied. Total rules applied 8218 place count 280 transition count 5122
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 11 with 6 rules applied. Total rules applied 8224 place count 280 transition count 5116
Drop transitions removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 12 with 2 rules applied. Total rules applied 8226 place count 280 transition count 5114
Partial Free-agglomeration rule applied 93 times.
Drop transitions removed 93 transitions
Iterating global reduction 12 with 93 rules applied. Total rules applied 8319 place count 280 transition count 5114
Ensure Unique test removed 14 transitions
Reduce isomorphic transitions removed 14 transitions.
Iterating post reduction 12 with 14 rules applied. Total rules applied 8333 place count 280 transition count 5100
Applied a total of 8333 rules in 5146 ms. Remains 280 /1667 variables (removed 1387) and now considering 5100/165221 (removed 160121) transitions.
Running SMT prover for 1 properties.
[2023-03-17 03:59:09] [INFO ] Flow matrix only has 4940 transitions (discarded 160 similar events)
// Phase 1: matrix 4940 rows 280 cols
[2023-03-17 03:59:09] [INFO ] Computed 0 place invariants in 50 ms
[2023-03-17 03:59:09] [INFO ] After 37ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-17 03:59:10] [INFO ] After 721ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-17 03:59:10] [INFO ] State equation strengthened by 14 read => feed constraints.
[2023-03-17 03:59:10] [INFO ] After 112ms SMT Verify possible using 14 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-17 03:59:11] [INFO ] After 251ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 92 ms.
[2023-03-17 03:59:11] [INFO ] After 1112ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Starting structural reductions in LTL mode, iteration 0 : 1967/1967 places, 149582/149582 transitions.
Applied a total of 0 rules in 231 ms. Remains 1967 /1967 variables (removed 0) and now considering 149582/149582 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 235 ms. Remains : 1967/1967 places, 149582/149582 transitions.
[2023-03-17 03:59:15] [INFO ] Flatten gal took : 3521 ms
[2023-03-17 03:59:18] [INFO ] Flatten gal took : 3408 ms
[2023-03-17 03:59:28] [INFO ] Input system was already deterministic with 149582 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1967/1967 places, 149582/149582 transitions.
Applied a total of 0 rules in 270 ms. Remains 1967 /1967 variables (removed 0) and now considering 149582/149582 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 276 ms. Remains : 1967/1967 places, 149582/149582 transitions.
[2023-03-17 03:59:33] [INFO ] Flatten gal took : 3672 ms
[2023-03-17 03:59:37] [INFO ] Flatten gal took : 4022 ms
[2023-03-17 03:59:47] [INFO ] Input system was already deterministic with 149582 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1967/1967 places, 149582/149582 transitions.
Graph (trivial) has 1657 edges and 1967 vertex of which 115 / 1967 are part of one of the 43 SCC in 6 ms
Free SCC test removed 72 places
Ensure Unique test removed 586 transitions
Reduce isomorphic transitions removed 586 transitions.
Graph (complete) has 143614 edges and 1895 vertex of which 1894 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.90 ms
Discarding 1 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 2 rules applied. Total rules applied 4 place count 1894 transition count 148993
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 6 place count 1892 transition count 148993
Performed 3 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 3 Pre rules applied. Total rules applied 6 place count 1892 transition count 148990
Deduced a syphon composed of 3 places in 82 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 2 with 6 rules applied. Total rules applied 12 place count 1889 transition count 148990
Discarding 6 places :
Symmetric choice reduction at 2 with 6 rule applications. Total rules 18 place count 1883 transition count 148978
Iterating global reduction 2 with 6 rules applied. Total rules applied 24 place count 1883 transition count 148978
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 2 with 6 rules applied. Total rules applied 30 place count 1883 transition count 148972
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 36 place count 1877 transition count 148960
Iterating global reduction 3 with 6 rules applied. Total rules applied 42 place count 1877 transition count 148960
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 3 with 6 rules applied. Total rules applied 48 place count 1877 transition count 148954
Discarding 3 places :
Symmetric choice reduction at 4 with 3 rule applications. Total rules 51 place count 1874 transition count 148948
Iterating global reduction 4 with 3 rules applied. Total rules applied 54 place count 1874 transition count 148948
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 4 with 3 rules applied. Total rules applied 57 place count 1874 transition count 148945
Performed 10 Post agglomeration using F-continuation condition.Transition count delta: 10
Deduced a syphon composed of 10 places in 85 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 5 with 20 rules applied. Total rules applied 77 place count 1864 transition count 148935
Applied a total of 77 rules in 5449 ms. Remains 1864 /1967 variables (removed 103) and now considering 148935/149582 (removed 647) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5457 ms. Remains : 1864/1967 places, 148935/149582 transitions.
[2023-03-17 03:59:56] [INFO ] Flatten gal took : 3124 ms
[2023-03-17 03:59:59] [INFO ] Flatten gal took : 3551 ms
[2023-03-17 04:00:07] [INFO ] Input system was already deterministic with 148935 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1967/1967 places, 149582/149582 transitions.
Applied a total of 0 rules in 225 ms. Remains 1967 /1967 variables (removed 0) and now considering 149582/149582 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 227 ms. Remains : 1967/1967 places, 149582/149582 transitions.
[2023-03-17 04:00:11] [INFO ] Flatten gal took : 3062 ms
[2023-03-17 04:00:14] [INFO ] Flatten gal took : 3538 ms
[2023-03-17 04:00:21] [INFO ] Input system was already deterministic with 149582 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1967/1967 places, 149582/149582 transitions.
Applied a total of 0 rules in 280 ms. Remains 1967 /1967 variables (removed 0) and now considering 149582/149582 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 283 ms. Remains : 1967/1967 places, 149582/149582 transitions.
[2023-03-17 04:00:26] [INFO ] Flatten gal took : 3462 ms
[2023-03-17 04:00:29] [INFO ] Flatten gal took : 3548 ms
[2023-03-17 04:00:37] [INFO ] Input system was already deterministic with 149582 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1967/1967 places, 149582/149582 transitions.
Graph (trivial) has 1663 edges and 1967 vertex of which 115 / 1967 are part of one of the 43 SCC in 5 ms
Free SCC test removed 72 places
Ensure Unique test removed 586 transitions
Reduce isomorphic transitions removed 586 transitions.
Graph (complete) has 143614 edges and 1895 vertex of which 1894 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.88 ms
Discarding 1 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 2 rules applied. Total rules applied 4 place count 1893 transition count 148992
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 6 place count 1891 transition count 148992
Performed 3 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 3 Pre rules applied. Total rules applied 6 place count 1891 transition count 148989
Deduced a syphon composed of 3 places in 69 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 2 with 6 rules applied. Total rules applied 12 place count 1888 transition count 148989
Discarding 6 places :
Symmetric choice reduction at 2 with 6 rule applications. Total rules 18 place count 1882 transition count 148977
Iterating global reduction 2 with 6 rules applied. Total rules applied 24 place count 1882 transition count 148977
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 2 with 6 rules applied. Total rules applied 30 place count 1882 transition count 148971
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 36 place count 1876 transition count 148959
Iterating global reduction 3 with 6 rules applied. Total rules applied 42 place count 1876 transition count 148959
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 3 with 6 rules applied. Total rules applied 48 place count 1876 transition count 148953
Discarding 3 places :
Symmetric choice reduction at 4 with 3 rule applications. Total rules 51 place count 1873 transition count 148947
Iterating global reduction 4 with 3 rules applied. Total rules applied 54 place count 1873 transition count 148947
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 4 with 3 rules applied. Total rules applied 57 place count 1873 transition count 148944
Performed 10 Post agglomeration using F-continuation condition.Transition count delta: 10
Deduced a syphon composed of 10 places in 62 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 5 with 20 rules applied. Total rules applied 77 place count 1863 transition count 148934
Applied a total of 77 rules in 4333 ms. Remains 1863 /1967 variables (removed 104) and now considering 148934/149582 (removed 648) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4337 ms. Remains : 1863/1967 places, 148934/149582 transitions.
[2023-03-17 04:00:45] [INFO ] Flatten gal took : 3686 ms
[2023-03-17 04:00:50] [INFO ] Flatten gal took : 4071 ms
[2023-03-17 04:00:57] [INFO ] Input system was already deterministic with 148934 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1967/1967 places, 149582/149582 transitions.
Applied a total of 0 rules in 298 ms. Remains 1967 /1967 variables (removed 0) and now considering 149582/149582 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 301 ms. Remains : 1967/1967 places, 149582/149582 transitions.
[2023-03-17 04:01:02] [INFO ] Flatten gal took : 3463 ms
[2023-03-17 04:01:06] [INFO ] Flatten gal took : 4003 ms
[2023-03-17 04:01:13] [INFO ] Input system was already deterministic with 149582 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1967/1967 places, 149582/149582 transitions.
Applied a total of 0 rules in 326 ms. Remains 1967 /1967 variables (removed 0) and now considering 149582/149582 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 331 ms. Remains : 1967/1967 places, 149582/149582 transitions.
[2023-03-17 04:01:17] [INFO ] Flatten gal took : 3126 ms
[2023-03-17 04:01:20] [INFO ] Flatten gal took : 3587 ms
[2023-03-17 04:01:28] [INFO ] Input system was already deterministic with 149582 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1967/1967 places, 149582/149582 transitions.
Applied a total of 0 rules in 236 ms. Remains 1967 /1967 variables (removed 0) and now considering 149582/149582 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 239 ms. Remains : 1967/1967 places, 149582/149582 transitions.
[2023-03-17 04:01:32] [INFO ] Flatten gal took : 3155 ms
[2023-03-17 04:01:36] [INFO ] Flatten gal took : 3966 ms
[2023-03-17 04:01:43] [INFO ] Input system was already deterministic with 149582 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1967/1967 places, 149582/149582 transitions.
Applied a total of 0 rules in 228 ms. Remains 1967 /1967 variables (removed 0) and now considering 149582/149582 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 231 ms. Remains : 1967/1967 places, 149582/149582 transitions.
[2023-03-17 04:01:47] [INFO ] Flatten gal took : 3130 ms
[2023-03-17 04:01:50] [INFO ] Flatten gal took : 3587 ms
[2023-03-17 04:01:57] [INFO ] Input system was already deterministic with 149582 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1967/1967 places, 149582/149582 transitions.
Graph (trivial) has 1657 edges and 1967 vertex of which 112 / 1967 are part of one of the 42 SCC in 5 ms
Free SCC test removed 70 places
Ensure Unique test removed 582 transitions
Reduce isomorphic transitions removed 582 transitions.
Graph (complete) has 143638 edges and 1897 vertex of which 1896 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.86 ms
Discarding 1 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 2 rules applied. Total rules applied 4 place count 1895 transition count 148996
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 6 place count 1893 transition count 148996
Performed 3 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 3 Pre rules applied. Total rules applied 6 place count 1893 transition count 148993
Deduced a syphon composed of 3 places in 57 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 2 with 6 rules applied. Total rules applied 12 place count 1890 transition count 148993
Discarding 6 places :
Symmetric choice reduction at 2 with 6 rule applications. Total rules 18 place count 1884 transition count 148981
Iterating global reduction 2 with 6 rules applied. Total rules applied 24 place count 1884 transition count 148981
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 2 with 6 rules applied. Total rules applied 30 place count 1884 transition count 148975
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 36 place count 1878 transition count 148963
Iterating global reduction 3 with 6 rules applied. Total rules applied 42 place count 1878 transition count 148963
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 3 with 6 rules applied. Total rules applied 48 place count 1878 transition count 148957
Discarding 3 places :
Symmetric choice reduction at 4 with 3 rule applications. Total rules 51 place count 1875 transition count 148951
Iterating global reduction 4 with 3 rules applied. Total rules applied 54 place count 1875 transition count 148951
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 4 with 3 rules applied. Total rules applied 57 place count 1875 transition count 148948
Performed 10 Post agglomeration using F-continuation condition.Transition count delta: 10
Deduced a syphon composed of 10 places in 60 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 5 with 20 rules applied. Total rules applied 77 place count 1865 transition count 148938
Applied a total of 77 rules in 3953 ms. Remains 1865 /1967 variables (removed 102) and now considering 148938/149582 (removed 644) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3956 ms. Remains : 1865/1967 places, 148938/149582 transitions.
[2023-03-17 04:02:05] [INFO ] Flatten gal took : 3049 ms
[2023-03-17 04:02:08] [INFO ] Flatten gal took : 3549 ms
[2023-03-17 04:02:17] [INFO ] Input system was already deterministic with 148938 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1967/1967 places, 149582/149582 transitions.
Applied a total of 0 rules in 285 ms. Remains 1967 /1967 variables (removed 0) and now considering 149582/149582 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 289 ms. Remains : 1967/1967 places, 149582/149582 transitions.
[2023-03-17 04:02:21] [INFO ] Flatten gal took : 3527 ms
[2023-03-17 04:02:25] [INFO ] Flatten gal took : 4033 ms
[2023-03-17 04:02:35] [INFO ] Input system was already deterministic with 149582 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1967/1967 places, 149582/149582 transitions.
Applied a total of 0 rules in 292 ms. Remains 1967 /1967 variables (removed 0) and now considering 149582/149582 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 296 ms. Remains : 1967/1967 places, 149582/149582 transitions.
[2023-03-17 04:02:39] [INFO ] Flatten gal took : 3482 ms
[2023-03-17 04:02:43] [INFO ] Flatten gal took : 3754 ms
[2023-03-17 04:02:52] [INFO ] Input system was already deterministic with 149582 transitions.
[2023-03-17 04:02:56] [INFO ] Flatten gal took : 3723 ms
[2023-03-17 04:03:01] [INFO ] Flatten gal took : 4368 ms
[2023-03-17 04:03:01] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2023-03-17 04:03:01] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 1967 places, 149582 transitions and 594939 arcs took 306 ms.
Total runtime 1934223 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT RERS2020-PT-pb105
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 1467168 kB
After kill :
MemTotal: 16393216 kB
MemFree: 15913552 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 372 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 377 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 382 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 387 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 392 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 397 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 402 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 407 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 412 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 417 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 422 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 427 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 432 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 437 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 442 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 447 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 452 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 457 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 462 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 467 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 472 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 477 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 482 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 487 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 492 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 497 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 502 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 507 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 512 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 517 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 522 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 527 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 532 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 537 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 542 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 547 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 552 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 557 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 562 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 567 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 572 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 577 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 582 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 587 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 592 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 597 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 602 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 607 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 612 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 617 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 622 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 627 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 632 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 637 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 642 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 647 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 652 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 657 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 662 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 667 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 672 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 677 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 682 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 687 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 692 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 697 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 702 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 707 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 712 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 717 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 722 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 727 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 732 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 737 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 742 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 747 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 752 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 757 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 762 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 767 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 404.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 772 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 777 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 782 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 787 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 792 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 797 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 802 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 807 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 812 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 817 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 822 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 827 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 832 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 837 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 842 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 847 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 852 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 857 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 862 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 867 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 872 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 877 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 882 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 887 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 892 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 897 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 902 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 907 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 912 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 917 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 922 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 927 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 932 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 937 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 942 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 947 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 952 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 957 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 962 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 967 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 972 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 977 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 982 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 987 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 992 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 997 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1002 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1007 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1012 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1017 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1022 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1027 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1032 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1037 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1042 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1047 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1052 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1058 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1063 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1068 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1073 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1078 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1083 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1088 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1093 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1098 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1103 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1108 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1113 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1118 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1123 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1128 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1133 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1138 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1143 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 376.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1148 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1153 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1158 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1163 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1168 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1173 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1178 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1183 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1188 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1193 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1198 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1203 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1208 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1213 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1218 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1223 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1228 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1233 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1238 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1243 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1248 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1253 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1258 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1263 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1268 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1273 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1278 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1283 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1288 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1293 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1298 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1303 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1308 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1313 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1318 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1323 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1328 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1333 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1338 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1343 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1348 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1353 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1358 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1363 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1368 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1373 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1378 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1383 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1388 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1393 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1398 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1403 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1408 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1413 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1418 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1423 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1428 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1433 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1438 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1443 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1448 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1453 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1458 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1463 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1468 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1473 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1478 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1483 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1488 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1493 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1498 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1503 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1508 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1513 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1518 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1523 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1528 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1533 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1538 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 395.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1543 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1548 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1553 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1558 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1563 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1568 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1573 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1578 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1583 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1588 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1593 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1598 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1603 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1608 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1613 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1618 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1623 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1628 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1633 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1638 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1643 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1648 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1653 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1658 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb105-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-02: AG 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb105-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS2020-PT-pb105-CTLFireability-15: AXAG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1663 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: caught signal Terminated - aborting LoLA

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS2020-PT-pb105-CTLFireability-00: CTL unknown AGGR
RERS2020-PT-pb105-CTLFireability-02: AG unknown AGGR
RERS2020-PT-pb105-CTLFireability-03: CTL unknown AGGR
RERS2020-PT-pb105-CTLFireability-04: CTL unknown AGGR
RERS2020-PT-pb105-CTLFireability-05: CTL unknown AGGR
RERS2020-PT-pb105-CTLFireability-06: CTL unknown AGGR
RERS2020-PT-pb105-CTLFireability-07: CTL unknown AGGR
RERS2020-PT-pb105-CTLFireability-08: CTL unknown AGGR
RERS2020-PT-pb105-CTLFireability-09: CTL unknown AGGR
RERS2020-PT-pb105-CTLFireability-10: CTL unknown AGGR
RERS2020-PT-pb105-CTLFireability-11: CTL unknown AGGR
RERS2020-PT-pb105-CTLFireability-12: DISJ unknown DISJ
RERS2020-PT-pb105-CTLFireability-13: CTL unknown AGGR
RERS2020-PT-pb105-CTLFireability-14: CONJ unknown CONJ
RERS2020-PT-pb105-CTLFireability-15: AXAG unknown AGGR


Time elapsed: 1663 secs. Pages in use: 0

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RERS2020-PT-pb105"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is RERS2020-PT-pb105, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r327-tall-167889199400250"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RERS2020-PT-pb105.tgz
mv RERS2020-PT-pb105 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;