About the Execution of LoLa+red for RERS17pb115-PT-3
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
16153.932 | 3600000.00 | 3706914.00 | 11416.40 | ????????T??????? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r327-tall-167889199200162.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is RERS17pb115-PT-3, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r327-tall-167889199200162
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 70M
-rw-r--r-- 1 mcc users 4.9K Feb 25 13:49 CTLCardinality.txt
-rw-r--r-- 1 mcc users 44K Feb 25 13:49 CTLCardinality.xml
-rw-r--r-- 1 mcc users 8.4K Feb 25 13:46 CTLFireability.txt
-rw-r--r-- 1 mcc users 64K Feb 25 13:46 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:39 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:39 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.0K Feb 25 16:39 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:39 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 25 13:57 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 106K Feb 25 13:57 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 13:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 64K Feb 25 13:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:39 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:39 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 69M Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME RERS17pb115-PT-3-CTLFireability-00
FORMULA_NAME RERS17pb115-PT-3-CTLFireability-01
FORMULA_NAME RERS17pb115-PT-3-CTLFireability-02
FORMULA_NAME RERS17pb115-PT-3-CTLFireability-03
FORMULA_NAME RERS17pb115-PT-3-CTLFireability-04
FORMULA_NAME RERS17pb115-PT-3-CTLFireability-05
FORMULA_NAME RERS17pb115-PT-3-CTLFireability-06
FORMULA_NAME RERS17pb115-PT-3-CTLFireability-07
FORMULA_NAME RERS17pb115-PT-3-CTLFireability-08
FORMULA_NAME RERS17pb115-PT-3-CTLFireability-09
FORMULA_NAME RERS17pb115-PT-3-CTLFireability-10
FORMULA_NAME RERS17pb115-PT-3-CTLFireability-11
FORMULA_NAME RERS17pb115-PT-3-CTLFireability-12
FORMULA_NAME RERS17pb115-PT-3-CTLFireability-13
FORMULA_NAME RERS17pb115-PT-3-CTLFireability-14
FORMULA_NAME RERS17pb115-PT-3-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678987673929
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RERS17pb115-PT-3
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-16 17:27:55] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-16 17:27:55] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-16 17:27:57] [INFO ] Load time of PNML (sax parser for PT used): 1818 ms
[2023-03-16 17:27:57] [INFO ] Transformed 1399 places.
[2023-03-16 17:27:58] [INFO ] Transformed 144369 transitions.
[2023-03-16 17:27:58] [INFO ] Parsed PT model containing 1399 places and 144369 transitions and 577414 arcs in 2347 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 37 ms.
Support contains 261 out of 1399 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 1399/1399 places, 144369/144369 transitions.
Ensure Unique test removed 18 places
Iterating post reduction 0 with 18 rules applied. Total rules applied 18 place count 1381 transition count 144369
Applied a total of 18 rules in 775 ms. Remains 1381 /1399 variables (removed 18) and now considering 144369/144369 (removed 0) transitions.
[2023-03-16 17:27:59] [INFO ] Flow matrix only has 81238 transitions (discarded 63131 similar events)
// Phase 1: matrix 81238 rows 1381 cols
[2023-03-16 17:28:00] [INFO ] Computed 19 place invariants in 472 ms
[2023-03-16 17:28:07] [INFO ] Implicit Places using invariants in 7979 ms returned []
Implicit Place search using SMT only with invariants took 8008 ms to find 0 implicit places.
[2023-03-16 17:28:07] [INFO ] Flow matrix only has 81238 transitions (discarded 63131 similar events)
[2023-03-16 17:28:07] [INFO ] Invariant cache hit.
[2023-03-16 17:28:38] [INFO ] Performed 88923/144369 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 17:28:56] [INFO ] Dead Transitions using invariants and state equation in 48823 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 1381/1399 places, 144369/144369 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 57635 ms. Remains : 1381/1399 places, 144369/144369 transitions.
Support contains 261 out of 1381 places after structural reductions.
[2023-03-16 17:29:01] [INFO ] Flatten gal took : 3523 ms
[2023-03-16 17:29:04] [INFO ] Flatten gal took : 3423 ms
[2023-03-16 17:29:12] [INFO ] Input system was already deterministic with 144369 transitions.
Support contains 257 out of 1381 places (down from 261) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1512 ms. (steps per millisecond=6 ) properties (out of 107) seen :10
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=27 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=31 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 124 ms. (steps per millisecond=8 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 97) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 97) seen :0
Running SMT prover for 97 properties.
[2023-03-16 17:29:16] [INFO ] Flow matrix only has 81238 transitions (discarded 63131 similar events)
[2023-03-16 17:29:16] [INFO ] Invariant cache hit.
[2023-03-16 17:29:18] [INFO ] [Real]Absence check using 19 positive place invariants in 18 ms returned sat
[2023-03-16 17:29:41] [INFO ] After 21475ms SMT Verify possible using state equation in real domain returned unsat :0 sat :18 real:79
[2023-03-16 17:29:43] [INFO ] State equation strengthened by 2277 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 17:29:43] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 17:29:43] [INFO ] After 27270ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Fused 97 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 237 out of 1381 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1381/1381 places, 144369/144369 transitions.
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 0 with 1 rules applied. Total rules applied 1 place count 1380 transition count 144368
Applied a total of 1 rules in 2415 ms. Remains 1380 /1381 variables (removed 1) and now considering 144368/144369 (removed 1) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 2419 ms. Remains : 1380/1381 places, 144368/144369 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1220 ms. (steps per millisecond=8 ) properties (out of 97) seen :4
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=30 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=31 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=31 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=31 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=31 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 34 ms. (steps per millisecond=29 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=30 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=31 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 93) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 93) seen :0
Interrupted probabilistic random walk after 6300 steps, run timeout after 6005 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 6300 steps, saw 5417 distinct states, run finished after 6006 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 93 properties.
[2023-03-16 17:29:55] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
// Phase 1: matrix 81237 rows 1380 cols
[2023-03-16 17:29:55] [INFO ] Computed 19 place invariants in 274 ms
[2023-03-16 17:29:57] [INFO ] [Real]Absence check using 19 positive place invariants in 16 ms returned sat
[2023-03-16 17:30:20] [INFO ] After 21389ms SMT Verify possible using state equation in real domain returned unsat :0 sat :53 real:40
[2023-03-16 17:30:20] [INFO ] State equation strengthened by 741 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 17:30:21] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 17:30:21] [INFO ] After 25672ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Fused 93 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 233 out of 1380 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1380/1380 places, 144368/144368 transitions.
Applied a total of 0 rules in 866 ms. Remains 1380 /1380 variables (removed 0) and now considering 144368/144368 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 866 ms. Remains : 1380/1380 places, 144368/144368 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1109 ms. (steps per millisecond=9 ) properties (out of 93) seen :3
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=31 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 71 ms. (steps per millisecond=14 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 90) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 90) seen :0
Interrupted probabilistic random walk after 5788 steps, run timeout after 6003 ms. (steps per millisecond=0 ) properties seen :{}
Probabilistic random walk after 5788 steps, saw 4977 distinct states, run finished after 6003 ms. (steps per millisecond=0 ) properties seen :0
Running SMT prover for 90 properties.
[2023-03-16 17:30:30] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 17:30:30] [INFO ] Invariant cache hit.
[2023-03-16 17:30:33] [INFO ] [Real]Absence check using 19 positive place invariants in 16 ms returned sat
[2023-03-16 17:30:55] [INFO ] After 21534ms SMT Verify possible using state equation in real domain returned unsat :0 sat :19 real:71
[2023-03-16 17:30:56] [INFO ] State equation strengthened by 741 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 17:30:56] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 17:30:56] [INFO ] After 26248ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Fused 90 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 227 out of 1380 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1380/1380 places, 144368/144368 transitions.
Applied a total of 0 rules in 1276 ms. Remains 1380 /1380 variables (removed 0) and now considering 144368/144368 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1276 ms. Remains : 1380/1380 places, 144368/144368 transitions.
[2023-03-16 17:31:02] [INFO ] Flatten gal took : 2992 ms
[2023-03-16 17:31:05] [INFO ] Flatten gal took : 3145 ms
[2023-03-16 17:31:11] [INFO ] Input system was already deterministic with 144369 transitions.
Computed a total of 1 stabilizing places and 1 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 1381/1381 places, 144369/144369 transitions.
Applied a total of 0 rules in 444 ms. Remains 1381 /1381 variables (removed 0) and now considering 144369/144369 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 449 ms. Remains : 1381/1381 places, 144369/144369 transitions.
[2023-03-16 17:31:16] [INFO ] Flatten gal took : 3076 ms
[2023-03-16 17:31:19] [INFO ] Flatten gal took : 3694 ms
[2023-03-16 17:31:27] [INFO ] Input system was already deterministic with 144369 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1381/1381 places, 144369/144369 transitions.
Applied a total of 0 rules in 458 ms. Remains 1381 /1381 variables (removed 0) and now considering 144369/144369 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 461 ms. Remains : 1381/1381 places, 144369/144369 transitions.
[2023-03-16 17:31:31] [INFO ] Flatten gal took : 2968 ms
[2023-03-16 17:31:34] [INFO ] Flatten gal took : 3392 ms
[2023-03-16 17:31:41] [INFO ] Input system was already deterministic with 144369 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1381/1381 places, 144369/144369 transitions.
Applied a total of 0 rules in 424 ms. Remains 1381 /1381 variables (removed 0) and now considering 144369/144369 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 426 ms. Remains : 1381/1381 places, 144369/144369 transitions.
[2023-03-16 17:31:46] [INFO ] Flatten gal took : 3291 ms
[2023-03-16 17:31:49] [INFO ] Flatten gal took : 3599 ms
[2023-03-16 17:31:57] [INFO ] Input system was already deterministic with 144369 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1381/1381 places, 144369/144369 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 1169 ms. Remains 1380 /1381 variables (removed 1) and now considering 144368/144369 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1174 ms. Remains : 1380/1381 places, 144368/144369 transitions.
[2023-03-16 17:32:02] [INFO ] Flatten gal took : 3023 ms
[2023-03-16 17:32:05] [INFO ] Flatten gal took : 3407 ms
[2023-03-16 17:32:12] [INFO ] Input system was already deterministic with 144368 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1381/1381 places, 144369/144369 transitions.
Applied a total of 0 rules in 613 ms. Remains 1381 /1381 variables (removed 0) and now considering 144369/144369 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 619 ms. Remains : 1381/1381 places, 144369/144369 transitions.
[2023-03-16 17:32:17] [INFO ] Flatten gal took : 2975 ms
[2023-03-16 17:32:20] [INFO ] Flatten gal took : 3312 ms
[2023-03-16 17:32:27] [INFO ] Input system was already deterministic with 144369 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1381/1381 places, 144369/144369 transitions.
Applied a total of 0 rules in 426 ms. Remains 1381 /1381 variables (removed 0) and now considering 144369/144369 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 434 ms. Remains : 1381/1381 places, 144369/144369 transitions.
[2023-03-16 17:32:31] [INFO ] Flatten gal took : 2947 ms
[2023-03-16 17:32:34] [INFO ] Flatten gal took : 3538 ms
[2023-03-16 17:32:42] [INFO ] Input system was already deterministic with 144369 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1381/1381 places, 144369/144369 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 920 ms. Remains 1380 /1381 variables (removed 1) and now considering 144368/144369 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 926 ms. Remains : 1380/1381 places, 144368/144369 transitions.
[2023-03-16 17:32:46] [INFO ] Flatten gal took : 2910 ms
[2023-03-16 17:32:49] [INFO ] Flatten gal took : 3405 ms
[2023-03-16 17:32:57] [INFO ] Input system was already deterministic with 144368 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1381/1381 places, 144369/144369 transitions.
Applied a total of 0 rules in 421 ms. Remains 1381 /1381 variables (removed 0) and now considering 144369/144369 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 424 ms. Remains : 1381/1381 places, 144369/144369 transitions.
[2023-03-16 17:33:01] [INFO ] Flatten gal took : 2945 ms
[2023-03-16 17:33:04] [INFO ] Flatten gal took : 3444 ms
[2023-03-16 17:33:11] [INFO ] Input system was already deterministic with 144369 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1381/1381 places, 144369/144369 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 916 ms. Remains 1380 /1381 variables (removed 1) and now considering 144368/144369 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 920 ms. Remains : 1380/1381 places, 144368/144369 transitions.
[2023-03-16 17:33:15] [INFO ] Flatten gal took : 2989 ms
[2023-03-16 17:33:19] [INFO ] Flatten gal took : 3511 ms
[2023-03-16 17:33:26] [INFO ] Input system was already deterministic with 144368 transitions.
Finished random walk after 385 steps, including 0 resets, run visited all 1 properties in 20 ms. (steps per millisecond=19 )
FORMULA RERS17pb115-PT-3-CTLFireability-08 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 1381/1381 places, 144369/144369 transitions.
Applied a total of 0 rules in 426 ms. Remains 1381 /1381 variables (removed 0) and now considering 144369/144369 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 430 ms. Remains : 1381/1381 places, 144369/144369 transitions.
[2023-03-16 17:33:30] [INFO ] Flatten gal took : 2932 ms
[2023-03-16 17:33:33] [INFO ] Flatten gal took : 3608 ms
[2023-03-16 17:33:40] [INFO ] Input system was already deterministic with 144369 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1381/1381 places, 144369/144369 transitions.
Applied a total of 0 rules in 433 ms. Remains 1381 /1381 variables (removed 0) and now considering 144369/144369 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 438 ms. Remains : 1381/1381 places, 144369/144369 transitions.
[2023-03-16 17:33:44] [INFO ] Flatten gal took : 3015 ms
[2023-03-16 17:33:48] [INFO ] Flatten gal took : 3526 ms
[2023-03-16 17:33:54] [INFO ] Input system was already deterministic with 144369 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1381/1381 places, 144369/144369 transitions.
Applied a total of 0 rules in 423 ms. Remains 1381 /1381 variables (removed 0) and now considering 144369/144369 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 426 ms. Remains : 1381/1381 places, 144369/144369 transitions.
[2023-03-16 17:33:58] [INFO ] Flatten gal took : 2932 ms
[2023-03-16 17:34:02] [INFO ] Flatten gal took : 3455 ms
[2023-03-16 17:34:09] [INFO ] Input system was already deterministic with 144369 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1381/1381 places, 144369/144369 transitions.
Applied a total of 0 rules in 438 ms. Remains 1381 /1381 variables (removed 0) and now considering 144369/144369 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 441 ms. Remains : 1381/1381 places, 144369/144369 transitions.
[2023-03-16 17:34:12] [INFO ] Flatten gal took : 2910 ms
[2023-03-16 17:34:16] [INFO ] Flatten gal took : 3507 ms
[2023-03-16 17:34:23] [INFO ] Input system was already deterministic with 144369 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1381/1381 places, 144369/144369 transitions.
Applied a total of 0 rules in 404 ms. Remains 1381 /1381 variables (removed 0) and now considering 144369/144369 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 408 ms. Remains : 1381/1381 places, 144369/144369 transitions.
[2023-03-16 17:34:27] [INFO ] Flatten gal took : 2859 ms
[2023-03-16 17:34:30] [INFO ] Flatten gal took : 3383 ms
[2023-03-16 17:34:37] [INFO ] Input system was already deterministic with 144369 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1381/1381 places, 144369/144369 transitions.
Applied a total of 0 rules in 494 ms. Remains 1381 /1381 variables (removed 0) and now considering 144369/144369 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 497 ms. Remains : 1381/1381 places, 144369/144369 transitions.
[2023-03-16 17:34:41] [INFO ] Flatten gal took : 3094 ms
[2023-03-16 17:34:45] [INFO ] Flatten gal took : 3584 ms
[2023-03-16 17:34:52] [INFO ] Input system was already deterministic with 144369 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1381/1381 places, 144369/144369 transitions.
Applied a total of 0 rules in 434 ms. Remains 1381 /1381 variables (removed 0) and now considering 144369/144369 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 437 ms. Remains : 1381/1381 places, 144369/144369 transitions.
[2023-03-16 17:34:56] [INFO ] Flatten gal took : 3213 ms
[2023-03-16 17:34:59] [INFO ] Flatten gal took : 3576 ms
[2023-03-16 17:35:06] [INFO ] Input system was already deterministic with 144369 transitions.
[2023-03-16 17:35:10] [INFO ] Flatten gal took : 3142 ms
[2023-03-16 17:35:13] [INFO ] Flatten gal took : 3487 ms
[2023-03-16 17:35:13] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-16 17:35:13] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 1381 places, 144369 transitions and 577396 arcs took 296 ms.
Total runtime 438270 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT RERS17pb115-PT-3
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 163748 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16272264 kB
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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RERS17pb115-PT-3-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-3-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-3-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-3-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-3-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-3-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-3-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-3-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-3-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-3-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-3-CTLFireability-11: CONJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-3-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-3-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-3-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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RERS17pb115-PT-3-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
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RERS17pb115-PT-3-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-3-CTLFireability-11: CONJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-3-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-3-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-3-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RERS17pb115-PT-3"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is RERS17pb115-PT-3, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r327-tall-167889199200162"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/RERS17pb115-PT-3.tgz
mv RERS17pb115-PT-3 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;