Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r327-tall-167889199200147.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is RERS17pb115-PT-1, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r327-tall-167889199200147
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 70M
-rw-r--r-- 1 mcc users 7.7K Feb 25 13:51 CTLCardinality.txt
-rw-r--r-- 1 mcc users 80K Feb 25 13:51 CTLCardinality.xml
-rw-r--r-- 1 mcc users 8.7K Feb 25 13:48 CTLFireability.txt
-rw-r--r-- 1 mcc users 67K Feb 25 13:48 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 16:39 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Feb 25 16:39 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Feb 25 16:39 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 16:39 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 13:59 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 139K Feb 25 13:59 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.6K Feb 25 13:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 52K Feb 25 13:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:39 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:39 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 69M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RERS17pb115-PT-1-LTLCardinality-00
FORMULA_NAME RERS17pb115-PT-1-LTLCardinality-01
FORMULA_NAME RERS17pb115-PT-1-LTLCardinality-02
FORMULA_NAME RERS17pb115-PT-1-LTLCardinality-03
FORMULA_NAME RERS17pb115-PT-1-LTLCardinality-04
FORMULA_NAME RERS17pb115-PT-1-LTLCardinality-05
FORMULA_NAME RERS17pb115-PT-1-LTLCardinality-06
FORMULA_NAME RERS17pb115-PT-1-LTLCardinality-07
FORMULA_NAME RERS17pb115-PT-1-LTLCardinality-08
FORMULA_NAME RERS17pb115-PT-1-LTLCardinality-09
FORMULA_NAME RERS17pb115-PT-1-LTLCardinality-10
FORMULA_NAME RERS17pb115-PT-1-LTLCardinality-11
FORMULA_NAME RERS17pb115-PT-1-LTLCardinality-12
FORMULA_NAME RERS17pb115-PT-1-LTLCardinality-13
FORMULA_NAME RERS17pb115-PT-1-LTLCardinality-14
FORMULA_NAME RERS17pb115-PT-1-LTLCardinality-15

=== Now, execution of the tool begins

BK_START 1678981582476

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=LTLCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RERS17pb115-PT-1
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-16 15:46:24] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLCardinality, -timeout, 360, -rebuildPNML]
[2023-03-16 15:46:24] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-16 15:46:26] [INFO ] Load time of PNML (sax parser for PT used): 1883 ms
[2023-03-16 15:46:26] [INFO ] Transformed 1399 places.
[2023-03-16 15:46:26] [INFO ] Transformed 144369 transitions.
[2023-03-16 15:46:26] [INFO ] Found NUPN structural information;
[2023-03-16 15:46:26] [INFO ] Parsed PT model containing 1399 places and 144369 transitions and 577414 arcs in 2495 ms.
Parsed 16 properties from file /home/mcc/execution/LTLCardinality.xml in 8 ms.
Working with output stream class java.io.PrintStream
Initial state reduction rules removed 5 formulas.
FORMULA RERS17pb115-PT-1-LTLCardinality-02 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA RERS17pb115-PT-1-LTLCardinality-04 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA RERS17pb115-PT-1-LTLCardinality-06 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA RERS17pb115-PT-1-LTLCardinality-08 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA RERS17pb115-PT-1-LTLCardinality-10 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA RERS17pb115-PT-1-LTLCardinality-12 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA RERS17pb115-PT-1-LTLCardinality-05 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 27 out of 1399 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 1399/1399 places, 144369/144369 transitions.
Ensure Unique test removed 18 places
Iterating post reduction 0 with 18 rules applied. Total rules applied 18 place count 1381 transition count 144369
Applied a total of 18 rules in 931 ms. Remains 1381 /1399 variables (removed 18) and now considering 144369/144369 (removed 0) transitions.
[2023-03-16 15:46:28] [INFO ] Flow matrix only has 81238 transitions (discarded 63131 similar events)
// Phase 1: matrix 81238 rows 1381 cols
[2023-03-16 15:46:29] [INFO ] Computed 19 place invariants in 418 ms
[2023-03-16 15:46:38] [INFO ] Implicit Places using invariants in 9709 ms returned []
Implicit Place search using SMT only with invariants took 9734 ms to find 0 implicit places.
[2023-03-16 15:46:38] [INFO ] Flow matrix only has 81238 transitions (discarded 63131 similar events)
[2023-03-16 15:46:38] [INFO ] Invariant cache hit.
[2023-03-16 15:47:08] [INFO ] Performed 87461/144369 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 15:47:27] [INFO ] Dead Transitions using invariants and state equation in 49230 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 1381/1399 places, 144369/144369 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 59914 ms. Remains : 1381/1399 places, 144369/144369 transitions.
Support contains 27 out of 1381 places after structural reductions.
[2023-03-16 15:47:32] [INFO ] Flatten gal took : 3661 ms
[2023-03-16 15:47:35] [INFO ] Flatten gal took : 3436 ms
[2023-03-16 15:47:42] [INFO ] Input system was already deterministic with 144369 transitions.
Finished random walk after 4302 steps, including 1 resets, run visited all 16 properties in 540 ms. (steps per millisecond=7 )
FORMULA RERS17pb115-PT-1-LTLCardinality-11 FALSE TECHNIQUES REACHABILITY_KNOWLEDGE
Computed a total of 1 stabilizing places and 1 stable transitions
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!(G(F(p0)))'
Support contains 1 out of 1381 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 1381/1381 places, 144369/144369 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 1302 ms. Remains 1380 /1381 variables (removed 1) and now considering 144368/144369 (removed 1) transitions.
[2023-03-16 15:47:45] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
// Phase 1: matrix 81237 rows 1380 cols
[2023-03-16 15:47:46] [INFO ] Computed 19 place invariants in 321 ms
[2023-03-16 15:47:55] [INFO ] Implicit Places using invariants in 9390 ms returned []
Implicit Place search using SMT only with invariants took 9391 ms to find 0 implicit places.
[2023-03-16 15:47:55] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 15:47:55] [INFO ] Invariant cache hit.
[2023-03-16 15:48:25] [INFO ] Performed 83206/144368 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 15:48:47] [INFO ] Dead Transitions using invariants and state equation in 51949 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 62648 ms. Remains : 1380/1381 places, 144368/144369 transitions.
Stuttering acceptance computed with spot in 220 ms :[(NOT p0), (NOT p0)]
Running random walk in product with property : RERS17pb115-PT-1-LTLCardinality-00 automaton TGBA Formula[mat=[[{ cond=true, acceptance={} source=0 dest: 0}, { cond=(NOT p0), acceptance={} source=0 dest: 1}], [{ cond=(NOT p0), acceptance={0} source=1 dest: 1}]], initial=0, aps=[p0:(EQ s31 1)], nbAcceptance=1, properties=[trans-labels, explicit-labels, trans-acc, no-univ-branch, stutter-invariant, very-weak, weak, inherently-weak], stateDesc=[null, null][true, true]]
Product exploration timeout after 94810 steps with 210 reset in 10001 ms.
Product exploration explored 100000 steps with 211 reset in 9999 ms.
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Knowledge obtained : [(NOT p0), (X (NOT p0)), (X (X (NOT p0)))]
False Knowledge obtained : []
Knowledge based reduction with 3 factoid took 132 ms. Reduced automaton from 2 states, 3 edges and 1 AP (stutter insensitive) to 2 states, 3 edges and 1 AP (stutter insensitive).
Stuttering acceptance computed with spot in 90 ms :[(NOT p0), (NOT p0)]
Finished random walk after 156 steps, including 0 resets, run visited all 1 properties in 22 ms. (steps per millisecond=7 )
Knowledge obtained : [(NOT p0), (X (NOT p0)), (X (X (NOT p0)))]
False Knowledge obtained : [(F p0)]
Knowledge based reduction with 3 factoid took 141 ms. Reduced automaton from 2 states, 3 edges and 1 AP (stutter insensitive) to 2 states, 3 edges and 1 AP (stutter insensitive).
Stuttering acceptance computed with spot in 75 ms :[(NOT p0), (NOT p0)]
Stuttering acceptance computed with spot in 69 ms :[(NOT p0), (NOT p0)]
[2023-03-16 15:49:09] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 15:49:09] [INFO ] Invariant cache hit.
Could not prove EG (NOT p0)
Support contains 1 out of 1380 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 1380/1380 places, 144368/144368 transitions.
Applied a total of 0 rules in 1009 ms. Remains 1380 /1380 variables (removed 0) and now considering 144368/144368 (removed 0) transitions.
[2023-03-16 15:49:26] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 15:49:26] [INFO ] Invariant cache hit.
[2023-03-16 15:49:34] [INFO ] Implicit Places using invariants in 8278 ms returned []
Implicit Place search using SMT only with invariants took 8282 ms to find 0 implicit places.
[2023-03-16 15:49:34] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 15:49:34] [INFO ] Invariant cache hit.
[2023-03-16 15:50:04] [INFO ] Performed 90240/144368 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 15:50:22] [INFO ] Dead Transitions using invariants and state equation in 48313 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 57615 ms. Remains : 1380/1380 places, 144368/144368 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Knowledge obtained : [(NOT p0), (X (NOT p0)), (X (X (NOT p0)))]
False Knowledge obtained : []
Knowledge based reduction with 3 factoid took 130 ms. Reduced automaton from 2 states, 3 edges and 1 AP (stutter insensitive) to 2 states, 3 edges and 1 AP (stutter insensitive).
Stuttering acceptance computed with spot in 76 ms :[(NOT p0), (NOT p0)]
Finished random walk after 1085 steps, including 0 resets, run visited all 1 properties in 110 ms. (steps per millisecond=9 )
Knowledge obtained : [(NOT p0), (X (NOT p0)), (X (X (NOT p0)))]
False Knowledge obtained : [(F p0)]
Knowledge based reduction with 3 factoid took 231 ms. Reduced automaton from 2 states, 3 edges and 1 AP (stutter insensitive) to 2 states, 3 edges and 1 AP (stutter insensitive).
Stuttering acceptance computed with spot in 63 ms :[(NOT p0), (NOT p0)]
Stuttering acceptance computed with spot in 62 ms :[(NOT p0), (NOT p0)]
[2023-03-16 15:50:24] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 15:50:24] [INFO ] Invariant cache hit.
Could not prove EG (NOT p0)
Stuttering acceptance computed with spot in 83 ms :[(NOT p0), (NOT p0)]
Product exploration explored 100000 steps with 222 reset in 8298 ms.
Product exploration explored 100000 steps with 186 reset in 8171 ms.
Support contains 1 out of 1380 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 1380/1380 places, 144368/144368 transitions.
Applied a total of 0 rules in 841 ms. Remains 1380 /1380 variables (removed 0) and now considering 144368/144368 (removed 0) transitions.
[2023-03-16 15:50:57] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 15:50:57] [INFO ] Invariant cache hit.
[2023-03-16 15:51:05] [INFO ] Implicit Places using invariants in 8234 ms returned []
Implicit Place search using SMT only with invariants took 8239 ms to find 0 implicit places.
[2023-03-16 15:51:05] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 15:51:05] [INFO ] Invariant cache hit.
[2023-03-16 15:51:35] [INFO ] Performed 89644/144368 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 15:51:54] [INFO ] Dead Transitions using invariants and state equation in 48353 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 57439 ms. Remains : 1380/1380 places, 144368/144368 transitions.
Treatment of property RERS17pb115-PT-1-LTLCardinality-00 finished in 255412 ms.
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!((X(((X(p1)&&G(!p2))||p0)) U p3))'
Support contains 5 out of 1381 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 1381/1381 places, 144369/144369 transitions.
Applied a total of 0 rules in 479 ms. Remains 1381 /1381 variables (removed 0) and now considering 144369/144369 (removed 0) transitions.
[2023-03-16 15:52:00] [INFO ] Flow matrix only has 81238 transitions (discarded 63131 similar events)
// Phase 1: matrix 81238 rows 1381 cols
[2023-03-16 15:52:00] [INFO ] Computed 19 place invariants in 390 ms
[2023-03-16 15:52:09] [INFO ] Implicit Places using invariants in 9087 ms returned []
Implicit Place search using SMT only with invariants took 9089 ms to find 0 implicit places.
[2023-03-16 15:52:09] [INFO ] Flow matrix only has 81238 transitions (discarded 63131 similar events)
[2023-03-16 15:52:09] [INFO ] Invariant cache hit.
[2023-03-16 15:52:39] [INFO ] Performed 86655/144369 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 15:52:59] [INFO ] Dead Transitions using invariants and state equation in 49769 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 59348 ms. Remains : 1381/1381 places, 144369/144369 transitions.
Stuttering acceptance computed with spot in 210 ms :[(NOT p3), (OR (NOT p3) (AND (NOT p0) (NOT p1)) (AND (NOT p0) p2)), true, (AND (NOT p2) (NOT p1)), p2]
Running random walk in product with property : RERS17pb115-PT-1-LTLCardinality-01 automaton TGBA Formula[mat=[[{ cond=(NOT p3), acceptance={} source=0 dest: 1}], [{ cond=(OR (AND (NOT p3) p0) (AND (NOT p3) (NOT p2))), acceptance={0} source=1 dest: 1}, { cond=(AND (NOT p0) p2), acceptance={0} source=1 dest: 2}, { cond=(AND (NOT p0) (NOT p2)), acceptance={0} source=1 dest: 3}, { cond=(AND (NOT p0) (NOT p2)), acceptance={0} source=1 dest: 4}], [{ cond=true, acceptance={0} source=2 dest: 2}], [{ cond=(AND (NOT p2) (NOT p1)), acceptance={} source=3 dest: 2}], [{ cond=p2, acceptance={} source=4 dest: 2}, { cond=(NOT p2), acceptance={} source=4 dest: 4}]], initial=0, aps=[p3:(EQ s264 1), p0:(OR (EQ s746 0) (EQ s704 1)), p2:(OR (EQ s718 0) (EQ s560 1)), p1:(OR (EQ s746 0) (EQ s704 1))], nbAcceptance=1, properties=[trans-labels, explicit-labels, trans-acc, no-univ-branch, stutter-sensitive, very-weak, weak, inherently-weak], stateDesc=[null, null, null, null, null][false, false, false, false, false]]
Product exploration explored 100000 steps with 85 reset in 9129 ms.
Product exploration explored 100000 steps with 99 reset in 8508 ms.
Computed a total of 1 stabilizing places and 1 stable transitions
Computed a total of 1 stabilizing places and 1 stable transitions
Knowledge obtained : [(AND (NOT p3) (NOT p0) p2 (NOT p1)), (X (NOT (AND (NOT p0) p2))), (X (OR (AND (NOT p3) p0) (AND (NOT p3) (NOT p2)))), (X (NOT (AND (NOT p0) (NOT p2)))), (X (X p2)), (X (X (NOT (AND (NOT p0) p2)))), true, (X (X (NOT (AND (NOT p2) (NOT p1))))), (X (X (OR (AND (NOT p3) p0) (AND (NOT p3) (NOT p2))))), (X (X (NOT (AND (NOT p0) (NOT p2)))))]
False Knowledge obtained : []
Knowledge based reduction with 10 factoid took 453 ms. Reduced automaton from 5 states, 9 edges and 4 AP (stutter sensitive) to 5 states, 9 edges and 4 AP (stutter sensitive).
Stuttering acceptance computed with spot in 165 ms :[(OR (NOT p3) (AND (NOT p0) (NOT p1)) (AND (NOT p0) p2)), (OR (NOT p3) (AND (NOT p0) (NOT p1)) (AND (NOT p0) p2)), true, (AND (NOT p2) (NOT p1)), p2]
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1024 ms. (steps per millisecond=9 ) properties (out of 5) seen :3
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 111 ms. (steps per millisecond=90 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 112 ms. (steps per millisecond=89 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-16 15:53:20] [INFO ] Flow matrix only has 81238 transitions (discarded 63131 similar events)
[2023-03-16 15:53:20] [INFO ] Invariant cache hit.
[2023-03-16 15:53:20] [INFO ] [Real]Absence check using 19 positive place invariants in 20 ms returned sat
[2023-03-16 15:53:20] [INFO ] After 282ms SMT Verify possible using all constraints in real domain returned unsat :2 sat :0
Fused 2 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Found 2 invariant AP formulas.
Knowledge obtained : [(AND (NOT p3) (NOT p0) p2 (NOT p1)), (X (NOT (AND (NOT p0) p2))), (X (OR (AND (NOT p3) p0) (AND (NOT p3) (NOT p2)))), (X (NOT (AND (NOT p0) (NOT p2)))), (X (X p2)), (X (X (NOT (AND (NOT p0) p2)))), true, (X (X (NOT (AND (NOT p2) (NOT p1))))), (X (X (OR (AND (NOT p3) p0) (AND (NOT p3) (NOT p2))))), (X (X (NOT (AND (NOT p0) (NOT p2))))), (G (NOT (AND (NOT p1) (NOT p2)))), (G (NOT (AND (NOT p0) (NOT p2))))]
False Knowledge obtained : [(F (NOT p2)), (F (OR (AND (NOT p3) p0) (AND (NOT p3) (NOT p2)))), (F (NOT (AND (NOT p0) p2)))]
Knowledge based reduction with 12 factoid took 558 ms. Reduced automaton from 5 states, 9 edges and 4 AP (stutter sensitive) to 3 states, 4 edges and 2 AP (stutter sensitive).
Stuttering acceptance computed with spot in 75 ms :[(OR (NOT p0) (NOT p3)), (OR (NOT p0) (NOT p3)), true]
Stuttering acceptance computed with spot in 73 ms :[(OR (NOT p0) (NOT p3)), (OR (NOT p0) (NOT p3)), true]
[2023-03-16 15:53:21] [INFO ] Flow matrix only has 81238 transitions (discarded 63131 similar events)
[2023-03-16 15:53:21] [INFO ] Invariant cache hit.
Could not prove EG (NOT p0)
[2023-03-16 15:53:36] [INFO ] Flow matrix only has 81238 transitions (discarded 63131 similar events)
[2023-03-16 15:53:37] [INFO ] Invariant cache hit.
Could not prove EG (NOT p3)
Support contains 3 out of 1381 places. Attempting structural reductions.
Property had overlarge support with respect to TGBA, discarding it for now.
Starting structural reductions in LTL mode, iteration 0 : 1381/1381 places, 144369/144369 transitions.
Applied a total of 0 rules in 425 ms. Remains 1381 /1381 variables (removed 0) and now considering 144369/144369 (removed 0) transitions.
[2023-03-16 15:53:52] [INFO ] Flow matrix only has 81238 transitions (discarded 63131 similar events)
[2023-03-16 15:53:52] [INFO ] Invariant cache hit.
[2023-03-16 15:54:00] [INFO ] Implicit Places using invariants in 8138 ms returned []
Implicit Place search using SMT only with invariants took 8140 ms to find 0 implicit places.
[2023-03-16 15:54:01] [INFO ] Flow matrix only has 81238 transitions (discarded 63131 similar events)
[2023-03-16 15:54:01] [INFO ] Invariant cache hit.
[2023-03-16 15:54:31] [INFO ] Performed 88726/144369 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 15:54:50] [INFO ] Dead Transitions using invariants and state equation in 49508 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 58078 ms. Remains : 1381/1381 places, 144369/144369 transitions.
Computed a total of 1 stabilizing places and 1 stable transitions
Computed a total of 1 stabilizing places and 1 stable transitions
Knowledge obtained : [(AND (NOT p3) (NOT p0)), (X (AND (NOT p3) p0)), (X p0), (X (X (AND (NOT p3) p0))), true, (X (X p0))]
False Knowledge obtained : []
Knowledge based reduction with 6 factoid took 231 ms. Reduced automaton from 3 states, 4 edges and 2 AP (stutter sensitive) to 3 states, 4 edges and 2 AP (stutter sensitive).
Stuttering acceptance computed with spot in 84 ms :[(OR (NOT p0) (NOT p3)), (OR (NOT p0) (NOT p3)), true]
Finished random walk after 1 steps, including 0 resets, run visited all 2 properties in 5 ms. (steps per millisecond=0 )
Knowledge obtained : [(AND (NOT p3) (NOT p0)), (X (AND (NOT p3) p0)), (X p0), (X (X (AND (NOT p3) p0))), true, (X (X p0))]
False Knowledge obtained : [(F (AND (NOT p3) p0)), (F p0)]
Knowledge based reduction with 6 factoid took 418 ms. Reduced automaton from 3 states, 4 edges and 2 AP (stutter sensitive) to 3 states, 4 edges and 2 AP (stutter sensitive).
Stuttering acceptance computed with spot in 96 ms :[(OR (NOT p0) (NOT p3)), (OR (NOT p0) (NOT p3)), true]
Stuttering acceptance computed with spot in 83 ms :[(OR (NOT p0) (NOT p3)), (OR (NOT p0) (NOT p3)), true]
[2023-03-16 15:54:52] [INFO ] Flow matrix only has 81238 transitions (discarded 63131 similar events)
[2023-03-16 15:54:53] [INFO ] Invariant cache hit.
Could not prove EG (NOT p0)
[2023-03-16 15:55:08] [INFO ] Flow matrix only has 81238 transitions (discarded 63131 similar events)
[2023-03-16 15:55:08] [INFO ] Invariant cache hit.
Could not prove EG (NOT p3)
Stuttering acceptance computed with spot in 94 ms :[(OR (NOT p0) (NOT p3)), (OR (NOT p0) (NOT p3)), true]
Product exploration explored 100000 steps with 81 reset in 8540 ms.
Product exploration explored 100000 steps with 84 reset in 8712 ms.
Applying partial POR strategy [true, false, true]
Stuttering acceptance computed with spot in 96 ms :[(OR (NOT p0) (NOT p3)), (OR (NOT p0) (NOT p3)), true]
Support contains 3 out of 1381 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 1381/1381 places, 144369/144369 transitions.
Applied a total of 0 rules in 1046 ms. Remains 1381 /1381 variables (removed 0) and now considering 144369/144369 (removed 0) transitions.
[2023-03-16 15:55:42] [INFO ] Flow matrix only has 81238 transitions (discarded 63131 similar events)
[2023-03-16 15:55:42] [INFO ] Invariant cache hit.
[2023-03-16 15:56:12] [INFO ] Performed 90005/144369 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 15:56:30] [INFO ] Dead Transitions using invariants and state equation in 48239 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 49289 ms. Remains : 1381/1381 places, 144369/144369 transitions.
Support contains 3 out of 1381 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 1381/1381 places, 144369/144369 transitions.
Applied a total of 0 rules in 444 ms. Remains 1381 /1381 variables (removed 0) and now considering 144369/144369 (removed 0) transitions.
[2023-03-16 15:56:31] [INFO ] Flow matrix only has 81238 transitions (discarded 63131 similar events)
[2023-03-16 15:56:31] [INFO ] Invariant cache hit.
[2023-03-16 15:56:39] [INFO ] Implicit Places using invariants in 8904 ms returned []
Implicit Place search using SMT only with invariants took 8905 ms to find 0 implicit places.
[2023-03-16 15:56:39] [INFO ] Flow matrix only has 81238 transitions (discarded 63131 similar events)
[2023-03-16 15:56:40] [INFO ] Invariant cache hit.
[2023-03-16 15:57:10] [INFO ] Performed 90519/144369 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 15:57:27] [INFO ] Dead Transitions using invariants and state equation in 48021 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 57374 ms. Remains : 1381/1381 places, 144369/144369 transitions.
Treatment of property RERS17pb115-PT-1-LTLCardinality-01 finished in 333327 ms.
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!((G(p0)||F(G(p1))))'
Support contains 3 out of 1381 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 1381/1381 places, 144369/144369 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 1109 ms. Remains 1380 /1381 variables (removed 1) and now considering 144368/144369 (removed 1) transitions.
[2023-03-16 15:57:34] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
// Phase 1: matrix 81237 rows 1380 cols
[2023-03-16 15:57:34] [INFO ] Computed 19 place invariants in 298 ms
[2023-03-16 15:57:42] [INFO ] Implicit Places using invariants in 8419 ms returned []
Implicit Place search using SMT only with invariants took 8423 ms to find 0 implicit places.
[2023-03-16 15:57:42] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 15:57:42] [INFO ] Invariant cache hit.
[2023-03-16 15:58:13] [INFO ] Performed 83324/144368 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 15:58:35] [INFO ] Dead Transitions using invariants and state equation in 52255 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 61792 ms. Remains : 1380/1381 places, 144368/144369 transitions.
Stuttering acceptance computed with spot in 74 ms :[(AND (NOT p0) (NOT p1)), (NOT p1)]
Running random walk in product with property : RERS17pb115-PT-1-LTLCardinality-03 automaton TGBA Formula[mat=[[{ cond=p0, acceptance={} source=0 dest: 0}, { cond=(NOT p0), acceptance={} source=0 dest: 1}], [{ cond=p1, acceptance={} source=1 dest: 1}, { cond=(NOT p1), acceptance={0} source=1 dest: 1}]], initial=0, aps=[p0:(OR (EQ s1220 0) (EQ s122 1)), p1:(EQ s366 1)], nbAcceptance=1, properties=[trans-labels, explicit-labels, trans-acc, complete, deterministic, no-univ-branch, unambiguous, semi-deterministic, stutter-invariant], stateDesc=[null, null][true, true]]
Product exploration explored 100000 steps with 0 reset in 8892 ms.
Product exploration explored 100000 steps with 0 reset in 8811 ms.
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Knowledge obtained : [(AND p0 (NOT p1)), (X p0), (X (NOT p1)), (X (X p0)), (X (X (NOT p1)))]
False Knowledge obtained : []
Knowledge based reduction with 5 factoid took 214 ms. Reduced automaton from 2 states, 4 edges and 2 AP (stutter insensitive) to 2 states, 4 edges and 2 AP (stutter insensitive).
Stuttering acceptance computed with spot in 62 ms :[(AND (NOT p0) (NOT p1)), (NOT p1)]
Finished random walk after 479 steps, including 0 resets, run visited all 2 properties in 49 ms. (steps per millisecond=9 )
Knowledge obtained : [(AND p0 (NOT p1)), (X p0), (X (NOT p1)), (X (X p0)), (X (X (NOT p1)))]
False Knowledge obtained : [(F (NOT p0)), (F p1)]
Knowledge based reduction with 5 factoid took 200 ms. Reduced automaton from 2 states, 4 edges and 2 AP (stutter insensitive) to 2 states, 4 edges and 2 AP (stutter insensitive).
Stuttering acceptance computed with spot in 94 ms :[(AND (NOT p0) (NOT p1)), (NOT p1)]
Stuttering acceptance computed with spot in 62 ms :[(AND (NOT p0) (NOT p1)), (NOT p1)]
Support contains 3 out of 1380 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 1380/1380 places, 144368/144368 transitions.
Applied a total of 0 rules in 854 ms. Remains 1380 /1380 variables (removed 0) and now considering 144368/144368 (removed 0) transitions.
[2023-03-16 15:58:55] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 15:58:55] [INFO ] Invariant cache hit.
[2023-03-16 15:59:04] [INFO ] Implicit Places using invariants in 9133 ms returned []
Implicit Place search using SMT only with invariants took 9134 ms to find 0 implicit places.
[2023-03-16 15:59:04] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 15:59:04] [INFO ] Invariant cache hit.
[2023-03-16 15:59:34] [INFO ] Performed 86740/144368 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 15:59:54] [INFO ] Dead Transitions using invariants and state equation in 49481 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 59476 ms. Remains : 1380/1380 places, 144368/144368 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Knowledge obtained : [(AND p0 (NOT p1)), (X p0), (X (NOT p1)), (X (X p0)), (X (X (NOT p1)))]
False Knowledge obtained : []
Knowledge based reduction with 5 factoid took 202 ms. Reduced automaton from 2 states, 4 edges and 2 AP (stutter insensitive) to 2 states, 4 edges and 2 AP (stutter insensitive).
Stuttering acceptance computed with spot in 70 ms :[(AND (NOT p0) (NOT p1)), (NOT p1)]
Finished random walk after 1975 steps, including 0 resets, run visited all 2 properties in 196 ms. (steps per millisecond=10 )
Knowledge obtained : [(AND p0 (NOT p1)), (X p0), (X (NOT p1)), (X (X p0)), (X (X (NOT p1)))]
False Knowledge obtained : [(F (NOT p0)), (F p1)]
Knowledge based reduction with 5 factoid took 210 ms. Reduced automaton from 2 states, 4 edges and 2 AP (stutter insensitive) to 2 states, 4 edges and 2 AP (stutter insensitive).
Stuttering acceptance computed with spot in 61 ms :[(AND (NOT p0) (NOT p1)), (NOT p1)]
Stuttering acceptance computed with spot in 74 ms :[(AND (NOT p0) (NOT p1)), (NOT p1)]
Stuttering acceptance computed with spot in 66 ms :[(AND (NOT p0) (NOT p1)), (NOT p1)]
Product exploration explored 100000 steps with 0 reset in 8627 ms.
Product exploration explored 100000 steps with 0 reset in 8785 ms.
Support contains 3 out of 1380 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 1380/1380 places, 144368/144368 transitions.
Applied a total of 0 rules in 827 ms. Remains 1380 /1380 variables (removed 0) and now considering 144368/144368 (removed 0) transitions.
[2023-03-16 16:00:14] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:00:14] [INFO ] Invariant cache hit.
[2023-03-16 16:00:22] [INFO ] Implicit Places using invariants in 7835 ms returned []
Implicit Place search using SMT only with invariants took 7836 ms to find 0 implicit places.
[2023-03-16 16:00:22] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:00:22] [INFO ] Invariant cache hit.
[2023-03-16 16:00:52] [INFO ] Performed 88408/144368 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 16:01:11] [INFO ] Dead Transitions using invariants and state equation in 48949 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 57618 ms. Remains : 1380/1380 places, 144368/144368 transitions.
Treatment of property RERS17pb115-PT-1-LTLCardinality-03 finished in 223080 ms.
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!(F(((p1 U p2)&&p0)))'
Support contains 6 out of 1381 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 1381/1381 places, 144369/144369 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 925 ms. Remains 1380 /1381 variables (removed 1) and now considering 144368/144369 (removed 1) transitions.
[2023-03-16 16:01:17] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:01:17] [INFO ] Invariant cache hit.
[2023-03-16 16:01:25] [INFO ] Implicit Places using invariants in 7939 ms returned []
Implicit Place search using SMT only with invariants took 7940 ms to find 0 implicit places.
[2023-03-16 16:01:25] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:01:25] [INFO ] Invariant cache hit.
[2023-03-16 16:01:55] [INFO ] Performed 89709/144368 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 16:02:13] [INFO ] Dead Transitions using invariants and state equation in 48254 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 57124 ms. Remains : 1380/1381 places, 144368/144369 transitions.
Stuttering acceptance computed with spot in 73 ms :[(NOT p2), (OR (NOT p0) (NOT p2))]
Running random walk in product with property : RERS17pb115-PT-1-LTLCardinality-07 automaton TGBA Formula[mat=[[{ cond=(AND (NOT p2) p1), acceptance={0} source=0 dest: 0}, { cond=(AND (NOT p2) (NOT p1)), acceptance={0} source=0 dest: 1}], [{ cond=(AND p0 (NOT p2) p1), acceptance={0} source=1 dest: 0}, { cond=(OR (NOT p0) (AND (NOT p2) (NOT p1))), acceptance={0} source=1 dest: 1}]], initial=1, aps=[p2:(OR (EQ s1250 0) (EQ s42 1)), p1:(OR (EQ s1361 0) (EQ s794 1)), p0:(AND (EQ s813 0) (EQ s483 1))], nbAcceptance=1, properties=[trans-labels, explicit-labels, trans-acc, colored, deterministic, no-univ-branch, unambiguous, semi-deterministic, stutter-invariant, weak, inherently-weak], stateDesc=[null, null][true, true]]
Product exploration explored 100000 steps with 52 reset in 8305 ms.
Product exploration explored 100000 steps with 54 reset in 8298 ms.
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Knowledge obtained : [(AND p2 p1 (NOT p0)), (X (OR (NOT p0) (AND (NOT p2) (NOT p1)))), (X (NOT (AND (NOT p2) (NOT p1)))), (X (NOT (AND p0 (NOT p2) p1))), (X (NOT (AND (NOT p2) p1))), (X (X (OR (NOT p0) (AND (NOT p2) (NOT p1))))), (X (X (NOT (AND (NOT p2) (NOT p1))))), (X (X (NOT (AND p0 (NOT p2) p1)))), (X (X (NOT (AND (NOT p2) p1))))]
False Knowledge obtained : []
Knowledge based reduction with 9 factoid took 344 ms. Reduced automaton from 2 states, 4 edges and 3 AP (stutter insensitive) to 2 states, 4 edges and 3 AP (stutter insensitive).
Stuttering acceptance computed with spot in 86 ms :[(NOT p2), (OR (NOT p2) (NOT p0))]
Incomplete random walk after 10000 steps, including 2 resets, run finished after 997 ms. (steps per millisecond=10 ) properties (out of 4) seen :2
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 126 ms. (steps per millisecond=79 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 110 ms. (steps per millisecond=90 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-16 16:02:33] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:02:33] [INFO ] Invariant cache hit.
[2023-03-16 16:02:33] [INFO ] [Real]Absence check using 19 positive place invariants in 16 ms returned sat
[2023-03-16 16:02:53] [INFO ] After 20350ms SMT Verify possible using state equation in real domain returned unsat :0 sat :2
[2023-03-16 16:02:54] [INFO ] State equation strengthened by 741 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Broken pipe ...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.addInvarianceKnowledge(LTLPropertySolver.java:701)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.applyKnowledgeBasedReductions(LTLPropertySolver.java:568)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.checkLTLProperty(LTLPropertySolver.java:251)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStutteringLTLTest(LTLPropertySolver.java:225)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStructuralLTLCheck(LTLPropertySolver.java:76)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:762)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 16:02:58] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 16:02:58] [INFO ] After 25032ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Fused 2 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 6 out of 1380 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1380/1380 places, 144368/144368 transitions.
Applied a total of 0 rules in 958 ms. Remains 1380 /1380 variables (removed 0) and now considering 144368/144368 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 961 ms. Remains : 1380/1380 places, 144368/144368 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 968 ms. (steps per millisecond=10 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 121 ms. (steps per millisecond=82 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 150 ms. (steps per millisecond=66 ) properties (out of 2) seen :0
Interrupted probabilistic random walk after 2165 steps, run timeout after 3003 ms. (steps per millisecond=0 ) properties seen :{}
Probabilistic random walk after 2165 steps, saw 1689 distinct states, run finished after 3004 ms. (steps per millisecond=0 ) properties seen :0
Running SMT prover for 2 properties.
[2023-03-16 16:03:03] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:03:03] [INFO ] Invariant cache hit.
[2023-03-16 16:03:03] [INFO ] [Real]Absence check using 19 positive place invariants in 19 ms returned sat
[2023-03-16 16:03:24] [INFO ] After 20506ms SMT Verify possible using state equation in real domain returned unsat :0 sat :2
[2023-03-16 16:03:25] [INFO ] State equation strengthened by 741 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Broken pipe ...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.addInvarianceKnowledge(LTLPropertySolver.java:701)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.applyKnowledgeBasedReductions(LTLPropertySolver.java:568)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.checkLTLProperty(LTLPropertySolver.java:251)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStutteringLTLTest(LTLPropertySolver.java:225)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStructuralLTLCheck(LTLPropertySolver.java:76)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:762)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 16:03:28] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 16:03:28] [INFO ] After 25029ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Fused 2 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 6 out of 1380 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1380/1380 places, 144368/144368 transitions.
Applied a total of 0 rules in 920 ms. Remains 1380 /1380 variables (removed 0) and now considering 144368/144368 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 921 ms. Remains : 1380/1380 places, 144368/144368 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1380/1380 places, 144368/144368 transitions.
Applied a total of 0 rules in 914 ms. Remains 1380 /1380 variables (removed 0) and now considering 144368/144368 (removed 0) transitions.
[2023-03-16 16:03:30] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:03:30] [INFO ] Invariant cache hit.
[2023-03-16 16:03:38] [INFO ] Implicit Places using invariants in 7922 ms returned []
Implicit Place search using SMT only with invariants took 7924 ms to find 0 implicit places.
[2023-03-16 16:03:38] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:03:38] [INFO ] Invariant cache hit.
[2023-03-16 16:04:08] [INFO ] Performed 88910/144368 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 16:04:27] [INFO ] Dead Transitions using invariants and state equation in 48768 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 57624 ms. Remains : 1380/1380 places, 144368/144368 transitions.
Knowledge obtained : [(AND p2 p1 (NOT p0)), (X (OR (NOT p0) (AND (NOT p2) (NOT p1)))), (X (NOT (AND (NOT p2) (NOT p1)))), (X (NOT (AND p0 (NOT p2) p1))), (X (NOT (AND (NOT p2) p1))), (X (X (OR (NOT p0) (AND (NOT p2) (NOT p1))))), (X (X (NOT (AND (NOT p2) (NOT p1))))), (X (X (NOT (AND p0 (NOT p2) p1)))), (X (X (NOT (AND (NOT p2) p1))))]
False Knowledge obtained : [(F (NOT (OR (NOT p0) (AND (NOT p1) (NOT p2))))), (F (AND p1 (NOT p2)))]
Knowledge based reduction with 9 factoid took 348 ms. Reduced automaton from 2 states, 4 edges and 3 AP (stutter insensitive) to 2 states, 4 edges and 3 AP (stutter insensitive).
Stuttering acceptance computed with spot in 68 ms :[(NOT p2), (OR (NOT p2) (NOT p0))]
Stuttering acceptance computed with spot in 71 ms :[(NOT p2), (OR (NOT p2) (NOT p0))]
[2023-03-16 16:04:27] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:04:28] [INFO ] Invariant cache hit.
Could not prove EG (NOT p0)
Support contains 6 out of 1380 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 1380/1380 places, 144368/144368 transitions.
Applied a total of 0 rules in 837 ms. Remains 1380 /1380 variables (removed 0) and now considering 144368/144368 (removed 0) transitions.
[2023-03-16 16:04:44] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:04:44] [INFO ] Invariant cache hit.
[2023-03-16 16:04:52] [INFO ] Implicit Places using invariants in 7771 ms returned []
Implicit Place search using SMT only with invariants took 7773 ms to find 0 implicit places.
[2023-03-16 16:04:52] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:04:52] [INFO ] Invariant cache hit.
[2023-03-16 16:05:22] [INFO ] Performed 89702/144368 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 16:05:40] [INFO ] Dead Transitions using invariants and state equation in 48625 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 57240 ms. Remains : 1380/1380 places, 144368/144368 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Knowledge obtained : [(AND p1 p2 (NOT p0)), (X (NOT (AND (NOT p1) (NOT p2)))), (X (NOT (AND p1 (NOT p2)))), (X (NOT (AND p0 p1 (NOT p2)))), (X (OR (NOT p0) (AND (NOT p1) (NOT p2)))), (X (X (NOT (AND (NOT p1) (NOT p2))))), (X (X (NOT (AND p1 (NOT p2))))), (X (X (NOT (AND p0 p1 (NOT p2))))), (X (X (OR (NOT p0) (AND (NOT p1) (NOT p2)))))]
False Knowledge obtained : []
Knowledge based reduction with 9 factoid took 328 ms. Reduced automaton from 2 states, 4 edges and 3 AP (stutter insensitive) to 2 states, 4 edges and 3 AP (stutter insensitive).
Stuttering acceptance computed with spot in 74 ms :[(OR (NOT p2) (NOT p0)), (NOT p2)]
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1067 ms. (steps per millisecond=9 ) properties (out of 4) seen :3
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 120 ms. (steps per millisecond=83 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-16 16:05:43] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:05:43] [INFO ] Invariant cache hit.
[2023-03-16 16:05:43] [INFO ] [Real]Absence check using 19 positive place invariants in 15 ms returned sat
[2023-03-16 16:06:03] [INFO ] After 19511ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-16 16:06:03] [INFO ] State equation strengthened by 741 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.addInvarianceKnowledge(LTLPropertySolver.java:701)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.applyKnowledgeBasedReductions(LTLPropertySolver.java:568)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.checkLTLProperty(LTLPropertySolver.java:261)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStutteringLTLTest(LTLPropertySolver.java:225)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStructuralLTLCheck(LTLPropertySolver.java:76)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:762)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 16:06:08] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 16:06:08] [INFO ] After 25018ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 0 ms.
Support contains 4 out of 1380 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1380/1380 places, 144368/144368 transitions.
Applied a total of 0 rules in 913 ms. Remains 1380 /1380 variables (removed 0) and now considering 144368/144368 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 916 ms. Remains : 1380/1380 places, 144368/144368 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 996 ms. (steps per millisecond=10 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 103 ms. (steps per millisecond=97 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 2095 steps, run timeout after 3002 ms. (steps per millisecond=0 ) properties seen :{}
Probabilistic random walk after 2095 steps, saw 1633 distinct states, run finished after 3002 ms. (steps per millisecond=0 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-16 16:06:13] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:06:13] [INFO ] Invariant cache hit.
[2023-03-16 16:06:14] [INFO ] [Real]Absence check using 19 positive place invariants in 13 ms returned sat
[2023-03-16 16:06:33] [INFO ] After 19261ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-16 16:06:33] [INFO ] State equation strengthened by 741 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.addInvarianceKnowledge(LTLPropertySolver.java:701)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.applyKnowledgeBasedReductions(LTLPropertySolver.java:568)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.checkLTLProperty(LTLPropertySolver.java:261)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStutteringLTLTest(LTLPropertySolver.java:225)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStructuralLTLCheck(LTLPropertySolver.java:76)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:762)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 16:06:38] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 16:06:38] [INFO ] After 25023ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 0 ms.
Support contains 4 out of 1380 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1380/1380 places, 144368/144368 transitions.
Applied a total of 0 rules in 991 ms. Remains 1380 /1380 variables (removed 0) and now considering 144368/144368 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 991 ms. Remains : 1380/1380 places, 144368/144368 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1380/1380 places, 144368/144368 transitions.
Applied a total of 0 rules in 908 ms. Remains 1380 /1380 variables (removed 0) and now considering 144368/144368 (removed 0) transitions.
[2023-03-16 16:06:40] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:06:40] [INFO ] Invariant cache hit.
[2023-03-16 16:06:49] [INFO ] Implicit Places using invariants in 8456 ms returned []
Implicit Place search using SMT only with invariants took 8458 ms to find 0 implicit places.
[2023-03-16 16:06:49] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:06:49] [INFO ] Invariant cache hit.
[2023-03-16 16:07:19] [INFO ] Performed 89649/144368 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 16:07:37] [INFO ] Dead Transitions using invariants and state equation in 48502 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 57880 ms. Remains : 1380/1380 places, 144368/144368 transitions.
Knowledge obtained : [(AND p1 p2 (NOT p0)), (X (NOT (AND (NOT p1) (NOT p2)))), (X (NOT (AND p1 (NOT p2)))), (X (NOT (AND p0 p1 (NOT p2)))), (X (OR (NOT p0) (AND (NOT p1) (NOT p2)))), (X (X (NOT (AND (NOT p1) (NOT p2))))), (X (X (NOT (AND p1 (NOT p2))))), (X (X (NOT (AND p0 p1 (NOT p2))))), (X (X (OR (NOT p0) (AND (NOT p1) (NOT p2)))))]
False Knowledge obtained : [(F (AND p1 (NOT p2))), (F (NOT (OR (AND (NOT p1) (NOT p2)) (NOT p0)))), (F (AND p1 (NOT p2) p0))]
Knowledge based reduction with 9 factoid took 382 ms. Reduced automaton from 2 states, 4 edges and 3 AP (stutter insensitive) to 2 states, 4 edges and 3 AP (stutter insensitive).
Stuttering acceptance computed with spot in 71 ms :[(OR (NOT p2) (NOT p0)), (NOT p2)]
Stuttering acceptance computed with spot in 87 ms :[(OR (NOT p2) (NOT p0)), (NOT p2)]
[2023-03-16 16:07:38] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:07:39] [INFO ] Invariant cache hit.
Could not prove EG (NOT p0)
Stuttering acceptance computed with spot in 89 ms :[(OR (NOT p2) (NOT p0)), (NOT p2)]
Product exploration explored 100000 steps with 58 reset in 8511 ms.
Product exploration explored 100000 steps with 56 reset in 8885 ms.
Support contains 6 out of 1380 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 1380/1380 places, 144368/144368 transitions.
Applied a total of 0 rules in 838 ms. Remains 1380 /1380 variables (removed 0) and now considering 144368/144368 (removed 0) transitions.
[2023-03-16 16:08:12] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:08:12] [INFO ] Invariant cache hit.
[2023-03-16 16:08:20] [INFO ] Implicit Places using invariants in 8070 ms returned []
Implicit Place search using SMT only with invariants took 8071 ms to find 0 implicit places.
[2023-03-16 16:08:20] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:08:20] [INFO ] Invariant cache hit.
[2023-03-16 16:08:50] [INFO ] Performed 88586/144368 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 16:09:10] [INFO ] Dead Transitions using invariants and state equation in 49552 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 58465 ms. Remains : 1380/1380 places, 144368/144368 transitions.
Treatment of property RERS17pb115-PT-1-LTLCardinality-07 finished in 478919 ms.
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!(G(F(p0)))'
Support contains 2 out of 1381 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 1381/1381 places, 144369/144369 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 952 ms. Remains 1380 /1381 variables (removed 1) and now considering 144368/144369 (removed 1) transitions.
[2023-03-16 16:09:16] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:09:16] [INFO ] Invariant cache hit.
[2023-03-16 16:09:24] [INFO ] Implicit Places using invariants in 8511 ms returned []
Implicit Place search using SMT only with invariants took 8512 ms to find 0 implicit places.
[2023-03-16 16:09:24] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:09:24] [INFO ] Invariant cache hit.
[2023-03-16 16:09:54] [INFO ] Performed 85941/144368 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 16:10:15] [INFO ] Dead Transitions using invariants and state equation in 50685 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 60156 ms. Remains : 1380/1381 places, 144368/144369 transitions.
Stuttering acceptance computed with spot in 83 ms :[(NOT p0), (NOT p0)]
Running random walk in product with property : RERS17pb115-PT-1-LTLCardinality-09 automaton TGBA Formula[mat=[[{ cond=true, acceptance={} source=0 dest: 0}, { cond=(NOT p0), acceptance={} source=0 dest: 1}], [{ cond=(NOT p0), acceptance={0} source=1 dest: 1}]], initial=0, aps=[p0:(OR (EQ s284 0) (EQ s1013 1))], nbAcceptance=1, properties=[trans-labels, explicit-labels, trans-acc, no-univ-branch, stutter-invariant, very-weak, weak, inherently-weak], stateDesc=[null, null][true, true]]
Product exploration explored 100000 steps with 44 reset in 8701 ms.
Product exploration explored 100000 steps with 39 reset in 8394 ms.
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Knowledge obtained : [p0, (X p0), (X (X p0))]
False Knowledge obtained : []
Knowledge based reduction with 3 factoid took 90 ms. Reduced automaton from 2 states, 3 edges and 1 AP (stutter insensitive) to 2 states, 3 edges and 1 AP (stutter insensitive).
Stuttering acceptance computed with spot in 71 ms :[(NOT p0), (NOT p0)]
Finished random walk after 1862 steps, including 0 resets, run visited all 1 properties in 179 ms. (steps per millisecond=10 )
Knowledge obtained : [p0, (X p0), (X (X p0))]
False Knowledge obtained : [(F (NOT p0))]
Knowledge based reduction with 3 factoid took 137 ms. Reduced automaton from 2 states, 3 edges and 1 AP (stutter insensitive) to 2 states, 3 edges and 1 AP (stutter insensitive).
Stuttering acceptance computed with spot in 72 ms :[(NOT p0), (NOT p0)]
Stuttering acceptance computed with spot in 68 ms :[(NOT p0), (NOT p0)]
Support contains 2 out of 1380 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 1380/1380 places, 144368/144368 transitions.
Applied a total of 0 rules in 833 ms. Remains 1380 /1380 variables (removed 0) and now considering 144368/144368 (removed 0) transitions.
[2023-03-16 16:10:35] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:10:35] [INFO ] Invariant cache hit.
[2023-03-16 16:10:43] [INFO ] Implicit Places using invariants in 8565 ms returned []
Implicit Place search using SMT only with invariants took 8570 ms to find 0 implicit places.
[2023-03-16 16:10:43] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:10:43] [INFO ] Invariant cache hit.
[2023-03-16 16:11:14] [INFO ] Performed 86949/144368 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 16:11:34] [INFO ] Dead Transitions using invariants and state equation in 50180 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 59588 ms. Remains : 1380/1380 places, 144368/144368 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Knowledge obtained : [p0, (X p0), (X (X p0))]
False Knowledge obtained : []
Knowledge based reduction with 3 factoid took 132 ms. Reduced automaton from 2 states, 3 edges and 1 AP (stutter insensitive) to 2 states, 3 edges and 1 AP (stutter insensitive).
Stuttering acceptance computed with spot in 68 ms :[(NOT p0), (NOT p0)]
Finished random walk after 4510 steps, including 1 resets, run visited all 1 properties in 446 ms. (steps per millisecond=10 )
Knowledge obtained : [p0, (X p0), (X (X p0))]
False Knowledge obtained : [(F (NOT p0))]
Knowledge based reduction with 3 factoid took 142 ms. Reduced automaton from 2 states, 3 edges and 1 AP (stutter insensitive) to 2 states, 3 edges and 1 AP (stutter insensitive).
Stuttering acceptance computed with spot in 75 ms :[(NOT p0), (NOT p0)]
Stuttering acceptance computed with spot in 63 ms :[(NOT p0), (NOT p0)]
Stuttering acceptance computed with spot in 63 ms :[(NOT p0), (NOT p0)]
Product exploration explored 100000 steps with 37 reset in 8704 ms.
Product exploration explored 100000 steps with 42 reset in 8665 ms.
Support contains 2 out of 1380 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 1380/1380 places, 144368/144368 transitions.
Applied a total of 0 rules in 902 ms. Remains 1380 /1380 variables (removed 0) and now considering 144368/144368 (removed 0) transitions.
[2023-03-16 16:11:54] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:11:54] [INFO ] Invariant cache hit.
[2023-03-16 16:12:03] [INFO ] Implicit Places using invariants in 9419 ms returned []
Implicit Place search using SMT only with invariants took 9422 ms to find 0 implicit places.
[2023-03-16 16:12:04] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:12:04] [INFO ] Invariant cache hit.
[2023-03-16 16:12:34] [INFO ] Performed 86226/144368 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 16:12:53] [INFO ] Dead Transitions using invariants and state equation in 49816 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 60144 ms. Remains : 1380/1380 places, 144368/144368 transitions.
Treatment of property RERS17pb115-PT-1-LTLCardinality-09 finished in 223813 ms.
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!(G((X(G(p0)) U p0)))'
Support contains 2 out of 1381 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 1381/1381 places, 144369/144369 transitions.
Applied a total of 0 rules in 445 ms. Remains 1381 /1381 variables (removed 0) and now considering 144369/144369 (removed 0) transitions.
[2023-03-16 16:12:59] [INFO ] Flow matrix only has 81238 transitions (discarded 63131 similar events)
// Phase 1: matrix 81238 rows 1381 cols
[2023-03-16 16:12:59] [INFO ] Computed 19 place invariants in 317 ms
[2023-03-16 16:13:08] [INFO ] Implicit Places using invariants in 8958 ms returned []
Implicit Place search using SMT only with invariants took 8963 ms to find 0 implicit places.
[2023-03-16 16:13:08] [INFO ] Flow matrix only has 81238 transitions (discarded 63131 similar events)
[2023-03-16 16:13:08] [INFO ] Invariant cache hit.
[2023-03-16 16:13:38] [INFO ] Performed 89229/144369 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 16:13:57] [INFO ] Dead Transitions using invariants and state equation in 49024 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 58435 ms. Remains : 1381/1381 places, 144369/144369 transitions.
Stuttering acceptance computed with spot in 90 ms :[true, (NOT p0), (NOT p0)]
Running random walk in product with property : RERS17pb115-PT-1-LTLCardinality-13 automaton TGBA Formula[mat=[[{ cond=true, acceptance={0} source=0 dest: 0}], [{ cond=p0, acceptance={} source=1 dest: 1}, { cond=(NOT p0), acceptance={} source=1 dest: 2}], [{ cond=(NOT p0), acceptance={} source=2 dest: 0}, { cond=p0, acceptance={} source=2 dest: 2}]], initial=1, aps=[p0:(OR (EQ s1202 0) (EQ s524 1))], nbAcceptance=1, properties=[trans-labels, explicit-labels, trans-acc, complete, deterministic, no-univ-branch, unambiguous, semi-deterministic, stutter-sensitive, terminal, very-weak, weak, inherently-weak], stateDesc=[null, null, null][false, false, false]]
Entered a terminal (fully accepting) state of product in 1167 steps with 0 reset in 129 ms.
FORMULA RERS17pb115-PT-1-LTLCardinality-13 FALSE TECHNIQUES STUTTER_TEST
Treatment of property RERS17pb115-PT-1-LTLCardinality-13 finished in 59036 ms.
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!(F(G(p0)))'
Support contains 2 out of 1381 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 1381/1381 places, 144369/144369 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 1073 ms. Remains 1380 /1381 variables (removed 1) and now considering 144368/144369 (removed 1) transitions.
[2023-03-16 16:13:59] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
// Phase 1: matrix 81237 rows 1380 cols
[2023-03-16 16:13:59] [INFO ] Computed 19 place invariants in 265 ms
[2023-03-16 16:14:07] [INFO ] Implicit Places using invariants in 8754 ms returned []
Implicit Place search using SMT only with invariants took 8756 ms to find 0 implicit places.
[2023-03-16 16:14:07] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:14:07] [INFO ] Invariant cache hit.
[2023-03-16 16:14:38] [INFO ] Performed 87767/144368 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 16:14:57] [INFO ] Dead Transitions using invariants and state equation in 50091 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 59925 ms. Remains : 1380/1381 places, 144368/144369 transitions.
Stuttering acceptance computed with spot in 50 ms :[(NOT p0)]
Running random walk in product with property : RERS17pb115-PT-1-LTLCardinality-14 automaton TGBA Formula[mat=[[{ cond=p0, acceptance={} source=0 dest: 0}, { cond=(NOT p0), acceptance={0} source=0 dest: 0}]], initial=0, aps=[p0:(AND (NEQ s839 0) (NEQ s30 1))], nbAcceptance=1, properties=[trans-labels, explicit-labels, trans-acc, complete, deterministic, no-univ-branch, unambiguous, semi-deterministic, stutter-invariant], stateDesc=[null][true]]
Product exploration explored 100000 steps with 0 reset in 9433 ms.
Product exploration explored 100000 steps with 0 reset in 9524 ms.
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Knowledge obtained : [(NOT p0), (X (NOT p0)), (X (X (NOT p0)))]
False Knowledge obtained : []
Knowledge based reduction with 3 factoid took 123 ms. Reduced automaton from 1 states, 2 edges and 1 AP (stutter insensitive) to 1 states, 2 edges and 1 AP (stutter insensitive).
Stuttering acceptance computed with spot in 37 ms :[(NOT p0)]
Finished random walk after 4249 steps, including 1 resets, run visited all 1 properties in 420 ms. (steps per millisecond=10 )
Knowledge obtained : [(NOT p0), (X (NOT p0)), (X (X (NOT p0)))]
False Knowledge obtained : [(F p0)]
Knowledge based reduction with 3 factoid took 149 ms. Reduced automaton from 1 states, 2 edges and 1 AP (stutter insensitive) to 1 states, 2 edges and 1 AP (stutter insensitive).
Stuttering acceptance computed with spot in 35 ms :[(NOT p0)]
Stuttering acceptance computed with spot in 29 ms :[(NOT p0)]
[2023-03-16 16:15:19] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:15:19] [INFO ] Invariant cache hit.
Could not prove EG (NOT p0)
Support contains 2 out of 1380 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 1380/1380 places, 144368/144368 transitions.
Applied a total of 0 rules in 1087 ms. Remains 1380 /1380 variables (removed 0) and now considering 144368/144368 (removed 0) transitions.
[2023-03-16 16:15:35] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:15:35] [INFO ] Invariant cache hit.
[2023-03-16 16:15:43] [INFO ] Implicit Places using invariants in 8352 ms returned []
Implicit Place search using SMT only with invariants took 8352 ms to find 0 implicit places.
[2023-03-16 16:15:43] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:15:43] [INFO ] Invariant cache hit.
[2023-03-16 16:16:14] [INFO ] Performed 87910/144368 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 16:16:33] [INFO ] Dead Transitions using invariants and state equation in 49382 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 58826 ms. Remains : 1380/1380 places, 144368/144368 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Knowledge obtained : [(NOT p0), (X (NOT p0)), (X (X (NOT p0)))]
False Knowledge obtained : []
Knowledge based reduction with 3 factoid took 124 ms. Reduced automaton from 1 states, 2 edges and 1 AP (stutter insensitive) to 1 states, 2 edges and 1 AP (stutter insensitive).
Stuttering acceptance computed with spot in 30 ms :[(NOT p0)]
Finished random walk after 923 steps, including 0 resets, run visited all 1 properties in 88 ms. (steps per millisecond=10 )
Knowledge obtained : [(NOT p0), (X (NOT p0)), (X (X (NOT p0)))]
False Knowledge obtained : [(F p0)]
Knowledge based reduction with 3 factoid took 154 ms. Reduced automaton from 1 states, 2 edges and 1 AP (stutter insensitive) to 1 states, 2 edges and 1 AP (stutter insensitive).
Stuttering acceptance computed with spot in 38 ms :[(NOT p0)]
Stuttering acceptance computed with spot in 25 ms :[(NOT p0)]
[2023-03-16 16:16:34] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:16:35] [INFO ] Invariant cache hit.
Could not prove EG (NOT p0)
Stuttering acceptance computed with spot in 44 ms :[(NOT p0)]
Product exploration explored 100000 steps with 0 reset in 8781 ms.
Product exploration explored 100000 steps with 0 reset in 9082 ms.
Support contains 2 out of 1380 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 1380/1380 places, 144368/144368 transitions.
Applied a total of 0 rules in 846 ms. Remains 1380 /1380 variables (removed 0) and now considering 144368/144368 (removed 0) transitions.
[2023-03-16 16:17:09] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:17:09] [INFO ] Invariant cache hit.
[2023-03-16 16:17:17] [INFO ] Implicit Places using invariants in 8200 ms returned []
Implicit Place search using SMT only with invariants took 8202 ms to find 0 implicit places.
[2023-03-16 16:17:17] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:17:17] [INFO ] Invariant cache hit.
[2023-03-16 16:17:47] [INFO ] Performed 90452/144368 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 16:18:05] [INFO ] Dead Transitions using invariants and state equation in 48108 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 57159 ms. Remains : 1380/1380 places, 144368/144368 transitions.
Treatment of property RERS17pb115-PT-1-LTLCardinality-14 finished in 252897 ms.
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!(F((G(F(p0))||G(p1))))'
Support contains 4 out of 1381 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 1381/1381 places, 144369/144369 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 955 ms. Remains 1380 /1381 variables (removed 1) and now considering 144368/144369 (removed 1) transitions.
[2023-03-16 16:18:11] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:18:11] [INFO ] Invariant cache hit.
[2023-03-16 16:18:20] [INFO ] Implicit Places using invariants in 8421 ms returned []
Implicit Place search using SMT only with invariants took 8422 ms to find 0 implicit places.
[2023-03-16 16:18:20] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:18:20] [INFO ] Invariant cache hit.
[2023-03-16 16:18:50] [INFO ] Performed 88491/144368 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 16:19:09] [INFO ] Dead Transitions using invariants and state equation in 48994 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 58376 ms. Remains : 1380/1381 places, 144368/144369 transitions.
Stuttering acceptance computed with spot in 75 ms :[(AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0))]
Running random walk in product with property : RERS17pb115-PT-1-LTLCardinality-15 automaton TGBA Formula[mat=[[{ cond=true, acceptance={} source=0 dest: 0}, { cond=(AND (NOT p1) (NOT p0)), acceptance={} source=0 dest: 1}], [{ cond=(AND p1 (NOT p0)), acceptance={} source=1 dest: 1}, { cond=(AND (NOT p1) (NOT p0)), acceptance={0} source=1 dest: 1}]], initial=0, aps=[p1:(OR (EQ s444 0) (EQ s746 1)), p0:(OR (EQ s437 0) (EQ s644 1))], nbAcceptance=1, properties=[trans-labels, explicit-labels, trans-acc, no-univ-branch, stutter-invariant], stateDesc=[null, null][true, true]]
Product exploration explored 100000 steps with 3 reset in 9178 ms.
Product exploration explored 100000 steps with 3 reset in 8706 ms.
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Knowledge obtained : [(AND p1 p0), (X (NOT (AND (NOT p1) (NOT p0)))), (X (NOT (AND p1 (NOT p0)))), (X (X (NOT (AND (NOT p1) (NOT p0))))), (X (X (NOT (AND p1 (NOT p0)))))]
False Knowledge obtained : []
Knowledge based reduction with 5 factoid took 187 ms. Reduced automaton from 2 states, 4 edges and 2 AP (stutter insensitive) to 2 states, 4 edges and 2 AP (stutter insensitive).
Stuttering acceptance computed with spot in 78 ms :[(AND (NOT p0) (NOT p1)), (AND (NOT p0) (NOT p1))]
Incomplete random walk after 10000 steps, including 2 resets, run finished after 991 ms. (steps per millisecond=10 ) properties (out of 2) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 105 ms. (steps per millisecond=95 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-16 16:19:29] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:19:29] [INFO ] Invariant cache hit.
[2023-03-16 16:19:30] [INFO ] [Real]Absence check using 19 positive place invariants in 14 ms returned sat
[2023-03-16 16:19:49] [INFO ] After 19367ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-16 16:19:50] [INFO ] State equation strengthened by 741 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.addInvarianceKnowledge(LTLPropertySolver.java:701)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.applyKnowledgeBasedReductions(LTLPropertySolver.java:568)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.checkLTLProperty(LTLPropertySolver.java:251)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStutteringLTLTest(LTLPropertySolver.java:225)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStructuralLTLCheck(LTLPropertySolver.java:76)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:762)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 16:19:54] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 16:19:54] [INFO ] After 25032ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 0 ms.
Support contains 4 out of 1380 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1380/1380 places, 144368/144368 transitions.
Applied a total of 0 rules in 920 ms. Remains 1380 /1380 variables (removed 0) and now considering 144368/144368 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 924 ms. Remains : 1380/1380 places, 144368/144368 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 980 ms. (steps per millisecond=10 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 104 ms. (steps per millisecond=96 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 1985 steps, run timeout after 3003 ms. (steps per millisecond=0 ) properties seen :{}
Probabilistic random walk after 1985 steps, saw 1547 distinct states, run finished after 3003 ms. (steps per millisecond=0 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-16 16:20:00] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:20:00] [INFO ] Invariant cache hit.
[2023-03-16 16:20:00] [INFO ] [Real]Absence check using 19 positive place invariants in 14 ms returned sat
[2023-03-16 16:20:19] [INFO ] After 19237ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-16 16:20:20] [INFO ] State equation strengthened by 741 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.addInvarianceKnowledge(LTLPropertySolver.java:701)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.applyKnowledgeBasedReductions(LTLPropertySolver.java:568)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.checkLTLProperty(LTLPropertySolver.java:251)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStutteringLTLTest(LTLPropertySolver.java:225)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStructuralLTLCheck(LTLPropertySolver.java:76)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:762)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 16:20:25] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 16:20:25] [INFO ] After 25027ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 0 ms.
Support contains 4 out of 1380 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1380/1380 places, 144368/144368 transitions.
Applied a total of 0 rules in 916 ms. Remains 1380 /1380 variables (removed 0) and now considering 144368/144368 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 916 ms. Remains : 1380/1380 places, 144368/144368 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1380/1380 places, 144368/144368 transitions.
Applied a total of 0 rules in 915 ms. Remains 1380 /1380 variables (removed 0) and now considering 144368/144368 (removed 0) transitions.
[2023-03-16 16:20:27] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:20:27] [INFO ] Invariant cache hit.
[2023-03-16 16:20:36] [INFO ] Implicit Places using invariants in 8836 ms returned []
Implicit Place search using SMT only with invariants took 8837 ms to find 0 implicit places.
[2023-03-16 16:20:36] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:20:36] [INFO ] Invariant cache hit.
[2023-03-16 16:21:06] [INFO ] Performed 89410/144368 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 16:21:24] [INFO ] Dead Transitions using invariants and state equation in 48596 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 58361 ms. Remains : 1380/1380 places, 144368/144368 transitions.
Knowledge obtained : [(AND p1 p0), (X (NOT (AND (NOT p1) (NOT p0)))), (X (NOT (AND p1 (NOT p0)))), (X (X (NOT (AND (NOT p1) (NOT p0))))), (X (X (NOT (AND p1 (NOT p0)))))]
False Knowledge obtained : [(F (AND (NOT p0) p1))]
Knowledge based reduction with 5 factoid took 249 ms. Reduced automaton from 2 states, 4 edges and 2 AP (stutter insensitive) to 2 states, 4 edges and 2 AP (stutter insensitive).
Stuttering acceptance computed with spot in 83 ms :[(AND (NOT p0) (NOT p1)), (AND (NOT p0) (NOT p1))]
Stuttering acceptance computed with spot in 72 ms :[(AND (NOT p0) (NOT p1)), (AND (NOT p0) (NOT p1))]
Support contains 4 out of 1380 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 1380/1380 places, 144368/144368 transitions.
Applied a total of 0 rules in 841 ms. Remains 1380 /1380 variables (removed 0) and now considering 144368/144368 (removed 0) transitions.
[2023-03-16 16:21:26] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:21:26] [INFO ] Invariant cache hit.
[2023-03-16 16:21:34] [INFO ] Implicit Places using invariants in 8488 ms returned []
Implicit Place search using SMT only with invariants took 8489 ms to find 0 implicit places.
[2023-03-16 16:21:34] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:21:34] [INFO ] Invariant cache hit.
[2023-03-16 16:22:04] [INFO ] Performed 90545/144368 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 16:22:23] [INFO ] Dead Transitions using invariants and state equation in 48569 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 57903 ms. Remains : 1380/1380 places, 144368/144368 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Knowledge obtained : [(AND p0 p1), (X (NOT (AND (NOT p0) (NOT p1)))), (X (NOT (AND (NOT p0) p1))), (X (X (NOT (AND (NOT p0) (NOT p1))))), (X (X (NOT (AND (NOT p0) p1))))]
False Knowledge obtained : []
Knowledge based reduction with 5 factoid took 171 ms. Reduced automaton from 2 states, 4 edges and 2 AP (stutter insensitive) to 2 states, 4 edges and 2 AP (stutter insensitive).
Stuttering acceptance computed with spot in 73 ms :[(AND (NOT p0) (NOT p1)), (AND (NOT p0) (NOT p1))]
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1061 ms. (steps per millisecond=9 ) properties (out of 2) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 115 ms. (steps per millisecond=86 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-16 16:22:25] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:22:25] [INFO ] Invariant cache hit.
[2023-03-16 16:22:26] [INFO ] [Real]Absence check using 19 positive place invariants in 13 ms returned sat
[2023-03-16 16:22:45] [INFO ] After 19394ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-16 16:22:46] [INFO ] State equation strengthened by 741 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Broken pipe ...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.addInvarianceKnowledge(LTLPropertySolver.java:701)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.applyKnowledgeBasedReductions(LTLPropertySolver.java:568)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.checkLTLProperty(LTLPropertySolver.java:261)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStutteringLTLTest(LTLPropertySolver.java:225)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStructuralLTLCheck(LTLPropertySolver.java:76)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:762)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 16:22:50] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 16:22:50] [INFO ] After 25023ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 0 ms.
Support contains 4 out of 1380 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1380/1380 places, 144368/144368 transitions.
Applied a total of 0 rules in 914 ms. Remains 1380 /1380 variables (removed 0) and now considering 144368/144368 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 918 ms. Remains : 1380/1380 places, 144368/144368 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1003 ms. (steps per millisecond=9 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 103 ms. (steps per millisecond=97 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 2014 steps, run timeout after 3005 ms. (steps per millisecond=0 ) properties seen :{}
Probabilistic random walk after 2014 steps, saw 1567 distinct states, run finished after 3006 ms. (steps per millisecond=0 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-16 16:22:56] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:22:56] [INFO ] Invariant cache hit.
[2023-03-16 16:22:56] [INFO ] [Real]Absence check using 19 positive place invariants in 12 ms returned sat
[2023-03-16 16:23:15] [INFO ] After 19454ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-16 16:23:16] [INFO ] State equation strengthened by 741 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Broken pipe ...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.addInvarianceKnowledge(LTLPropertySolver.java:701)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.applyKnowledgeBasedReductions(LTLPropertySolver.java:568)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.checkLTLProperty(LTLPropertySolver.java:261)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStutteringLTLTest(LTLPropertySolver.java:225)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStructuralLTLCheck(LTLPropertySolver.java:76)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:762)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 16:23:21] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 16:23:21] [INFO ] After 25028ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 0 ms.
Support contains 4 out of 1380 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1380/1380 places, 144368/144368 transitions.
Applied a total of 0 rules in 924 ms. Remains 1380 /1380 variables (removed 0) and now considering 144368/144368 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 924 ms. Remains : 1380/1380 places, 144368/144368 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1380/1380 places, 144368/144368 transitions.
Applied a total of 0 rules in 924 ms. Remains 1380 /1380 variables (removed 0) and now considering 144368/144368 (removed 0) transitions.
[2023-03-16 16:23:23] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:23:23] [INFO ] Invariant cache hit.
[2023-03-16 16:23:31] [INFO ] Implicit Places using invariants in 8559 ms returned []
Implicit Place search using SMT only with invariants took 8560 ms to find 0 implicit places.
[2023-03-16 16:23:31] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:23:31] [INFO ] Invariant cache hit.
[2023-03-16 16:24:01] [INFO ] Performed 89857/144368 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 16:24:20] [INFO ] Dead Transitions using invariants and state equation in 49200 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 58699 ms. Remains : 1380/1380 places, 144368/144368 transitions.
Knowledge obtained : [(AND p0 p1), (X (NOT (AND (NOT p0) (NOT p1)))), (X (NOT (AND (NOT p0) p1))), (X (X (NOT (AND (NOT p0) (NOT p1))))), (X (X (NOT (AND (NOT p0) p1))))]
False Knowledge obtained : [(F (AND (NOT p0) p1))]
Knowledge based reduction with 5 factoid took 214 ms. Reduced automaton from 2 states, 4 edges and 2 AP (stutter insensitive) to 2 states, 4 edges and 2 AP (stutter insensitive).
Stuttering acceptance computed with spot in 66 ms :[(AND (NOT p0) (NOT p1)), (AND (NOT p0) (NOT p1))]
Stuttering acceptance computed with spot in 91 ms :[(AND (NOT p0) (NOT p1)), (AND (NOT p0) (NOT p1))]
Stuttering acceptance computed with spot in 71 ms :[(AND (NOT p0) (NOT p1)), (AND (NOT p0) (NOT p1))]
Product exploration explored 100000 steps with 3 reset in 8884 ms.
Product exploration explored 100000 steps with 1 reset in 9036 ms.
Support contains 4 out of 1380 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 1380/1380 places, 144368/144368 transitions.
Applied a total of 0 rules in 842 ms. Remains 1380 /1380 variables (removed 0) and now considering 144368/144368 (removed 0) transitions.
[2023-03-16 16:24:40] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:24:40] [INFO ] Invariant cache hit.
[2023-03-16 16:24:49] [INFO ] Implicit Places using invariants in 8775 ms returned []
Implicit Place search using SMT only with invariants took 8776 ms to find 0 implicit places.
[2023-03-16 16:24:49] [INFO ] Flow matrix only has 81237 transitions (discarded 63131 similar events)
[2023-03-16 16:24:49] [INFO ] Invariant cache hit.
[2023-03-16 16:25:19] [INFO ] Performed 90898/144368 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 16:25:38] [INFO ] Dead Transitions using invariants and state equation in 48815 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 58436 ms. Remains : 1380/1380 places, 144368/144368 transitions.
Treatment of property RERS17pb115-PT-1-LTLCardinality-15 finished in 452289 ms.
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!(G(F(p0)))'
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!((X(((X(p1)&&G(!p2))||p0)) U p3))'
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!((G(p0)||F(G(p1))))'
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!(F(((p1 U p2)&&p0)))'
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!(G(F(p0)))'
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!(F(G(p0)))'
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!(F((G(F(p0))||G(p1))))'
[2023-03-16 16:25:47] [INFO ] Flatten gal took : 3344 ms
[2023-03-16 16:25:47] [INFO ] Export to MCC of 7 properties in file /home/mcc/execution/LTLCardinality.sr.xml took 2 ms.
[2023-03-16 16:25:47] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 1381 places, 144369 transitions and 577396 arcs took 324 ms.
Total runtime 2363730 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT RERS17pb115-PT-1
BK_EXAMINATION: LTLCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
LTLCardinality
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 12650300 kB
After kill :
MemTotal: 16393216 kB
MemFree: 15903884 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination LTLCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/LTLCardinality.xml
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 59 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 64 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 69 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 74 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 79 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 84 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 89 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 94 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 99 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 104 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 109 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 114 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 119 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 124 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 129 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 134 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 139 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 144 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 149 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 154 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 159 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 164 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 169 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 174 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 179 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 184 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 189 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 194 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 199 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 204 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 209 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 214 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 219 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 224 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 229 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 234 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 239 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 244 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 249 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 254 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 259 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 264 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 269 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 274 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 279 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 284 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 289 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 294 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 299 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 304 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 309 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 314 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 319 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 324 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 329 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 334 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 339 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 344 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 349 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 354 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 359 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 364 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 369 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 374 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 379 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 384 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 389 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 394 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 399 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 404 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 409 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 414 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 419 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 424 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 429 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 434 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 439 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 444 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 449 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 454 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 459 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 464 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 469 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 474 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 479 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 484 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 489 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 494 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 499 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 504 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 509 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 514 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 519 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 524 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 529 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 534 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 539 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 544 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 549 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 554 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 559 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 564 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 569 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 574 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 579 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 584 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 589 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 594 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 599 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 604 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 609 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 614 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 619 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 624 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 629 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
lola: Created skeleton in 577.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 634 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 639 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 644 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 649 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 654 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 659 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 664 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 669 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 674 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 679 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 684 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 689 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 694 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 699 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 704 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 709 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 714 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 719 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 724 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 729 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 734 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 739 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 745 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 750 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 755 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 760 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 765 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 770 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 775 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 780 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 785 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 790 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 795 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 800 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 805 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 810 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 815 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 820 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 825 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 830 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 835 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 840 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 845 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 850 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 855 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 860 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 865 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 870 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 875 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 880 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 885 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 890 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 895 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 900 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 905 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 910 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 915 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 920 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 925 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 930 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 935 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 940 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 945 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 950 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 955 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 960 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 965 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 970 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 975 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 980 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 985 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 990 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 995 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1000 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1005 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1010 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1015 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1020 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1025 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1030 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1035 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1040 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1045 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1050 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1055 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1060 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1065 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1070 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1075 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1080 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1085 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1090 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1095 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1100 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1105 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1110 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1115 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1120 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1125 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1130 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1135 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1140 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1145 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1150 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1155 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1160 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1165 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1170 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1175 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1180 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1185 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1190 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1195 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1200 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1205 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1210 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
lola: Created skeleton in 581.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1215 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1220 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1225 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-1-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-1-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-1-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1230 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 7
lola: caught signal Terminated - aborting LoLA

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb115-PT-1-LTLCardinality-00: LTL unknown AGGR
RERS17pb115-PT-1-LTLCardinality-01: LTL unknown AGGR
RERS17pb115-PT-1-LTLCardinality-03: LTL unknown AGGR
RERS17pb115-PT-1-LTLCardinality-07: LTL unknown AGGR
RERS17pb115-PT-1-LTLCardinality-09: LTL unknown AGGR
RERS17pb115-PT-1-LTLCardinality-14: LTL unknown AGGR
RERS17pb115-PT-1-LTLCardinality-15: LTL unknown AGGR


Time elapsed: 1234 secs. Pages in use: 0

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RERS17pb115-PT-1"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is RERS17pb115-PT-1, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r327-tall-167889199200147"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RERS17pb115-PT-1.tgz
mv RERS17pb115-PT-1 execution
cd execution
if [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "UpperBounds" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] || [ "LTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;