About the Execution of LoLa+red for RERS17pb114-PT-8
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16203.871 | 3600000.00 | 3716862.00 | 9620.60 | ?????????????T?? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r327-tall-167889199200130.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is RERS17pb114-PT-8, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r327-tall-167889199200130
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 73M
-rw-r--r-- 1 mcc users 6.2K Feb 26 05:04 CTLCardinality.txt
-rw-r--r-- 1 mcc users 63K Feb 26 05:04 CTLCardinality.xml
-rw-r--r-- 1 mcc users 8.0K Feb 26 05:00 CTLFireability.txt
-rw-r--r-- 1 mcc users 58K Feb 26 05:00 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 16:39 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Feb 25 16:39 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.0K Feb 25 16:39 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:39 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 26 05:11 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 159K Feb 26 05:11 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.7K Feb 26 05:08 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 59K Feb 26 05:08 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:39 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:39 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 73M Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME RERS17pb114-PT-8-CTLFireability-00
FORMULA_NAME RERS17pb114-PT-8-CTLFireability-01
FORMULA_NAME RERS17pb114-PT-8-CTLFireability-02
FORMULA_NAME RERS17pb114-PT-8-CTLFireability-03
FORMULA_NAME RERS17pb114-PT-8-CTLFireability-04
FORMULA_NAME RERS17pb114-PT-8-CTLFireability-05
FORMULA_NAME RERS17pb114-PT-8-CTLFireability-06
FORMULA_NAME RERS17pb114-PT-8-CTLFireability-07
FORMULA_NAME RERS17pb114-PT-8-CTLFireability-08
FORMULA_NAME RERS17pb114-PT-8-CTLFireability-09
FORMULA_NAME RERS17pb114-PT-8-CTLFireability-10
FORMULA_NAME RERS17pb114-PT-8-CTLFireability-11
FORMULA_NAME RERS17pb114-PT-8-CTLFireability-12
FORMULA_NAME RERS17pb114-PT-8-CTLFireability-13
FORMULA_NAME RERS17pb114-PT-8-CTLFireability-14
FORMULA_NAME RERS17pb114-PT-8-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678974464611
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RERS17pb114-PT-8
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-16 13:47:46] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-16 13:47:46] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-16 13:47:48] [INFO ] Load time of PNML (sax parser for PT used): 1887 ms
[2023-03-16 13:47:48] [INFO ] Transformed 1446 places.
[2023-03-16 13:47:48] [INFO ] Transformed 151085 transitions.
[2023-03-16 13:47:48] [INFO ] Parsed PT model containing 1446 places and 151085 transitions and 604252 arcs in 2387 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 37 ms.
Support contains 238 out of 1446 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 1446/1446 places, 151085/151085 transitions.
Ensure Unique test removed 17 places
Iterating post reduction 0 with 17 rules applied. Total rules applied 17 place count 1429 transition count 151085
Applied a total of 17 rules in 1008 ms. Remains 1429 /1446 variables (removed 17) and now considering 151085/151085 (removed 0) transitions.
[2023-03-16 13:47:50] [INFO ] Flow matrix only has 84691 transitions (discarded 66394 similar events)
// Phase 1: matrix 84691 rows 1429 cols
[2023-03-16 13:47:51] [INFO ] Computed 18 place invariants in 458 ms
[2023-03-16 13:47:59] [INFO ] Implicit Places using invariants in 8720 ms returned []
Implicit Place search using SMT only with invariants took 8751 ms to find 0 implicit places.
[2023-03-16 13:47:59] [INFO ] Flow matrix only has 84691 transitions (discarded 66394 similar events)
[2023-03-16 13:47:59] [INFO ] Invariant cache hit.
[2023-03-16 13:48:29] [INFO ] Performed 95895/151085 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 13:48:46] [INFO ] Dead Transitions using invariants and state equation in 47257 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 1429/1446 places, 151085/151085 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 57037 ms. Remains : 1429/1446 places, 151085/151085 transitions.
Support contains 238 out of 1429 places after structural reductions.
[2023-03-16 13:48:51] [INFO ] Flatten gal took : 3339 ms
[2023-03-16 13:48:54] [INFO ] Flatten gal took : 3370 ms
[2023-03-16 13:49:01] [INFO ] Input system was already deterministic with 151085 transitions.
Support contains 230 out of 1429 places (down from 238) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1025 ms. (steps per millisecond=9 ) properties (out of 95) seen :6
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 114 ms. (steps per millisecond=8 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 89) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 89) seen :0
Interrupted probabilistic random walk after 9874 steps, run timeout after 6003 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 9874 steps, saw 8219 distinct states, run finished after 6004 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 89 properties.
[2023-03-16 13:49:11] [INFO ] Flow matrix only has 84691 transitions (discarded 66394 similar events)
[2023-03-16 13:49:11] [INFO ] Invariant cache hit.
[2023-03-16 13:49:13] [INFO ] [Real]Absence check using 18 positive place invariants in 16 ms returned sat
[2023-03-16 13:49:15] [INFO ] After 3858ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:89
[2023-03-16 13:49:17] [INFO ] [Nat]Absence check using 18 positive place invariants in 14 ms returned sat
[2023-03-16 13:49:40] [INFO ] After 21455ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :89
[2023-03-16 13:49:42] [INFO ] State equation strengthened by 2342 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 13:49:42] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 13:49:42] [INFO ] After 27313ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:89
Fused 89 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 1 ms.
Support contains 216 out of 1429 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Drop transitions removed 512 transitions
Reduce isomorphic transitions removed 512 transitions.
Iterating post reduction 0 with 512 rules applied. Total rules applied 512 place count 1429 transition count 150573
Applied a total of 512 rules in 2050 ms. Remains 1429 /1429 variables (removed 0) and now considering 150573/151085 (removed 512) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 2059 ms. Remains : 1429/1429 places, 150573/151085 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1207 ms. (steps per millisecond=8 ) properties (out of 89) seen :3
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=30 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 86) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 86) seen :0
Interrupted probabilistic random walk after 9304 steps, run timeout after 6006 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 9304 steps, saw 8439 distinct states, run finished after 6006 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 86 properties.
[2023-03-16 13:49:53] [INFO ] Flow matrix only has 84690 transitions (discarded 65883 similar events)
// Phase 1: matrix 84690 rows 1429 cols
[2023-03-16 13:49:53] [INFO ] Computed 18 place invariants in 270 ms
[2023-03-16 13:49:55] [INFO ] [Real]Absence check using 18 positive place invariants in 16 ms returned sat
[2023-03-16 13:49:57] [INFO ] After 3607ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:86
[2023-03-16 13:49:59] [INFO ] [Nat]Absence check using 18 positive place invariants in 13 ms returned sat
[2023-03-16 13:50:22] [INFO ] After 21578ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :86
[2023-03-16 13:50:24] [INFO ] State equation strengthened by 2341 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 13:50:24] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 13:50:24] [INFO ] After 26848ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:86
Fused 86 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 210 out of 1429 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1429/1429 places, 150573/150573 transitions.
Applied a total of 0 rules in 1379 ms. Remains 1429 /1429 variables (removed 0) and now considering 150573/150573 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1379 ms. Remains : 1429/1429 places, 150573/150573 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 992 ms. (steps per millisecond=10 ) properties (out of 86) seen :3
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 48 ms. (steps per millisecond=20 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 45 ms. (steps per millisecond=22 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 83) seen :0
Interrupted probabilistic random walk after 8969 steps, run timeout after 6001 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 8969 steps, saw 8147 distinct states, run finished after 6001 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 83 properties.
[2023-03-16 13:50:34] [INFO ] Flow matrix only has 84690 transitions (discarded 65883 similar events)
[2023-03-16 13:50:34] [INFO ] Invariant cache hit.
[2023-03-16 13:50:36] [INFO ] [Real]Absence check using 18 positive place invariants in 15 ms returned sat
[2023-03-16 13:50:37] [INFO ] After 3746ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:83
[2023-03-16 13:50:39] [INFO ] [Nat]Absence check using 18 positive place invariants in 13 ms returned sat
[2023-03-16 13:51:02] [INFO ] After 21608ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :83
[2023-03-16 13:51:03] [INFO ] State equation strengthened by 2341 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 13:51:03] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 13:51:03] [INFO ] After 25884ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:83
Fused 83 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 205 out of 1429 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1429/1429 places, 150573/150573 transitions.
Applied a total of 0 rules in 1072 ms. Remains 1429 /1429 variables (removed 0) and now considering 150573/150573 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1072 ms. Remains : 1429/1429 places, 150573/150573 transitions.
[2023-03-16 13:51:08] [INFO ] Flatten gal took : 2807 ms
[2023-03-16 13:51:11] [INFO ] Flatten gal took : 3296 ms
[2023-03-16 13:51:18] [INFO ] Input system was already deterministic with 151085 transitions.
Computed a total of 1 stabilizing places and 1 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 651 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 654 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 13:51:22] [INFO ] Flatten gal took : 2826 ms
[2023-03-16 13:51:25] [INFO ] Flatten gal took : 3251 ms
[2023-03-16 13:51:32] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 624 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 628 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 13:51:36] [INFO ] Flatten gal took : 2782 ms
[2023-03-16 13:51:39] [INFO ] Flatten gal took : 3256 ms
[2023-03-16 13:51:45] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 624 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 626 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 13:51:49] [INFO ] Flatten gal took : 2794 ms
[2023-03-16 13:51:53] [INFO ] Flatten gal took : 3225 ms
[2023-03-16 13:51:59] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 622 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 625 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 13:52:03] [INFO ] Flatten gal took : 2812 ms
[2023-03-16 13:52:06] [INFO ] Flatten gal took : 3217 ms
[2023-03-16 13:52:12] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 664 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 668 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 13:52:16] [INFO ] Flatten gal took : 2804 ms
[2023-03-16 13:52:20] [INFO ] Flatten gal took : 3196 ms
[2023-03-16 13:52:26] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 553 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 558 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 13:52:30] [INFO ] Flatten gal took : 2743 ms
[2023-03-16 13:52:33] [INFO ] Flatten gal took : 3058 ms
[2023-03-16 13:52:39] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 1138 ms. Remains 1428 /1429 variables (removed 1) and now considering 151084/151085 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1144 ms. Remains : 1428/1429 places, 151084/151085 transitions.
[2023-03-16 13:52:44] [INFO ] Flatten gal took : 3114 ms
[2023-03-16 13:52:47] [INFO ] Flatten gal took : 3433 ms
[2023-03-16 13:52:53] [INFO ] Input system was already deterministic with 151084 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 536 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 545 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 13:52:57] [INFO ] Flatten gal took : 2801 ms
[2023-03-16 13:53:00] [INFO ] Flatten gal took : 3247 ms
[2023-03-16 13:53:07] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 563 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 567 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 13:53:11] [INFO ] Flatten gal took : 2864 ms
[2023-03-16 13:53:14] [INFO ] Flatten gal took : 3045 ms
[2023-03-16 13:53:20] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 548 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 552 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 13:53:24] [INFO ] Flatten gal took : 2786 ms
[2023-03-16 13:53:27] [INFO ] Flatten gal took : 3213 ms
[2023-03-16 13:53:33] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 556 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 560 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 13:53:37] [INFO ] Flatten gal took : 2824 ms
[2023-03-16 13:53:40] [INFO ] Flatten gal took : 3223 ms
[2023-03-16 13:53:46] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 547 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 550 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 13:53:50] [INFO ] Flatten gal took : 2777 ms
[2023-03-16 13:53:53] [INFO ] Flatten gal took : 3192 ms
[2023-03-16 13:54:00] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 551 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 554 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 13:54:04] [INFO ] Flatten gal took : 2832 ms
[2023-03-16 13:54:07] [INFO ] Flatten gal took : 3026 ms
[2023-03-16 13:54:13] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 1119 ms. Remains 1428 /1429 variables (removed 1) and now considering 151084/151085 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1124 ms. Remains : 1428/1429 places, 151084/151085 transitions.
[2023-03-16 13:54:17] [INFO ] Flatten gal took : 3081 ms
[2023-03-16 13:54:21] [INFO ] Flatten gal took : 3719 ms
[2023-03-16 13:54:27] [INFO ] Input system was already deterministic with 151084 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 639 ms. (steps per millisecond=15 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 63 ms. (steps per millisecond=158 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 6952 steps, run timeout after 3006 ms. (steps per millisecond=2 ) properties seen :{}
Probabilistic random walk after 6952 steps, saw 5964 distinct states, run finished after 3006 ms. (steps per millisecond=2 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-16 13:54:31] [INFO ] Flow matrix only has 84690 transitions (discarded 66394 similar events)
// Phase 1: matrix 84690 rows 1428 cols
[2023-03-16 13:54:32] [INFO ] Computed 18 place invariants in 280 ms
[2023-03-16 13:54:32] [INFO ] [Real]Absence check using 18 positive place invariants in 15 ms returned sat
[2023-03-16 13:54:52] [INFO ] After 20396ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-16 13:54:53] [INFO ] State equation strengthened by 773 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Broken pipe ...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:669)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 13:54:57] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 13:54:57] [INFO ] After 25042ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 0 ms.
Support contains 2 out of 1428 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1428/1428 places, 151084/151084 transitions.
Drop transitions removed 512 transitions
Reduce isomorphic transitions removed 512 transitions.
Iterating post reduction 0 with 512 rules applied. Total rules applied 512 place count 1428 transition count 150572
Applied a total of 512 rules in 1415 ms. Remains 1428 /1428 variables (removed 0) and now considering 150572/151084 (removed 512) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1419 ms. Remains : 1428/1428 places, 150572/151084 transitions.
Finished random walk after 82345 steps, including 0 resets, run visited all 1 properties in 7785 ms. (steps per millisecond=10 )
FORMULA RERS17pb114-PT-8-CTLFireability-13 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 555 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 559 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 13:55:10] [INFO ] Flatten gal took : 2809 ms
[2023-03-16 13:55:13] [INFO ] Flatten gal took : 3272 ms
[2023-03-16 13:55:19] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 543 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 547 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 13:55:23] [INFO ] Flatten gal took : 2779 ms
[2023-03-16 13:55:26] [INFO ] Flatten gal took : 3274 ms
[2023-03-16 13:55:32] [INFO ] Input system was already deterministic with 151085 transitions.
[2023-03-16 13:55:36] [INFO ] Flatten gal took : 3116 ms
[2023-03-16 13:55:40] [INFO ] Flatten gal took : 3323 ms
[2023-03-16 13:55:40] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2023-03-16 13:55:40] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 1429 places, 151085 transitions and 604235 arcs took 307 ms.
Total runtime 474048 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT RERS17pb114-PT-8
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393232 kB
MemFree: 188472 kB
After kill :
MemTotal: 16393232 kB
MemFree: 16266892 kB
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:394
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 321 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 326 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 331 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 336 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 341 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 346 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 351 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 356 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 361 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 366 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 371 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 376 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 381 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 386 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 391 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 396 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 401 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 406 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 411 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 416 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 421 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 426 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 431 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 436 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 441 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 446 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 451 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 456 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 461 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 466 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 471 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 476 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 481 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 486 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 491 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 496 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 501 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 506 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 511 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 516 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 521 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 526 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 531 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 536 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 541 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 546 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 551 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 556 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 561 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 566 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 571 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 576 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 581 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 586 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 591 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 596 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 601 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 606 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 611 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 616 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 621 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 626 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 631 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 636 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 641 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 646 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 651 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 656 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 661 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 666 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 671 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 676 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 681 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 686 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 691 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 696 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 701 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 706 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 711 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 716 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 721 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 726 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 731 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 736 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 741 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 746 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 751 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 756 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 761 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 766 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 771 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 776 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 781 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 786 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 791 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 796 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 801 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 806 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 811 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 816 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 821 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 826 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 831 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 836 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 841 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 846 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 851 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 856 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 861 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 866 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 871 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 876 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 881 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 886 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 891 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 896 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 901 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 906 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 911 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 916 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 921 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 606.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 926 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 931 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 936 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 941 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 946 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 951 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 956 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 961 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 966 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 971 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 976 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 981 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 986 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 991 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 996 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1001 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1006 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1011 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1016 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1021 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1026 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1031 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1036 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1041 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1046 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1051 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1056 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1061 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1066 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1071 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1076 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1081 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1086 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1091 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1096 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1101 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1106 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1111 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1116 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1121 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1126 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1131 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1136 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1141 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1146 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1151 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1156 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1161 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1166 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1171 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1176 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1181 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1186 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1191 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1196 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1201 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1206 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1211 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1216 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1221 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1226 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1231 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1236 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1241 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1246 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1251 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1256 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1261 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1266 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1271 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1276 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1281 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1286 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1291 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1296 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1301 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1306 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1311 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1316 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1321 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1326 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1331 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1336 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1341 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1346 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1351 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1356 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1361 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1366 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1371 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1376 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1381 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1386 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1391 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1396 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1401 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1406 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1411 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1416 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1421 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1426 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1431 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1436 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1441 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1446 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1451 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1456 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1461 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1466 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1471 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1476 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1481 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1486 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1491 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1496 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1501 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1506 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1511 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1517 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1522 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1527 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1532 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1537 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1542 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1547 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 627.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1552 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1557 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1562 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1567 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1572 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1577 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1582 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1587 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1592 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1597 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1602 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1607 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1612 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1617 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1622 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1627 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1632 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1637 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1642 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1647 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1652 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1657 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1662 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1667 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1672 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1677 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1682 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1687 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1692 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1697 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1702 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1707 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1712 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1717 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1722 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1727 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1732 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1737 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1742 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1747 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1752 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1757 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1762 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1767 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1772 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1777 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1782 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1787 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1792 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1797 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1802 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1807 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1812 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1817 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1822 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1827 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1832 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1837 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1842 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1847 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1852 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1857 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1862 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1867 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1872 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1877 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1882 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1887 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1892 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1897 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1902 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1907 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1912 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1917 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1922 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1927 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1932 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1937 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1942 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1947 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1952 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1957 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1962 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1967 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1972 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1977 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1982 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1987 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1992 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1997 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2002 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2007 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2012 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2017 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2022 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2027 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2032 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2037 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2042 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2047 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2052 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2057 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2062 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2067 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2072 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2077 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2082 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2087 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2092 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2097 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2102 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2107 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2112 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2117 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2122 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2127 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2132 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2137 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2142 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2147 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2152 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2157 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2162 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2167 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2172 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2177 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2182 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 636.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2187 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2192 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2197 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2202 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2207 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2212 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2217 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2222 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2227 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2232 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2237 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2242 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2247 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2252 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2257 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2262 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2267 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2272 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2277 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2282 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2287 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2292 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2297 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2302 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2307 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2312 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2317 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2322 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2327 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2332 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2337 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2342 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2347 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2352 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2357 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2362 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2367 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2372 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2377 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2382 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2387 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2392 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2397 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2402 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2407 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2412 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2417 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2422 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2427 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2432 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2437 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2442 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2447 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2452 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2457 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2462 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2467 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2472 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2477 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2482 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2487 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2492 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2497 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2502 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2507 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2512 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2517 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2522 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2527 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2532 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2537 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2542 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2547 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2552 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2557 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2562 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2567 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2572 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2577 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2582 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2587 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2592 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2597 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2602 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2607 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2612 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2617 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2622 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2627 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2632 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2637 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2642 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2647 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2652 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2657 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2662 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2667 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2672 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2677 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2682 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2687 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2692 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2697 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2702 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2707 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2712 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2717 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2722 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2727 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2732 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2737 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2742 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2747 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2752 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2757 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2762 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2767 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 584.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2772 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2777 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2782 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2787 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2792 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2797 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2802 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2807 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2812 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2817 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2822 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2827 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2832 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2837 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2842 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2847 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2852 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2857 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2862 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2867 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2872 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2877 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2882 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2887 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2892 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2897 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2902 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2907 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2912 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2917 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2922 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2927 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2932 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2937 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2942 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2948 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2953 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2958 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2963 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2968 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2973 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2978 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2983 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2988 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2993 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2998 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3003 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3008 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3013 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3018 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3023 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3028 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3033 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3038 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3043 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3048 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3053 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3058 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3063 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3068 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3073 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3078 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3083 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3088 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3093 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3098 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3103 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3108 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3113 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3118 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-8-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb114-PT-8-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-8-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-8-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3123 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: caught signal Terminated - aborting LoLA
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb114-PT-8-CTLFireability-00: CTL unknown AGGR
RERS17pb114-PT-8-CTLFireability-01: DISJ unknown DISJ
RERS17pb114-PT-8-CTLFireability-02: CTL unknown AGGR
RERS17pb114-PT-8-CTLFireability-03: CTL unknown AGGR
RERS17pb114-PT-8-CTLFireability-04: CTL unknown AGGR
RERS17pb114-PT-8-CTLFireability-05: CTL unknown AGGR
RERS17pb114-PT-8-CTLFireability-06: DISJ unknown DISJ
RERS17pb114-PT-8-CTLFireability-07: CTL unknown AGGR
RERS17pb114-PT-8-CTLFireability-08: CTL unknown AGGR
RERS17pb114-PT-8-CTLFireability-09: CTL unknown AGGR
RERS17pb114-PT-8-CTLFireability-10: DISJ unknown DISJ
RERS17pb114-PT-8-CTLFireability-11: CTL unknown AGGR
RERS17pb114-PT-8-CTLFireability-12: CTL unknown AGGR
RERS17pb114-PT-8-CTLFireability-14: CTL unknown AGGR
RERS17pb114-PT-8-CTLFireability-15: CONJ unknown CONJ
Time elapsed: 3123 secs. Pages in use: 0
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RERS17pb114-PT-8"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is RERS17pb114-PT-8, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r327-tall-167889199200130"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/RERS17pb114-PT-8.tgz
mv RERS17pb114-PT-8 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;