Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r327-tall-167889199200114.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is RERS17pb114-PT-6, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r327-tall-167889199200114
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 73M
-rw-r--r-- 1 mcc users 6.6K Feb 26 04:41 CTLCardinality.txt
-rw-r--r-- 1 mcc users 72K Feb 26 04:41 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.7K Feb 26 04:37 CTLFireability.txt
-rw-r--r-- 1 mcc users 48K Feb 26 04:37 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:38 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 16:38 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Feb 25 16:38 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 16:38 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 26 04:51 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 152K Feb 26 04:51 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Feb 26 04:44 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 73K Feb 26 04:44 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:38 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:38 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 73M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RERS17pb114-PT-6-CTLFireability-00
FORMULA_NAME RERS17pb114-PT-6-CTLFireability-01
FORMULA_NAME RERS17pb114-PT-6-CTLFireability-02
FORMULA_NAME RERS17pb114-PT-6-CTLFireability-03
FORMULA_NAME RERS17pb114-PT-6-CTLFireability-04
FORMULA_NAME RERS17pb114-PT-6-CTLFireability-05
FORMULA_NAME RERS17pb114-PT-6-CTLFireability-06
FORMULA_NAME RERS17pb114-PT-6-CTLFireability-07
FORMULA_NAME RERS17pb114-PT-6-CTLFireability-08
FORMULA_NAME RERS17pb114-PT-6-CTLFireability-09
FORMULA_NAME RERS17pb114-PT-6-CTLFireability-10
FORMULA_NAME RERS17pb114-PT-6-CTLFireability-11
FORMULA_NAME RERS17pb114-PT-6-CTLFireability-12
FORMULA_NAME RERS17pb114-PT-6-CTLFireability-13
FORMULA_NAME RERS17pb114-PT-6-CTLFireability-14
FORMULA_NAME RERS17pb114-PT-6-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678967234458

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RERS17pb114-PT-6
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-16 11:47:16] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-16 11:47:16] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-16 11:47:18] [INFO ] Load time of PNML (sax parser for PT used): 1897 ms
[2023-03-16 11:47:18] [INFO ] Transformed 1446 places.
[2023-03-16 11:47:18] [INFO ] Transformed 151085 transitions.
[2023-03-16 11:47:18] [INFO ] Parsed PT model containing 1446 places and 151085 transitions and 604252 arcs in 2454 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 35 ms.
Support contains 201 out of 1446 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 1446/1446 places, 151085/151085 transitions.
Ensure Unique test removed 17 places
Iterating post reduction 0 with 17 rules applied. Total rules applied 17 place count 1429 transition count 151085
Applied a total of 17 rules in 1024 ms. Remains 1429 /1446 variables (removed 17) and now considering 151085/151085 (removed 0) transitions.
[2023-03-16 11:47:20] [INFO ] Flow matrix only has 84691 transitions (discarded 66394 similar events)
// Phase 1: matrix 84691 rows 1429 cols
[2023-03-16 11:47:21] [INFO ] Computed 18 place invariants in 452 ms
[2023-03-16 11:47:29] [INFO ] Implicit Places using invariants in 8568 ms returned []
Implicit Place search using SMT only with invariants took 8598 ms to find 0 implicit places.
[2023-03-16 11:47:29] [INFO ] Flow matrix only has 84691 transitions (discarded 66394 similar events)
[2023-03-16 11:47:29] [INFO ] Invariant cache hit.
[2023-03-16 11:47:59] [INFO ] Performed 96161/151085 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 11:48:16] [INFO ] Dead Transitions using invariants and state equation in 47427 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 1429/1446 places, 151085/151085 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 57070 ms. Remains : 1429/1446 places, 151085/151085 transitions.
Support contains 201 out of 1429 places after structural reductions.
[2023-03-16 11:48:21] [INFO ] Flatten gal took : 3434 ms
[2023-03-16 11:48:24] [INFO ] Flatten gal took : 3186 ms
[2023-03-16 11:48:32] [INFO ] Input system was already deterministic with 151085 transitions.
Support contains 199 out of 1429 places (down from 201) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1542 ms. (steps per millisecond=6 ) properties (out of 84) seen :2
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 43 ms. (steps per millisecond=23 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 41 ms. (steps per millisecond=24 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=31 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=30 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=31 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 82) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 82) seen :0
Interrupted probabilistic random walk after 8949 steps, run timeout after 6003 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 8949 steps, saw 7277 distinct states, run finished after 6010 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 82 properties.
[2023-03-16 11:48:42] [INFO ] Flow matrix only has 84691 transitions (discarded 66394 similar events)
[2023-03-16 11:48:42] [INFO ] Invariant cache hit.
[2023-03-16 11:48:44] [INFO ] [Real]Absence check using 18 positive place invariants in 17 ms returned sat
[2023-03-16 11:48:45] [INFO ] After 3208ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:82
[2023-03-16 11:48:47] [INFO ] [Nat]Absence check using 18 positive place invariants in 18 ms returned sat
[2023-03-16 11:49:10] [INFO ] After 21367ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :82
[2023-03-16 11:49:12] [INFO ] State equation strengthened by 2342 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 11:49:12] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 11:49:12] [INFO ] After 26421ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:82
Fused 82 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 195 out of 1429 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Drop transitions removed 512 transitions
Reduce isomorphic transitions removed 512 transitions.
Iterating post reduction 0 with 512 rules applied. Total rules applied 512 place count 1429 transition count 150573
Applied a total of 512 rules in 1535 ms. Remains 1429 /1429 variables (removed 0) and now considering 150573/151085 (removed 512) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1539 ms. Remains : 1429/1429 places, 150573/151085 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 836 ms. (steps per millisecond=11 ) properties (out of 82) seen :4
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 36 ms. (steps per millisecond=27 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 419 ms. (steps per millisecond=2 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 268 ms. (steps per millisecond=3 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=30 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=31 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=31 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=31 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=30 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 34 ms. (steps per millisecond=29 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 78) seen :0
Interrupted probabilistic random walk after 7797 steps, run timeout after 6002 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 7797 steps, saw 6998 distinct states, run finished after 6002 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 78 properties.
[2023-03-16 11:49:23] [INFO ] Flow matrix only has 84690 transitions (discarded 65883 similar events)
// Phase 1: matrix 84690 rows 1429 cols
[2023-03-16 11:49:23] [INFO ] Computed 18 place invariants in 297 ms
[2023-03-16 11:49:25] [INFO ] [Real]Absence check using 18 positive place invariants in 16 ms returned sat
[2023-03-16 11:49:48] [INFO ] After 21909ms SMT Verify possible using state equation in real domain returned unsat :0 sat :12 real:65
[2023-03-16 11:49:49] [INFO ] State equation strengthened by 2341 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 11:49:49] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 11:49:49] [INFO ] After 26580ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Fused 78 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 189 out of 1429 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1429/1429 places, 150573/150573 transitions.
Applied a total of 0 rules in 1264 ms. Remains 1429 /1429 variables (removed 0) and now considering 150573/150573 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1265 ms. Remains : 1429/1429 places, 150573/150573 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1013 ms. (steps per millisecond=9 ) properties (out of 78) seen :4
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=30 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=31 ) properties (out of 74) seen :0
Interrupted probabilistic random walk after 7780 steps, run timeout after 6001 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 7780 steps, saw 6983 distinct states, run finished after 6003 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 74 properties.
[2023-03-16 11:49:59] [INFO ] Flow matrix only has 84690 transitions (discarded 65883 similar events)
[2023-03-16 11:49:59] [INFO ] Invariant cache hit.
[2023-03-16 11:50:01] [INFO ] [Real]Absence check using 18 positive place invariants in 17 ms returned sat
[2023-03-16 11:50:02] [INFO ] After 2910ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:74
[2023-03-16 11:50:04] [INFO ] [Nat]Absence check using 18 positive place invariants in 17 ms returned sat
[2023-03-16 11:50:27] [INFO ] After 21587ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :74
[2023-03-16 11:50:29] [INFO ] State equation strengthened by 2341 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 11:50:29] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 11:50:29] [INFO ] After 26324ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:74
Fused 74 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 182 out of 1429 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1429/1429 places, 150573/150573 transitions.
Applied a total of 0 rules in 1283 ms. Remains 1429 /1429 variables (removed 0) and now considering 150573/150573 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1283 ms. Remains : 1429/1429 places, 150573/150573 transitions.
[2023-03-16 11:50:33] [INFO ] Flatten gal took : 2750 ms
[2023-03-16 11:50:37] [INFO ] Flatten gal took : 3115 ms
[2023-03-16 11:50:43] [INFO ] Input system was already deterministic with 151085 transitions.
Computed a total of 1 stabilizing places and 1 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 637 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 641 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 11:50:48] [INFO ] Flatten gal took : 2755 ms
[2023-03-16 11:50:51] [INFO ] Flatten gal took : 3414 ms
[2023-03-16 11:50:58] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 642 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 647 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 11:51:02] [INFO ] Flatten gal took : 2757 ms
[2023-03-16 11:51:05] [INFO ] Flatten gal took : 3229 ms
[2023-03-16 11:51:11] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 1294 ms. Remains 1428 /1429 variables (removed 1) and now considering 151084/151085 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1299 ms. Remains : 1428/1429 places, 151084/151085 transitions.
[2023-03-16 11:51:16] [INFO ] Flatten gal took : 3101 ms
[2023-03-16 11:51:20] [INFO ] Flatten gal took : 3503 ms
[2023-03-16 11:51:26] [INFO ] Input system was already deterministic with 151084 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 628 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 631 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 11:51:30] [INFO ] Flatten gal took : 2761 ms
[2023-03-16 11:51:33] [INFO ] Flatten gal took : 3198 ms
[2023-03-16 11:51:39] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 650 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 652 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 11:51:43] [INFO ] Flatten gal took : 2818 ms
[2023-03-16 11:51:46] [INFO ] Flatten gal took : 3220 ms
[2023-03-16 11:51:53] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 544 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 548 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 11:51:57] [INFO ] Flatten gal took : 2713 ms
[2023-03-16 11:52:00] [INFO ] Flatten gal took : 3237 ms
[2023-03-16 11:52:06] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 537 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 539 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 11:52:10] [INFO ] Flatten gal took : 2766 ms
[2023-03-16 11:52:13] [INFO ] Flatten gal took : 3272 ms
[2023-03-16 11:52:20] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 555 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 559 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 11:52:23] [INFO ] Flatten gal took : 2765 ms
[2023-03-16 11:52:27] [INFO ] Flatten gal took : 3241 ms
[2023-03-16 11:52:33] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 1160 ms. Remains 1428 /1429 variables (removed 1) and now considering 151084/151085 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1164 ms. Remains : 1428/1429 places, 151084/151085 transitions.
[2023-03-16 11:52:37] [INFO ] Flatten gal took : 3011 ms
[2023-03-16 11:52:41] [INFO ] Flatten gal took : 3186 ms
[2023-03-16 11:52:47] [INFO ] Input system was already deterministic with 151084 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 809 ms. (steps per millisecond=12 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 66 ms. (steps per millisecond=151 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 5378 steps, run timeout after 3005 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 5378 steps, saw 4534 distinct states, run finished after 3005 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-16 11:52:51] [INFO ] Flow matrix only has 84690 transitions (discarded 66394 similar events)
// Phase 1: matrix 84690 rows 1428 cols
[2023-03-16 11:52:51] [INFO ] Computed 18 place invariants in 289 ms
[2023-03-16 11:52:51] [INFO ] [Real]Absence check using 18 positive place invariants in 15 ms returned sat
[2023-03-16 11:53:13] [INFO ] After 21431ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-16 11:53:14] [INFO ] State equation strengthened by 773 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Broken pipe ...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:669)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 11:53:16] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 11:53:16] [INFO ] After 25022ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 0 ms.
Support contains 2 out of 1428 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1428/1428 places, 151084/151084 transitions.
Drop transitions removed 512 transitions
Reduce isomorphic transitions removed 512 transitions.
Iterating post reduction 0 with 512 rules applied. Total rules applied 512 place count 1428 transition count 150572
Applied a total of 512 rules in 1533 ms. Remains 1428 /1428 variables (removed 0) and now considering 150572/151084 (removed 512) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1538 ms. Remains : 1428/1428 places, 150572/151084 transitions.
Finished random walk after 20065 steps, including 0 resets, run visited all 1 properties in 2726 ms. (steps per millisecond=7 )
FORMULA RERS17pb114-PT-6-CTLFireability-08 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in SI_CTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 1223 ms. Remains 1428 /1429 variables (removed 1) and now considering 151084/151085 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1228 ms. Remains : 1428/1429 places, 151084/151085 transitions.
[2023-03-16 11:53:26] [INFO ] Flatten gal took : 3538 ms
[2023-03-16 11:53:30] [INFO ] Flatten gal took : 3590 ms
[2023-03-16 11:53:36] [INFO ] Input system was already deterministic with 151084 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 564 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 568 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 11:53:40] [INFO ] Flatten gal took : 2761 ms
[2023-03-16 11:53:43] [INFO ] Flatten gal took : 3246 ms
[2023-03-16 11:53:50] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 539 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 543 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 11:53:53] [INFO ] Flatten gal took : 2753 ms
[2023-03-16 11:53:57] [INFO ] Flatten gal took : 3218 ms
[2023-03-16 11:54:03] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 588 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 593 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 11:54:07] [INFO ] Flatten gal took : 2759 ms
[2023-03-16 11:54:10] [INFO ] Flatten gal took : 3194 ms
[2023-03-16 11:54:16] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 556 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 562 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 11:54:20] [INFO ] Flatten gal took : 2732 ms
[2023-03-16 11:54:23] [INFO ] Flatten gal took : 3226 ms
[2023-03-16 11:54:30] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 581 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 586 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 11:54:34] [INFO ] Flatten gal took : 2747 ms
[2023-03-16 11:54:37] [INFO ] Flatten gal took : 3077 ms
[2023-03-16 11:54:43] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 1067 ms. Remains 1428 /1429 variables (removed 1) and now considering 151084/151085 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1072 ms. Remains : 1428/1429 places, 151084/151085 transitions.
[2023-03-16 11:54:48] [INFO ] Flatten gal took : 3071 ms
[2023-03-16 11:54:51] [INFO ] Flatten gal took : 3575 ms
[2023-03-16 11:54:57] [INFO ] Input system was already deterministic with 151084 transitions.
[2023-03-16 11:55:01] [INFO ] Flatten gal took : 3064 ms
[2023-03-16 11:55:04] [INFO ] Flatten gal took : 3564 ms
[2023-03-16 11:55:04] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2023-03-16 11:55:05] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 1429 places, 151085 transitions and 604235 arcs took 299 ms.
Total runtime 469165 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT RERS17pb114-PT-6
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 2214184 kB
After kill :
MemTotal: 16393216 kB
MemFree: 15928700 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 273 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 278 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 283 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 288 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 293 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 298 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 303 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 308 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 313 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 318 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 323 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 328 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 333 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 338 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 343 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 348 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 353 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 358 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 363 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 368 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 373 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 378 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 383 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 388 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 393 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 398 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 403 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 408 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 413 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 418 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 423 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 428 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 433 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 438 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 443 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 448 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 453 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 458 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 463 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 468 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 473 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 478 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 483 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 488 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 493 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 498 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 503 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 508 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 513 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 518 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 523 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 528 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 533 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 538 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 543 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 548 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 553 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 558 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 563 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 568 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 573 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 578 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 583 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 588 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 593 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 598 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 603 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 608 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 613 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 618 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 623 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 628 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 633 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 638 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 643 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 648 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 653 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 658 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 663 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 668 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 673 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 678 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 683 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 688 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 693 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 698 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 703 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 708 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 713 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 718 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 723 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 728 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 733 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 738 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 743 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 748 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 753 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 758 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 763 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 768 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 773 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 778 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 783 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 788 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 793 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 798 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 532.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 803 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 808 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 813 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 818 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 823 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 828 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 834 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 839 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 844 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 849 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 854 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 859 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 864 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 869 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 874 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 879 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 884 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 889 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 894 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 899 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 904 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 909 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 914 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 919 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 924 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 929 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 934 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 939 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 944 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 949 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 954 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 959 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 964 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 969 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 974 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 979 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 984 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 989 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 994 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 999 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1004 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1009 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1014 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1019 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1024 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1029 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1034 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1039 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1044 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1049 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1054 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1059 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1064 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1069 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1074 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1079 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1084 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1089 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1094 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1099 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1104 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1109 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1114 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1119 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1124 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1129 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1134 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1139 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1144 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1149 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1154 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1159 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1164 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1169 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1174 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1179 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1184 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1189 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1194 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1199 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1204 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1209 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1214 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1219 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1224 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1229 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1234 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1239 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1244 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1249 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1254 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1259 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1264 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1269 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1274 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1279 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1284 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1289 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1294 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1299 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1304 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1309 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1314 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1319 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1324 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1329 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1334 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1339 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1344 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1349 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1354 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 558.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1359 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1364 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1369 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1374 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1379 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1384 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1389 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1394 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1399 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1404 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1409 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1414 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1419 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1424 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1429 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1434 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1439 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1444 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1449 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1454 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1459 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1464 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1469 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1474 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1479 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1484 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1489 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1494 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1499 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1504 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1509 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1514 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1519 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1524 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1529 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1534 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1539 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1544 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1549 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1554 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1559 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1564 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1569 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1574 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1579 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1584 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1589 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1594 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1599 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1604 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1609 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1614 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1619 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1624 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1629 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1634 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1639 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1644 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1649 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1654 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1659 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1664 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1669 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1674 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1679 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1684 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1689 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1694 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1699 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1704 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1709 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1714 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1719 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1724 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1729 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1734 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1739 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1744 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1749 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1754 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1759 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1764 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1769 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1774 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1779 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1784 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1789 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1794 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1799 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1804 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1809 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1814 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1819 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1824 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1829 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1834 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1839 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1844 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1849 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1854 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1859 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1864 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1869 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1874 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1879 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1884 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1889 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1894 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1899 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1904 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1909 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1914 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1919 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 564.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1924 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1929 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1934 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1939 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1944 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1949 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1954 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1959 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1964 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1969 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1974 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1979 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1984 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1989 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1994 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1999 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2004 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2009 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2014 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2019 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2024 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2029 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2034 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2039 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2044 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2049 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2054 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2059 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2064 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2069 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2074 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2079 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2084 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2089 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2094 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2099 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2104 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2109 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2114 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2119 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2124 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2129 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2134 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2139 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2144 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2149 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2154 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2159 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2164 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2169 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2174 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2179 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2184 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2189 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2194 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2199 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2204 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2209 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2214 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2219 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2224 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2229 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2234 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2239 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2244 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2249 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2254 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2259 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2264 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2269 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2274 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2279 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2284 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2289 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2294 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2299 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2304 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2309 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2314 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2319 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2324 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2329 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2334 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2339 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2345 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2350 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2355 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2360 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2365 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2370 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2375 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2380 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2385 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2390 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2395 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2400 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2405 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2410 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2415 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2420 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2425 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2430 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2435 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2440 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2445 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2450 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2455 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2460 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2465 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2470 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2475 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2480 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2485 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2490 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2495 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2500 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2505 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2510 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2515 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2520 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2525 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2530 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2535 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2540 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2545 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 626.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2550 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2555 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2560 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2565 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2570 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2575 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2580 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2585 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2590 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2595 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2600 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2605 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2610 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2615 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2620 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2625 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2630 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2635 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2640 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2645 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2650 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2655 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2660 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2665 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2670 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2675 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2680 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2685 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2690 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2695 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2700 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2705 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2710 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2715 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2720 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2725 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2730 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2735 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2740 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2745 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2750 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2755 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2760 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2765 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2770 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2775 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2780 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2785 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2790 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2795 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2800 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2805 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2810 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2815 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2820 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2825 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2830 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2835 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2840 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2845 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2850 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2855 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2860 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2865 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2870 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2875 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2880 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2885 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2890 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2895 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2900 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2905 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2910 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2915 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2920 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2925 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2930 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2935 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2940 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2945 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2950 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2955 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2960 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2965 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2970 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2975 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2980 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2985 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2990 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2995 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3000 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3005 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3010 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3015 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3020 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3025 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3030 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3035 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3040 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3045 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3050 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3055 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3060 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3065 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3070 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3075 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3080 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3085 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3090 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3095 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3100 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3105 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3110 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3115 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3120 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-6-CTLFireability-00: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-6-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-6-CTLFireability-15: EFEG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3125 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: caught signal Terminated - aborting LoLA

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb114-PT-6-CTLFireability-00: DISJ unknown DISJ
RERS17pb114-PT-6-CTLFireability-01: CTL unknown AGGR
RERS17pb114-PT-6-CTLFireability-02: CTL unknown AGGR
RERS17pb114-PT-6-CTLFireability-03: CTL unknown AGGR
RERS17pb114-PT-6-CTLFireability-04: CTL unknown AGGR
RERS17pb114-PT-6-CTLFireability-05: CTL unknown AGGR
RERS17pb114-PT-6-CTLFireability-06: CTL unknown AGGR
RERS17pb114-PT-6-CTLFireability-07: CTL unknown AGGR
RERS17pb114-PT-6-CTLFireability-09: CTL unknown AGGR
RERS17pb114-PT-6-CTLFireability-10: CTL unknown AGGR
RERS17pb114-PT-6-CTLFireability-11: CTL unknown AGGR
RERS17pb114-PT-6-CTLFireability-12: CTL unknown AGGR
RERS17pb114-PT-6-CTLFireability-13: CTL unknown AGGR
RERS17pb114-PT-6-CTLFireability-14: CTL unknown AGGR
RERS17pb114-PT-6-CTLFireability-15: EFEG unknown AGGR


Time elapsed: 3128 secs. Pages in use: 0