fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r327-tall-167889199200098
Last Updated
May 14, 2023

About the Execution of LoLa+red for RERS17pb114-PT-4

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
12521.647 3600000.00 3728529.00 9311.30 ????????????T??? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r327-tall-167889199200098.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is RERS17pb114-PT-4, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r327-tall-167889199200098
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 73M
-rw-r--r-- 1 mcc users 5.7K Feb 26 04:51 CTLCardinality.txt
-rw-r--r-- 1 mcc users 58K Feb 26 04:51 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.8K Feb 26 04:47 CTLFireability.txt
-rw-r--r-- 1 mcc users 49K Feb 26 04:47 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:38 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:38 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.1K Feb 25 16:38 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:38 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 26 04:57 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 128K Feb 26 04:57 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.3K Feb 26 04:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 41K Feb 26 04:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:38 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:38 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 73M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RERS17pb114-PT-4-CTLFireability-00
FORMULA_NAME RERS17pb114-PT-4-CTLFireability-01
FORMULA_NAME RERS17pb114-PT-4-CTLFireability-02
FORMULA_NAME RERS17pb114-PT-4-CTLFireability-03
FORMULA_NAME RERS17pb114-PT-4-CTLFireability-04
FORMULA_NAME RERS17pb114-PT-4-CTLFireability-05
FORMULA_NAME RERS17pb114-PT-4-CTLFireability-06
FORMULA_NAME RERS17pb114-PT-4-CTLFireability-07
FORMULA_NAME RERS17pb114-PT-4-CTLFireability-08
FORMULA_NAME RERS17pb114-PT-4-CTLFireability-09
FORMULA_NAME RERS17pb114-PT-4-CTLFireability-10
FORMULA_NAME RERS17pb114-PT-4-CTLFireability-11
FORMULA_NAME RERS17pb114-PT-4-CTLFireability-12
FORMULA_NAME RERS17pb114-PT-4-CTLFireability-13
FORMULA_NAME RERS17pb114-PT-4-CTLFireability-14
FORMULA_NAME RERS17pb114-PT-4-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678962045517

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RERS17pb114-PT-4
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-16 10:20:47] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-16 10:20:47] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-16 10:20:49] [INFO ] Load time of PNML (sax parser for PT used): 1841 ms
[2023-03-16 10:20:49] [INFO ] Transformed 1446 places.
[2023-03-16 10:20:49] [INFO ] Transformed 151085 transitions.
[2023-03-16 10:20:49] [INFO ] Parsed PT model containing 1446 places and 151085 transitions and 604252 arcs in 2366 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 33 ms.
Support contains 193 out of 1446 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 1446/1446 places, 151085/151085 transitions.
Ensure Unique test removed 17 places
Iterating post reduction 0 with 17 rules applied. Total rules applied 17 place count 1429 transition count 151085
Applied a total of 17 rules in 1143 ms. Remains 1429 /1446 variables (removed 17) and now considering 151085/151085 (removed 0) transitions.
[2023-03-16 10:20:51] [INFO ] Flow matrix only has 84691 transitions (discarded 66394 similar events)
// Phase 1: matrix 84691 rows 1429 cols
[2023-03-16 10:20:52] [INFO ] Computed 18 place invariants in 494 ms
[2023-03-16 10:20:59] [INFO ] Implicit Places using invariants in 7822 ms returned []
Implicit Place search using SMT only with invariants took 7852 ms to find 0 implicit places.
[2023-03-16 10:20:59] [INFO ] Flow matrix only has 84691 transitions (discarded 66394 similar events)
[2023-03-16 10:20:59] [INFO ] Invariant cache hit.
[2023-03-16 10:21:29] [INFO ] Performed 89552/151085 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 10:21:50] [INFO ] Dead Transitions using invariants and state equation in 50317 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 1429/1446 places, 151085/151085 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 59332 ms. Remains : 1429/1446 places, 151085/151085 transitions.
Support contains 193 out of 1429 places after structural reductions.
[2023-03-16 10:21:54] [INFO ] Flatten gal took : 3879 ms
[2023-03-16 10:21:58] [INFO ] Flatten gal took : 3568 ms
[2023-03-16 10:22:05] [INFO ] Input system was already deterministic with 151085 transitions.
Support contains 170 out of 1429 places (down from 193) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1364 ms. (steps per millisecond=7 ) properties (out of 67) seen :6
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 61) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 61) seen :0
Interrupted probabilistic random walk after 9554 steps, run timeout after 6005 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 9554 steps, saw 7824 distinct states, run finished after 6007 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 61 properties.
[2023-03-16 10:22:15] [INFO ] Flow matrix only has 84691 transitions (discarded 66394 similar events)
[2023-03-16 10:22:15] [INFO ] Invariant cache hit.
[2023-03-16 10:22:16] [INFO ] [Real]Absence check using 18 positive place invariants in 17 ms returned sat
[2023-03-16 10:22:40] [INFO ] After 22300ms SMT Verify possible using state equation in real domain returned unsat :0 sat :7 real:54
[2023-03-16 10:22:42] [INFO ] State equation strengthened by 2342 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 10:22:42] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 10:22:42] [INFO ] After 27104ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Fused 61 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 157 out of 1429 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Drop transitions removed 512 transitions
Reduce isomorphic transitions removed 512 transitions.
Iterating post reduction 0 with 512 rules applied. Total rules applied 512 place count 1429 transition count 150573
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 1 with 1 rules applied. Total rules applied 513 place count 1428 transition count 150572
Applied a total of 513 rules in 3554 ms. Remains 1428 /1429 variables (removed 1) and now considering 150572/151085 (removed 513) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 3560 ms. Remains : 1428/1429 places, 150572/151085 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1242 ms. (steps per millisecond=8 ) properties (out of 61) seen :4
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 57) seen :0
Interrupted probabilistic random walk after 7760 steps, run timeout after 6008 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 7760 steps, saw 6981 distinct states, run finished after 6008 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 57 properties.
[2023-03-16 10:22:54] [INFO ] Flow matrix only has 84689 transitions (discarded 65883 similar events)
// Phase 1: matrix 84689 rows 1428 cols
[2023-03-16 10:22:55] [INFO ] Computed 18 place invariants in 330 ms
[2023-03-16 10:22:56] [INFO ] [Real]Absence check using 18 positive place invariants in 17 ms returned sat
[2023-03-16 10:23:20] [INFO ] After 22328ms SMT Verify possible using state equation in real domain returned unsat :0 sat :8 real:49
[2023-03-16 10:23:21] [INFO ] State equation strengthened by 773 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 10:23:21] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 10:23:21] [INFO ] After 26091ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Fused 57 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 148 out of 1428 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1428/1428 places, 150572/150572 transitions.
Applied a total of 0 rules in 1339 ms. Remains 1428 /1428 variables (removed 0) and now considering 150572/150572 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1339 ms. Remains : 1428/1428 places, 150572/150572 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1027 ms. (steps per millisecond=9 ) properties (out of 57) seen :2
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 57 ms. (steps per millisecond=17 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 55) seen :0
Interrupted probabilistic random walk after 7263 steps, run timeout after 6004 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 7263 steps, saw 6523 distinct states, run finished after 6004 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 55 properties.
[2023-03-16 10:23:31] [INFO ] Flow matrix only has 84689 transitions (discarded 65883 similar events)
[2023-03-16 10:23:31] [INFO ] Invariant cache hit.
[2023-03-16 10:23:32] [INFO ] [Real]Absence check using 18 positive place invariants in 20 ms returned sat
[2023-03-16 10:23:56] [INFO ] After 22683ms SMT Verify possible using state equation in real domain returned unsat :0 sat :6 real:49
[2023-03-16 10:23:57] [INFO ] State equation strengthened by 773 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 10:23:57] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 10:23:57] [INFO ] After 25960ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Fused 55 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 140 out of 1428 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1428/1428 places, 150572/150572 transitions.
Applied a total of 0 rules in 1203 ms. Remains 1428 /1428 variables (removed 0) and now considering 150572/150572 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1205 ms. Remains : 1428/1428 places, 150572/150572 transitions.
[2023-03-16 10:24:01] [INFO ] Flatten gal took : 2797 ms
[2023-03-16 10:24:04] [INFO ] Flatten gal took : 3196 ms
[2023-03-16 10:24:11] [INFO ] Input system was already deterministic with 151085 transitions.
Computed a total of 1 stabilizing places and 1 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 631 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 635 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 10:24:15] [INFO ] Flatten gal took : 2853 ms
[2023-03-16 10:24:19] [INFO ] Flatten gal took : 3340 ms
[2023-03-16 10:24:25] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 632 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 635 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 10:24:29] [INFO ] Flatten gal took : 2822 ms
[2023-03-16 10:24:32] [INFO ] Flatten gal took : 3265 ms
[2023-03-16 10:24:39] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 696 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 703 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 10:24:43] [INFO ] Flatten gal took : 2839 ms
[2023-03-16 10:24:46] [INFO ] Flatten gal took : 3281 ms
[2023-03-16 10:24:52] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 757 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 762 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 10:24:57] [INFO ] Flatten gal took : 2865 ms
[2023-03-16 10:25:00] [INFO ] Flatten gal took : 3332 ms
[2023-03-16 10:25:06] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 1283 ms. Remains 1428 /1429 variables (removed 1) and now considering 151084/151085 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1288 ms. Remains : 1428/1429 places, 151084/151085 transitions.
[2023-03-16 10:25:11] [INFO ] Flatten gal took : 3132 ms
[2023-03-16 10:25:15] [INFO ] Flatten gal took : 3612 ms
[2023-03-16 10:25:21] [INFO ] Input system was already deterministic with 151084 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 561 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 565 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 10:25:25] [INFO ] Flatten gal took : 2814 ms
[2023-03-16 10:25:29] [INFO ] Flatten gal took : 3263 ms
[2023-03-16 10:25:35] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 645 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 649 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 10:25:40] [INFO ] Flatten gal took : 3238 ms
[2023-03-16 10:25:44] [INFO ] Flatten gal took : 3847 ms
[2023-03-16 10:25:50] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 562 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 566 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 10:25:54] [INFO ] Flatten gal took : 2971 ms
[2023-03-16 10:25:57] [INFO ] Flatten gal took : 3190 ms
[2023-03-16 10:26:04] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 549 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 553 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 10:26:08] [INFO ] Flatten gal took : 2813 ms
[2023-03-16 10:26:11] [INFO ] Flatten gal took : 3300 ms
[2023-03-16 10:26:17] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 557 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 562 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 10:26:21] [INFO ] Flatten gal took : 2809 ms
[2023-03-16 10:26:24] [INFO ] Flatten gal took : 3287 ms
[2023-03-16 10:26:31] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 569 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 572 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 10:26:35] [INFO ] Flatten gal took : 2851 ms
[2023-03-16 10:26:38] [INFO ] Flatten gal took : 3307 ms
[2023-03-16 10:26:44] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 565 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 571 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 10:26:48] [INFO ] Flatten gal took : 2907 ms
[2023-03-16 10:26:52] [INFO ] Flatten gal took : 3333 ms
[2023-03-16 10:26:58] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 1066 ms. Remains 1428 /1429 variables (removed 1) and now considering 151084/151085 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1069 ms. Remains : 1428/1429 places, 151084/151085 transitions.
[2023-03-16 10:27:03] [INFO ] Flatten gal took : 3134 ms
[2023-03-16 10:27:06] [INFO ] Flatten gal took : 3597 ms
[2023-03-16 10:27:13] [INFO ] Input system was already deterministic with 151084 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 761 ms. (steps per millisecond=13 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 67 ms. (steps per millisecond=149 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 4889 steps, run timeout after 3004 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 4889 steps, saw 3919 distinct states, run finished after 3004 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-16 10:27:17] [INFO ] Flow matrix only has 84690 transitions (discarded 66394 similar events)
// Phase 1: matrix 84690 rows 1428 cols
[2023-03-16 10:27:17] [INFO ] Computed 18 place invariants in 311 ms
[2023-03-16 10:27:18] [INFO ] [Real]Absence check using 18 positive place invariants in 25 ms returned sat
[2023-03-16 10:27:38] [INFO ] After 20434ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-16 10:27:39] [INFO ] State equation strengthened by 773 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Broken pipe ...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:669)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 10:27:42] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 10:27:42] [INFO ] After 25024ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 0 ms.
Support contains 2 out of 1428 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1428/1428 places, 151084/151084 transitions.
Drop transitions removed 512 transitions
Reduce isomorphic transitions removed 512 transitions.
Iterating post reduction 0 with 512 rules applied. Total rules applied 512 place count 1428 transition count 150572
Applied a total of 512 rules in 1394 ms. Remains 1428 /1428 variables (removed 0) and now considering 150572/151084 (removed 512) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1398 ms. Remains : 1428/1428 places, 150572/151084 transitions.
Interrupted random walk after 273775 steps, including 0 resets, run timeout after 30001 ms. (steps per millisecond=9 ) properties seen 0
Interrupted Best-First random walk after 762490 steps, including 2 resets, run timeout after 5001 ms. (steps per millisecond=152 ) properties seen 0
Interrupted probabilistic random walk after 176380 steps, run timeout after 105004 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 176380 steps, saw 163395 distinct states, run finished after 105008 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-16 10:30:04] [INFO ] Flow matrix only has 84689 transitions (discarded 65883 similar events)
// Phase 1: matrix 84689 rows 1428 cols
[2023-03-16 10:30:05] [INFO ] Computed 18 place invariants in 291 ms
[2023-03-16 10:30:05] [INFO ] [Real]Absence check using 18 positive place invariants in 16 ms returned sat
[2023-03-16 10:30:26] [INFO ] After 21588ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-16 10:30:27] [INFO ] State equation strengthened by 773 read => feed constraints.
[2023-03-16 10:30:35] [INFO ] After 7721ms SMT Verify possible using 773 Read/Feed constraints in real domain returned unsat :0 sat :1
[2023-03-16 10:30:48] [INFO ] Deduced a trap composed of 96 places in 11552 ms of which 16 ms to minimize.
[2023-03-16 10:31:00] [INFO ] Deduced a trap composed of 96 places in 10989 ms of which 3 ms to minimize.
[2023-03-16 10:31:12] [INFO ] Deduced a trap composed of 40 places in 10430 ms of which 3 ms to minimize.
[2023-03-16 10:31:23] [INFO ] Deduced a trap composed of 96 places in 10437 ms of which 3 ms to minimize.
[2023-03-16 10:31:35] [INFO ] Deduced a trap composed of 40 places in 10032 ms of which 2 ms to minimize.
[2023-03-16 10:31:45] [INFO ] Deduced a trap composed of 64 places in 9234 ms of which 1 ms to minimize.
[2023-03-16 10:31:55] [INFO ] Deduced a trap composed of 64 places in 8687 ms of which 2 ms to minimize.
[2023-03-16 10:32:05] [INFO ] Deduced a trap composed of 64 places in 8839 ms of which 2 ms to minimize.
[2023-03-16 10:32:15] [INFO ] Deduced a trap composed of 128 places in 8219 ms of which 1 ms to minimize.
[2023-03-16 10:32:23] [INFO ] Deduced a trap composed of 64 places in 7417 ms of which 1 ms to minimize.
[2023-03-16 10:32:32] [INFO ] Deduced a trap composed of 64 places in 7417 ms of which 1 ms to minimize.
[2023-03-16 10:32:40] [INFO ] Deduced a trap composed of 128 places in 6510 ms of which 1 ms to minimize.
[2023-03-16 10:32:47] [INFO ] Deduced a trap composed of 64 places in 5812 ms of which 0 ms to minimize.
[2023-03-16 10:32:54] [INFO ] Deduced a trap composed of 128 places in 5494 ms of which 0 ms to minimize.
[2023-03-16 10:32:58] [INFO ] Trap strengthening (SAT) tested/added 15/14 trap constraints in 143285 ms
[2023-03-16 10:32:59] [INFO ] After 151828ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-16 10:32:59] [INFO ] After 174249ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-16 10:32:59] [INFO ] [Nat]Absence check using 18 positive place invariants in 14 ms returned sat
[2023-03-16 10:33:21] [INFO ] After 21815ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-16 10:33:29] [INFO ] After 8236ms SMT Verify possible using 773 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-16 10:33:41] [INFO ] Deduced a trap composed of 96 places in 10964 ms of which 2 ms to minimize.
[2023-03-16 10:33:53] [INFO ] Deduced a trap composed of 96 places in 10240 ms of which 2 ms to minimize.
[2023-03-16 10:34:04] [INFO ] Deduced a trap composed of 40 places in 9834 ms of which 1 ms to minimize.
[2023-03-16 10:34:14] [INFO ] Deduced a trap composed of 96 places in 9612 ms of which 2 ms to minimize.
[2023-03-16 10:34:25] [INFO ] Deduced a trap composed of 40 places in 9797 ms of which 2 ms to minimize.
[2023-03-16 10:34:36] [INFO ] Deduced a trap composed of 64 places in 8920 ms of which 2 ms to minimize.
[2023-03-16 10:34:45] [INFO ] Deduced a trap composed of 64 places in 8611 ms of which 1 ms to minimize.
[2023-03-16 10:34:55] [INFO ] Deduced a trap composed of 64 places in 8549 ms of which 1 ms to minimize.
[2023-03-16 10:35:04] [INFO ] Deduced a trap composed of 128 places in 8066 ms of which 1 ms to minimize.
[2023-03-16 10:35:13] [INFO ] Deduced a trap composed of 64 places in 7537 ms of which 1 ms to minimize.
[2023-03-16 10:35:22] [INFO ] Deduced a trap composed of 64 places in 7622 ms of which 1 ms to minimize.
[2023-03-16 10:35:29] [INFO ] Deduced a trap composed of 128 places in 6513 ms of which 1 ms to minimize.
[2023-03-16 10:35:37] [INFO ] Deduced a trap composed of 64 places in 5848 ms of which 2 ms to minimize.
[2023-03-16 10:35:43] [INFO ] Deduced a trap composed of 128 places in 5597 ms of which 1 ms to minimize.
[2023-03-16 10:35:48] [INFO ] Trap strengthening (SAT) tested/added 15/14 trap constraints in 138698 ms
[2023-03-16 10:35:49] [INFO ] After 147683ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 1246 ms.
[2023-03-16 10:35:50] [INFO ] After 170950ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 0 ms.
Support contains 2 out of 1428 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1428/1428 places, 150572/150572 transitions.
Applied a total of 0 rules in 1167 ms. Remains 1428 /1428 variables (removed 0) and now considering 150572/150572 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1167 ms. Remains : 1428/1428 places, 150572/150572 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1428/1428 places, 150572/150572 transitions.
Applied a total of 0 rules in 1156 ms. Remains 1428 /1428 variables (removed 0) and now considering 150572/150572 (removed 0) transitions.
[2023-03-16 10:35:52] [INFO ] Flow matrix only has 84689 transitions (discarded 65883 similar events)
[2023-03-16 10:35:52] [INFO ] Invariant cache hit.
[2023-03-16 10:36:01] [INFO ] Implicit Places using invariants in 8798 ms returned []
Implicit Place search using SMT only with invariants took 8799 ms to find 0 implicit places.
[2023-03-16 10:36:01] [INFO ] Flow matrix only has 84689 transitions (discarded 65883 similar events)
[2023-03-16 10:36:01] [INFO ] Invariant cache hit.
[2023-03-16 10:36:31] [INFO ] Performed 96817/150572 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 10:36:48] [INFO ] Dead Transitions using invariants and state equation in 46654 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 56622 ms. Remains : 1428/1428 places, 150572/150572 transitions.
Finished random walk after 3919 steps, including 0 resets, run visited all 2 properties in 422 ms. (steps per millisecond=9 )
Interrupted random walk after 333114 steps, including 0 resets, run timeout after 30001 ms. (steps per millisecond=11 ) properties seen 0
Finished Best-First random walk after 352463 steps, including 1 resets, run visited all 1 properties in 1571 ms. (steps per millisecond=224 )
FORMULA RERS17pb114-PT-4-CTLFireability-12 TRUE TECHNIQUES TOPOLOGICAL BESTFIRST_WALK
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 556 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 559 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 10:37:24] [INFO ] Flatten gal took : 2837 ms
[2023-03-16 10:37:27] [INFO ] Flatten gal took : 3303 ms
[2023-03-16 10:37:36] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 677 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 682 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 10:37:40] [INFO ] Flatten gal took : 3216 ms
[2023-03-16 10:37:44] [INFO ] Flatten gal took : 3887 ms
[2023-03-16 10:37:51] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 564 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 566 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 10:37:55] [INFO ] Flatten gal took : 2831 ms
[2023-03-16 10:37:58] [INFO ] Flatten gal took : 3228 ms
[2023-03-16 10:38:05] [INFO ] Input system was already deterministic with 151085 transitions.
[2023-03-16 10:38:08] [INFO ] Flatten gal took : 3112 ms
[2023-03-16 10:38:12] [INFO ] Flatten gal took : 3309 ms
[2023-03-16 10:38:12] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-16 10:38:12] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 1429 places, 151085 transitions and 604235 arcs took 304 ms.
Total runtime 1045097 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT RERS17pb114-PT-4
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 3454236 kB
After kill :
MemTotal: 16393216 kB
MemFree: 15924576 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:394
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 226 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 231 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 236 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 241 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 246 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 251 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 256 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 261 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 266 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 271 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 276 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 281 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 286 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 291 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 296 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 301 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 306 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 311 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 316 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 321 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 326 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 331 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 336 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 341 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 346 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 351 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 356 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 361 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 366 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 371 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 376 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 381 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 386 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 391 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 396 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 401 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 406 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 411 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 416 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 421 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 426 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 431 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 436 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 441 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 446 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 451 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 456 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 461 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 466 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 471 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 476 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 481 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 486 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 491 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 496 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 501 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 506 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 511 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 516 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 521 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 526 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 531 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 536 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 541 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 546 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 551 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 556 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 561 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 566 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 571 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 576 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 581 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 586 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 591 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 596 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 601 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 606 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 612 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 617 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 622 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 627 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 632 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 637 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 642 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 647 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 652 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 657 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 662 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 667 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 672 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 677 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 682 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 687 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 692 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 697 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 702 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 707 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 712 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 717 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 722 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 727 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 732 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 737 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 742 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 747 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 752 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 757 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 762 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 767 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 772 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 777 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 782 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 787 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 792 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 797 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 802 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 807 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 812 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 817 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 822 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 827 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 609.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 832 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 837 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 842 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 847 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 852 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 857 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 862 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 867 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 872 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 877 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 882 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 887 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 892 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 897 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 902 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 907 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 912 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 917 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 922 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 927 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 932 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 937 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 942 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 947 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 952 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 957 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 962 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 967 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 972 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 977 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 982 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 987 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 992 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 997 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1002 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1007 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1012 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1017 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1022 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1027 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1032 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1037 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1042 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1047 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1052 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1057 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1062 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1067 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1072 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1077 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1082 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1087 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1092 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1097 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1102 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1107 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1112 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1117 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1122 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1127 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1132 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1137 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1142 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1147 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1152 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1157 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1162 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1167 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1172 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1177 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1182 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1187 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1192 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1197 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1202 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1207 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1212 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1217 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1222 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1227 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1232 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1237 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1242 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1247 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1252 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1257 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1262 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1267 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1272 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1277 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1282 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1287 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1292 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1297 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1302 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1307 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1312 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1317 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1322 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1327 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1332 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1337 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1342 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1347 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1352 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1357 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1362 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1367 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1372 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1377 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1382 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1387 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 561.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1392 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1397 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1402 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1407 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1412 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1417 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1422 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1427 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1432 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1437 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1442 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1447 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1452 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1457 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1462 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1467 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1472 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1477 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1482 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1487 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1492 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1497 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1502 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1507 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1512 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1517 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1522 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1527 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1532 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1537 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1542 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1547 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1552 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1557 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1562 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1567 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1572 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1577 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1582 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1587 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1592 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1597 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1602 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1607 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1612 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1617 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1622 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1627 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1632 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1637 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1642 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1647 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1652 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1657 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1662 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1667 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1672 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1677 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1682 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1687 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1692 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1697 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1702 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1707 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1712 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1717 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1722 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1727 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1732 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1737 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1742 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1747 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1752 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1757 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1762 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1767 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1772 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1777 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1782 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1787 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1792 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1797 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1802 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1807 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1812 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1817 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1822 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1827 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1832 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1837 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1842 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1847 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1852 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1857 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1862 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1867 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1872 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1877 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1882 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1887 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1892 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1897 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1902 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1907 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1912 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1917 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1922 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1927 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1932 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1937 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1942 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1947 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1952 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1957 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 567.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1962 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1967 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1972 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1977 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1982 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1987 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1992 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1997 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2002 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2007 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2012 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2017 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2022 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2027 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2032 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2037 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2042 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2047 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2052 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2057 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2062 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2067 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2072 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2077 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2082 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2087 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2092 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2097 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2102 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2107 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2112 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2117 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2122 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2127 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2132 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2137 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2142 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2147 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2152 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2157 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2162 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2167 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2172 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2177 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2182 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2187 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2192 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2197 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2202 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2207 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2212 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2217 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2222 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2227 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2232 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2237 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2242 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2247 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2252 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2257 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2263 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2268 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2273 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2278 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2283 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2288 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2293 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2298 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2303 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2308 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2313 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2318 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2323 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2328 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2333 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2338 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2343 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2348 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2353 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2358 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2363 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2368 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2373 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2378 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2383 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2388 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2393 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2398 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2403 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2408 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2413 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2418 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2423 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2428 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2433 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2438 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2443 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2448 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2453 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2458 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2463 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2468 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2473 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2478 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2483 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2488 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2493 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2498 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2503 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2508 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2513 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2518 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2523 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2528 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2533 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2538 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2543 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 586.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-14: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2548 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: caught signal Terminated - aborting LoLA

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb114-PT-4-CTLFireability-00: CTL unknown AGGR
RERS17pb114-PT-4-CTLFireability-01: CTL unknown AGGR
RERS17pb114-PT-4-CTLFireability-02: CTL unknown AGGR
RERS17pb114-PT-4-CTLFireability-03: CONJ unknown CONJ
RERS17pb114-PT-4-CTLFireability-04: CTL unknown AGGR
RERS17pb114-PT-4-CTLFireability-05: CTL unknown AGGR
RERS17pb114-PT-4-CTLFireability-06: CTL unknown AGGR
RERS17pb114-PT-4-CTLFireability-07: CTL unknown AGGR
RERS17pb114-PT-4-CTLFireability-08: DISJ unknown DISJ
RERS17pb114-PT-4-CTLFireability-09: CTL unknown AGGR
RERS17pb114-PT-4-CTLFireability-10: CTL unknown AGGR
RERS17pb114-PT-4-CTLFireability-11: CTL unknown AGGR
RERS17pb114-PT-4-CTLFireability-13: CTL unknown AGGR
RERS17pb114-PT-4-CTLFireability-14: DISJ unknown DISJ
RERS17pb114-PT-4-CTLFireability-15: EXEF unknown AGGR


Time elapsed: 2552 secs. Pages in use: 0

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RERS17pb114-PT-4"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is RERS17pb114-PT-4, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r327-tall-167889199200098"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RERS17pb114-PT-4.tgz
mv RERS17pb114-PT-4 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;