About the Execution of LoLa+red for RERS17pb114-PT-1
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
16214.359 | 3600000.00 | 3768955.00 | 15939.00 | [undef] | Time out reached |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r327-tall-167889199100074.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is RERS17pb114-PT-1, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r327-tall-167889199100074
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 73M
-rw-r--r-- 1 mcc users 5.1K Feb 26 04:41 CTLCardinality.txt
-rw-r--r-- 1 mcc users 49K Feb 26 04:41 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.4K Feb 26 04:38 CTLFireability.txt
-rw-r--r-- 1 mcc users 44K Feb 26 04:38 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:38 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 16:38 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.1K Feb 25 16:38 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 16:38 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 26 04:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 120K Feb 26 04:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 13K Feb 26 04:51 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 81K Feb 26 04:51 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:38 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:38 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 73M Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME RERS17pb114-PT-1-CTLFireability-00
FORMULA_NAME RERS17pb114-PT-1-CTLFireability-01
FORMULA_NAME RERS17pb114-PT-1-CTLFireability-02
FORMULA_NAME RERS17pb114-PT-1-CTLFireability-03
FORMULA_NAME RERS17pb114-PT-1-CTLFireability-04
FORMULA_NAME RERS17pb114-PT-1-CTLFireability-05
FORMULA_NAME RERS17pb114-PT-1-CTLFireability-06
FORMULA_NAME RERS17pb114-PT-1-CTLFireability-07
FORMULA_NAME RERS17pb114-PT-1-CTLFireability-08
FORMULA_NAME RERS17pb114-PT-1-CTLFireability-09
FORMULA_NAME RERS17pb114-PT-1-CTLFireability-10
FORMULA_NAME RERS17pb114-PT-1-CTLFireability-11
FORMULA_NAME RERS17pb114-PT-1-CTLFireability-12
FORMULA_NAME RERS17pb114-PT-1-CTLFireability-13
FORMULA_NAME RERS17pb114-PT-1-CTLFireability-14
FORMULA_NAME RERS17pb114-PT-1-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678952897405
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RERS17pb114-PT-1
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-16 07:48:19] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-16 07:48:19] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-16 07:48:21] [INFO ] Load time of PNML (sax parser for PT used): 2064 ms
[2023-03-16 07:48:21] [INFO ] Transformed 1446 places.
[2023-03-16 07:48:21] [INFO ] Transformed 151085 transitions.
[2023-03-16 07:48:21] [INFO ] Found NUPN structural information;
[2023-03-16 07:48:21] [INFO ] Parsed PT model containing 1446 places and 151085 transitions and 604252 arcs in 2629 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 37 ms.
Support contains 178 out of 1446 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 1446/1446 places, 151085/151085 transitions.
Ensure Unique test removed 17 places
Iterating post reduction 0 with 17 rules applied. Total rules applied 17 place count 1429 transition count 151085
Applied a total of 17 rules in 1152 ms. Remains 1429 /1446 variables (removed 17) and now considering 151085/151085 (removed 0) transitions.
[2023-03-16 07:48:24] [INFO ] Flow matrix only has 84691 transitions (discarded 66394 similar events)
// Phase 1: matrix 84691 rows 1429 cols
[2023-03-16 07:48:24] [INFO ] Computed 18 place invariants in 459 ms
[2023-03-16 07:48:32] [INFO ] Implicit Places using invariants in 8790 ms returned []
Implicit Place search using SMT only with invariants took 8824 ms to find 0 implicit places.
[2023-03-16 07:48:32] [INFO ] Flow matrix only has 84691 transitions (discarded 66394 similar events)
[2023-03-16 07:48:32] [INFO ] Invariant cache hit.
[2023-03-16 07:49:03] [INFO ] Performed 88783/151085 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 07:49:23] [INFO ] Dead Transitions using invariants and state equation in 51069 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 1429/1446 places, 151085/151085 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 61067 ms. Remains : 1429/1446 places, 151085/151085 transitions.
Support contains 178 out of 1429 places after structural reductions.
[2023-03-16 07:49:28] [INFO ] Flatten gal took : 3455 ms
[2023-03-16 07:49:31] [INFO ] Flatten gal took : 3233 ms
[2023-03-16 07:49:38] [INFO ] Input system was already deterministic with 151085 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1407 ms. (steps per millisecond=7 ) properties (out of 83) seen :9
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 36 ms. (steps per millisecond=27 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=30 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=31 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 74) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 74) seen :0
Running SMT prover for 74 properties.
[2023-03-16 07:49:42] [INFO ] Flow matrix only has 84691 transitions (discarded 66394 similar events)
[2023-03-16 07:49:42] [INFO ] Invariant cache hit.
[2023-03-16 07:49:44] [INFO ] [Real]Absence check using 18 positive place invariants in 14 ms returned sat
[2023-03-16 07:50:07] [INFO ] After 22067ms SMT Verify possible using state equation in real domain returned unsat :0 sat :35 real:39
[2023-03-16 07:50:09] [INFO ] State equation strengthened by 2342 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 07:50:09] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 07:50:09] [INFO ] After 27146ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Fused 74 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 158 out of 1429 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Drop transitions removed 512 transitions
Reduce isomorphic transitions removed 512 transitions.
Iterating post reduction 0 with 512 rules applied. Total rules applied 512 place count 1429 transition count 150573
Applied a total of 512 rules in 2273 ms. Remains 1429 /1429 variables (removed 0) and now considering 150573/151085 (removed 512) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 2281 ms. Remains : 1429/1429 places, 150573/151085 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1374 ms. (steps per millisecond=7 ) properties (out of 74) seen :4
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=31 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 40 ms. (steps per millisecond=25 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 39 ms. (steps per millisecond=25 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=30 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 34 ms. (steps per millisecond=29 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 40 ms. (steps per millisecond=25 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 38 ms. (steps per millisecond=26 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=27 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 36 ms. (steps per millisecond=27 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=27 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 36 ms. (steps per millisecond=27 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 38 ms. (steps per millisecond=26 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 36 ms. (steps per millisecond=27 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 38 ms. (steps per millisecond=26 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=27 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 38 ms. (steps per millisecond=26 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 38 ms. (steps per millisecond=26 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 39 ms. (steps per millisecond=25 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 40 ms. (steps per millisecond=25 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 38 ms. (steps per millisecond=26 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 40 ms. (steps per millisecond=25 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 40 ms. (steps per millisecond=25 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 39 ms. (steps per millisecond=25 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 39 ms. (steps per millisecond=25 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 42 ms. (steps per millisecond=23 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=27 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 39 ms. (steps per millisecond=25 ) properties (out of 70) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 39 ms. (steps per millisecond=25 ) properties (out of 70) seen :0
Interrupted probabilistic random walk after 9665 steps, run timeout after 9003 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 9665 steps, saw 8112 distinct states, run finished after 9007 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 70 properties.
[2023-03-16 07:50:24] [INFO ] Flow matrix only has 84690 transitions (discarded 65883 similar events)
// Phase 1: matrix 84690 rows 1429 cols
[2023-03-16 07:50:25] [INFO ] Computed 18 place invariants in 308 ms
[2023-03-16 07:50:27] [INFO ] [Real]Absence check using 18 positive place invariants in 17 ms returned sat
[2023-03-16 07:50:50] [INFO ] After 22593ms SMT Verify possible using state equation in real domain returned unsat :0 sat :38 real:32
[2023-03-16 07:50:52] [INFO ] State equation strengthened by 2341 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 07:50:52] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 07:50:52] [INFO ] After 27150ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Fused 70 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 145 out of 1429 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1429/1429 places, 150573/150573 transitions.
Applied a total of 0 rules in 1285 ms. Remains 1429 /1429 variables (removed 0) and now considering 150573/150573 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1285 ms. Remains : 1429/1429 places, 150573/150573 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1256 ms. (steps per millisecond=7 ) properties (out of 70) seen :4
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 45 ms. (steps per millisecond=22 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 66) seen :0
Interrupted probabilistic random walk after 6132 steps, run timeout after 6003 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 6132 steps, saw 5209 distinct states, run finished after 6003 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 66 properties.
[2023-03-16 07:51:02] [INFO ] Flow matrix only has 84690 transitions (discarded 65883 similar events)
[2023-03-16 07:51:02] [INFO ] Invariant cache hit.
[2023-03-16 07:51:04] [INFO ] [Real]Absence check using 18 positive place invariants in 17 ms returned sat
[2023-03-16 07:51:28] [INFO ] After 22678ms SMT Verify possible using state equation in real domain returned unsat :0 sat :31 real:35
[2023-03-16 07:51:28] [INFO ] State equation strengthened by 2341 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 07:51:28] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 07:51:28] [INFO ] After 26182ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Fused 66 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 138 out of 1429 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1429/1429 places, 150573/150573 transitions.
Applied a total of 0 rules in 1177 ms. Remains 1429 /1429 variables (removed 0) and now considering 150573/150573 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1180 ms. Remains : 1429/1429 places, 150573/150573 transitions.
[2023-03-16 07:51:33] [INFO ] Flatten gal took : 2804 ms
[2023-03-16 07:51:36] [INFO ] Flatten gal took : 3204 ms
[2023-03-16 07:51:43] [INFO ] Input system was already deterministic with 151085 transitions.
Computed a total of 1 stabilizing places and 1 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 588 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 592 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 07:51:47] [INFO ] Flatten gal took : 2767 ms
[2023-03-16 07:51:50] [INFO ] Flatten gal took : 3231 ms
[2023-03-16 07:51:57] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 574 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 578 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 07:52:01] [INFO ] Flatten gal took : 2764 ms
[2023-03-16 07:52:04] [INFO ] Flatten gal took : 3195 ms
[2023-03-16 07:52:11] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 1213 ms. Remains 1428 /1429 variables (removed 1) and now considering 151084/151085 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1219 ms. Remains : 1428/1429 places, 151084/151085 transitions.
[2023-03-16 07:52:16] [INFO ] Flatten gal took : 3093 ms
[2023-03-16 07:52:19] [INFO ] Flatten gal took : 3545 ms
[2023-03-16 07:52:25] [INFO ] Input system was already deterministic with 151084 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 561 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 566 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 07:52:29] [INFO ] Flatten gal took : 2766 ms
[2023-03-16 07:52:32] [INFO ] Flatten gal took : 3137 ms
[2023-03-16 07:52:39] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 1091 ms. Remains 1428 /1429 variables (removed 1) and now considering 151084/151085 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1094 ms. Remains : 1428/1429 places, 151084/151085 transitions.
[2023-03-16 07:52:43] [INFO ] Flatten gal took : 3057 ms
[2023-03-16 07:52:47] [INFO ] Flatten gal took : 3514 ms
[2023-03-16 07:52:53] [INFO ] Input system was already deterministic with 151084 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 905 ms. (steps per millisecond=11 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 99 ms. (steps per millisecond=101 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 4071 steps, run timeout after 3006 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 4071 steps, saw 3014 distinct states, run finished after 3006 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-16 07:52:58] [INFO ] Flow matrix only has 84690 transitions (discarded 66394 similar events)
// Phase 1: matrix 84690 rows 1428 cols
[2023-03-16 07:52:58] [INFO ] Computed 18 place invariants in 303 ms
[2023-03-16 07:52:58] [INFO ] [Real]Absence check using 18 positive place invariants in 13 ms returned sat
[2023-03-16 07:53:19] [INFO ] After 20463ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-16 07:53:20] [INFO ] State equation strengthened by 773 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:669)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 07:53:23] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 07:53:23] [INFO ] After 25025ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 0 ms.
Support contains 2 out of 1428 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1428/1428 places, 151084/151084 transitions.
Drop transitions removed 512 transitions
Reduce isomorphic transitions removed 512 transitions.
Iterating post reduction 0 with 512 rules applied. Total rules applied 512 place count 1428 transition count 150572
Applied a total of 512 rules in 1868 ms. Remains 1428 /1428 variables (removed 0) and now considering 150572/151084 (removed 512) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1872 ms. Remains : 1428/1428 places, 150572/151084 transitions.
Interrupted random walk after 316794 steps, including 0 resets, run timeout after 30001 ms. (steps per millisecond=10 ) properties seen 0
Interrupted Best-First random walk after 700344 steps, including 2 resets, run timeout after 5001 ms. (steps per millisecond=140 ) properties seen 0
Interrupted probabilistic random walk after 114478 steps, run timeout after 105004 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 114478 steps, saw 91056 distinct states, run finished after 105005 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-16 07:55:45] [INFO ] Flow matrix only has 84689 transitions (discarded 65883 similar events)
// Phase 1: matrix 84689 rows 1428 cols
[2023-03-16 07:55:46] [INFO ] Computed 18 place invariants in 301 ms
[2023-03-16 07:55:46] [INFO ] [Real]Absence check using 18 positive place invariants in 15 ms returned sat
[2023-03-16 07:56:06] [INFO ] After 20228ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-16 07:56:07] [INFO ] State equation strengthened by 773 read => feed constraints.
[2023-03-16 07:56:15] [INFO ] After 7782ms SMT Verify possible using 773 Read/Feed constraints in real domain returned unsat :0 sat :1
[2023-03-16 07:56:28] [INFO ] Deduced a trap composed of 40 places in 12120 ms of which 13 ms to minimize.
[2023-03-16 07:56:42] [INFO ] Deduced a trap composed of 40 places in 12832 ms of which 2 ms to minimize.
[2023-03-16 07:56:55] [INFO ] Deduced a trap composed of 96 places in 11936 ms of which 3 ms to minimize.
[2023-03-16 07:57:07] [INFO ] Deduced a trap composed of 64 places in 10775 ms of which 6 ms to minimize.
[2023-03-16 07:57:19] [INFO ] Deduced a trap composed of 64 places in 10338 ms of which 2 ms to minimize.
[2023-03-16 07:57:30] [INFO ] Deduced a trap composed of 64 places in 9721 ms of which 1 ms to minimize.
[2023-03-16 07:57:39] [INFO ] Deduced a trap composed of 64 places in 8430 ms of which 1 ms to minimize.
[2023-03-16 07:57:48] [INFO ] Deduced a trap composed of 64 places in 8032 ms of which 1 ms to minimize.
[2023-03-16 07:57:57] [INFO ] Deduced a trap composed of 96 places in 7835 ms of which 1 ms to minimize.
[2023-03-16 07:58:06] [INFO ] Deduced a trap composed of 128 places in 7406 ms of which 1 ms to minimize.
[2023-03-16 07:58:14] [INFO ] Deduced a trap composed of 96 places in 6727 ms of which 1 ms to minimize.
[2023-03-16 07:58:21] [INFO ] Deduced a trap composed of 96 places in 5859 ms of which 1 ms to minimize.
[2023-03-16 07:58:27] [INFO ] Deduced a trap composed of 128 places in 5430 ms of which 0 ms to minimize.
[2023-03-16 07:58:33] [INFO ] Deduced a trap composed of 96 places in 4702 ms of which 0 ms to minimize.
[2023-03-16 07:58:38] [INFO ] Trap strengthening (SAT) tested/added 15/14 trap constraints in 143320 ms
[2023-03-16 07:58:39] [INFO ] After 151893ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-16 07:58:39] [INFO ] After 173007ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-16 07:58:39] [INFO ] [Nat]Absence check using 18 positive place invariants in 15 ms returned sat
[2023-03-16 07:59:00] [INFO ] After 21303ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-16 07:59:08] [INFO ] After 7934ms SMT Verify possible using 773 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-16 07:59:22] [INFO ] Deduced a trap composed of 40 places in 12571 ms of which 2 ms to minimize.
[2023-03-16 07:59:36] [INFO ] Deduced a trap composed of 40 places in 12639 ms of which 3 ms to minimize.
[2023-03-16 07:59:49] [INFO ] Deduced a trap composed of 64 places in 12349 ms of which 2 ms to minimize.
[2023-03-16 08:00:05] [INFO ] Deduced a trap composed of 64 places in 14612 ms of which 2 ms to minimize.
[2023-03-16 08:00:19] [INFO ] Deduced a trap composed of 64 places in 12061 ms of which 2 ms to minimize.
[2023-03-16 08:00:31] [INFO ] Deduced a trap composed of 64 places in 10989 ms of which 2 ms to minimize.
[2023-03-16 08:00:44] [INFO ] Deduced a trap composed of 64 places in 12395 ms of which 3 ms to minimize.
[2023-03-16 08:00:58] [INFO ] Deduced a trap composed of 96 places in 12656 ms of which 3 ms to minimize.
[2023-03-16 08:01:11] [INFO ] Deduced a trap composed of 96 places in 12214 ms of which 1 ms to minimize.
[2023-03-16 08:01:25] [INFO ] Deduced a trap composed of 64 places in 12073 ms of which 2 ms to minimize.
[2023-03-16 08:01:38] [INFO ] Deduced a trap composed of 64 places in 11966 ms of which 2 ms to minimize.
[2023-03-16 08:01:51] [INFO ] Deduced a trap composed of 64 places in 11644 ms of which 2 ms to minimize.
[2023-03-16 08:02:03] [INFO ] Deduced a trap composed of 64 places in 11493 ms of which 2 ms to minimize.
[2023-03-16 08:02:16] [INFO ] Deduced a trap composed of 96 places in 11612 ms of which 1 ms to minimize.
[2023-03-16 08:02:28] [INFO ] Deduced a trap composed of 66 places in 11280 ms of which 2 ms to minimize.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.refineWithTraps(DeadlockTester.java:1255)
at fr.lip6.move.gal.structural.smt.DeadlockTester.refineResultsWithTraps(DeadlockTester.java:736)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:656)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:669)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 08:02:28] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 08:02:28] [INFO ] After 229633ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:1
Parikh walk visited 0 properties in 0 ms.
Support contains 2 out of 1428 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1428/1428 places, 150572/150572 transitions.
Applied a total of 0 rules in 1567 ms. Remains 1428 /1428 variables (removed 0) and now considering 150572/150572 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1567 ms. Remains : 1428/1428 places, 150572/150572 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1428/1428 places, 150572/150572 transitions.
Applied a total of 0 rules in 1559 ms. Remains 1428 /1428 variables (removed 0) and now considering 150572/150572 (removed 0) transitions.
[2023-03-16 08:02:32] [INFO ] Flow matrix only has 84689 transitions (discarded 65883 similar events)
[2023-03-16 08:02:32] [INFO ] Invariant cache hit.
[2023-03-16 08:02:41] [INFO ] Implicit Places using invariants in 9032 ms returned []
Implicit Place search using SMT only with invariants took 9033 ms to find 0 implicit places.
[2023-03-16 08:02:41] [INFO ] Flow matrix only has 84689 transitions (discarded 65883 similar events)
[2023-03-16 08:02:41] [INFO ] Invariant cache hit.
[2023-03-16 08:03:11] [INFO ] Performed 88363/150572 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 08:03:32] [INFO ] Dead Transitions using invariants and state equation in 51752 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 62367 ms. Remains : 1428/1428 places, 150572/150572 transitions.
Finished random walk after 2042 steps, including 0 resets, run visited all 2 properties in 318 ms. (steps per millisecond=6 )
Interrupted random walk after 287034 steps, including 0 resets, run timeout after 30001 ms. (steps per millisecond=9 ) properties seen 0
Interrupted Best-First random walk after 632740 steps, including 1 resets, run timeout after 5001 ms. (steps per millisecond=126 ) properties seen 0
Interrupted probabilistic random walk after 125463 steps, run timeout after 105002 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 125463 steps, saw 99668 distinct states, run finished after 105004 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-16 08:05:53] [INFO ] Flow matrix only has 84689 transitions (discarded 65883 similar events)
[2023-03-16 08:05:53] [INFO ] Invariant cache hit.
[2023-03-16 08:05:54] [INFO ] [Real]Absence check using 18 positive place invariants in 15 ms returned sat
[2023-03-16 08:06:14] [INFO ] After 20671ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-16 08:06:15] [INFO ] State equation strengthened by 773 read => feed constraints.
[2023-03-16 08:06:23] [INFO ] After 7859ms SMT Verify possible using 773 Read/Feed constraints in real domain returned unsat :0 sat :1
[2023-03-16 08:06:36] [INFO ] Deduced a trap composed of 40 places in 11794 ms of which 2 ms to minimize.
[2023-03-16 08:06:48] [INFO ] Deduced a trap composed of 40 places in 11270 ms of which 2 ms to minimize.
[2023-03-16 08:07:00] [INFO ] Deduced a trap composed of 96 places in 10687 ms of which 2 ms to minimize.
[2023-03-16 08:07:11] [INFO ] Deduced a trap composed of 64 places in 9667 ms of which 1 ms to minimize.
[2023-03-16 08:07:21] [INFO ] Deduced a trap composed of 64 places in 8883 ms of which 2 ms to minimize.
[2023-03-16 08:07:31] [INFO ] Deduced a trap composed of 64 places in 8294 ms of which 3 ms to minimize.
[2023-03-16 08:07:41] [INFO ] Deduced a trap composed of 64 places in 9143 ms of which 1 ms to minimize.
[2023-03-16 08:07:50] [INFO ] Deduced a trap composed of 64 places in 8097 ms of which 1 ms to minimize.
[2023-03-16 08:07:59] [INFO ] Deduced a trap composed of 96 places in 7869 ms of which 0 ms to minimize.
[2023-03-16 08:08:08] [INFO ] Deduced a trap composed of 128 places in 7206 ms of which 0 ms to minimize.
[2023-03-16 08:08:16] [INFO ] Deduced a trap composed of 96 places in 6887 ms of which 1 ms to minimize.
[2023-03-16 08:08:23] [INFO ] Deduced a trap composed of 96 places in 5974 ms of which 0 ms to minimize.
[2023-03-16 08:08:30] [INFO ] Deduced a trap composed of 128 places in 5376 ms of which 0 ms to minimize.
[2023-03-16 08:08:36] [INFO ] Deduced a trap composed of 96 places in 4728 ms of which 1 ms to minimize.
[2023-03-16 08:08:40] [INFO ] Trap strengthening (SAT) tested/added 15/14 trap constraints in 137449 ms
[2023-03-16 08:08:41] [INFO ] After 146104ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-16 08:08:41] [INFO ] After 167817ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-16 08:08:41] [INFO ] [Nat]Absence check using 18 positive place invariants in 15 ms returned sat
[2023-03-16 08:09:02] [INFO ] After 20688ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-16 08:09:10] [INFO ] After 7724ms SMT Verify possible using 773 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-16 08:09:22] [INFO ] Deduced a trap composed of 40 places in 10706 ms of which 2 ms to minimize.
[2023-03-16 08:09:34] [INFO ] Deduced a trap composed of 40 places in 10739 ms of which 2 ms to minimize.
[2023-03-16 08:09:45] [INFO ] Deduced a trap composed of 64 places in 10554 ms of which 2 ms to minimize.
[2023-03-16 08:09:57] [INFO ] Deduced a trap composed of 64 places in 10617 ms of which 2 ms to minimize.
[2023-03-16 08:10:09] [INFO ] Deduced a trap composed of 64 places in 11048 ms of which 1 ms to minimize.
[2023-03-16 08:10:21] [INFO ] Deduced a trap composed of 64 places in 10668 ms of which 2 ms to minimize.
[2023-03-16 08:10:33] [INFO ] Deduced a trap composed of 64 places in 11411 ms of which 3 ms to minimize.
[2023-03-16 08:10:45] [INFO ] Deduced a trap composed of 96 places in 10897 ms of which 1 ms to minimize.
[2023-03-16 08:10:57] [INFO ] Deduced a trap composed of 96 places in 10822 ms of which 2 ms to minimize.
[2023-03-16 08:11:09] [INFO ] Deduced a trap composed of 64 places in 10428 ms of which 2 ms to minimize.
[2023-03-16 08:11:20] [INFO ] Deduced a trap composed of 64 places in 10013 ms of which 2 ms to minimize.
[2023-03-16 08:11:31] [INFO ] Deduced a trap composed of 64 places in 10038 ms of which 2 ms to minimize.
[2023-03-16 08:11:43] [INFO ] Deduced a trap composed of 64 places in 10493 ms of which 4 ms to minimize.
[2023-03-16 08:11:54] [INFO ] Deduced a trap composed of 96 places in 9899 ms of which 2 ms to minimize.
[2023-03-16 08:12:05] [INFO ] Deduced a trap composed of 66 places in 9584 ms of which 1 ms to minimize.
[2023-03-16 08:12:15] [INFO ] Deduced a trap composed of 128 places in 9566 ms of which 2 ms to minimize.
[2023-03-16 08:12:26] [INFO ] Deduced a trap composed of 96 places in 9758 ms of which 2 ms to minimize.
[2023-03-16 08:12:26] [INFO ] Trap strengthening (SAT) tested/added 17/17 trap constraints in 196274 ms
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Broken pipe ...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.refineResultsWithTraps(DeadlockTester.java:769)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:656)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:669)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 08:12:26] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 08:12:26] [INFO ] After 225023ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:1
Parikh walk visited 0 properties in 0 ms.
Support contains 2 out of 1428 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1428/1428 places, 150572/150572 transitions.
Applied a total of 0 rules in 1255 ms. Remains 1428 /1428 variables (removed 0) and now considering 150572/150572 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1255 ms. Remains : 1428/1428 places, 150572/150572 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1428/1428 places, 150572/150572 transitions.
Applied a total of 0 rules in 1261 ms. Remains 1428 /1428 variables (removed 0) and now considering 150572/150572 (removed 0) transitions.
[2023-03-16 08:12:29] [INFO ] Flow matrix only has 84689 transitions (discarded 65883 similar events)
[2023-03-16 08:12:29] [INFO ] Invariant cache hit.
[2023-03-16 08:12:37] [INFO ] Implicit Places using invariants in 8744 ms returned []
Implicit Place search using SMT only with invariants took 8747 ms to find 0 implicit places.
[2023-03-16 08:12:38] [INFO ] Flow matrix only has 84689 transitions (discarded 65883 similar events)
[2023-03-16 08:12:38] [INFO ] Invariant cache hit.
[2023-03-16 08:13:08] [INFO ] Performed 91062/150572 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 08:13:28] [INFO ] Dead Transitions using invariants and state equation in 50119 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 60142 ms. Remains : 1428/1428 places, 150572/150572 transitions.
Finished random walk after 3230 steps, including 0 resets, run visited all 2 properties in 322 ms. (steps per millisecond=10 )
Ensure Unique test removed 65883 transitions
Reduce isomorphic transitions removed 65883 transitions.
Iterating post reduction 0 with 65883 rules applied. Total rules applied 65883 place count 1428 transition count 84689
Applied a total of 65883 rules in 2928 ms. Remains 1428 /1428 variables (removed 0) and now considering 84689/150572 (removed 65883) transitions.
Running SMT prover for 1 properties.
// Phase 1: matrix 84689 rows 1428 cols
[2023-03-16 08:13:32] [INFO ] Computed 18 place invariants in 308 ms
[2023-03-16 08:13:32] [INFO ] [Real]Absence check using 18 positive place invariants in 16 ms returned sat
[2023-03-16 08:13:53] [INFO ] After 20632ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-16 08:14:00] [INFO ] Deduced a trap composed of 96 places in 5985 ms of which 2 ms to minimize.
[2023-03-16 08:14:06] [INFO ] Deduced a trap composed of 96 places in 5537 ms of which 1 ms to minimize.
[2023-03-16 08:14:12] [INFO ] Deduced a trap composed of 64 places in 4917 ms of which 1 ms to minimize.
[2023-03-16 08:14:18] [INFO ] Deduced a trap composed of 96 places in 4279 ms of which 1 ms to minimize.
[2023-03-16 08:14:22] [INFO ] Deduced a trap composed of 64 places in 3675 ms of which 0 ms to minimize.
[2023-03-16 08:14:26] [INFO ] Deduced a trap composed of 128 places in 2760 ms of which 0 ms to minimize.
[2023-03-16 08:14:30] [INFO ] Deduced a trap composed of 96 places in 2378 ms of which 1 ms to minimize.
[2023-03-16 08:14:32] [INFO ] Trap strengthening (SAT) tested/added 8/7 trap constraints in 39438 ms
[2023-03-16 08:14:33] [INFO ] After 60839ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-16 08:14:33] [INFO ] After 61086ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-16 08:14:33] [INFO ] [Nat]Absence check using 18 positive place invariants in 16 ms returned sat
[2023-03-16 08:14:54] [INFO ] After 20710ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-16 08:15:01] [INFO ] Deduced a trap composed of 96 places in 5770 ms of which 2 ms to minimize.
[2023-03-16 08:15:07] [INFO ] Deduced a trap composed of 64 places in 5439 ms of which 1 ms to minimize.
[2023-03-16 08:15:14] [INFO ] Deduced a trap composed of 96 places in 5790 ms of which 2 ms to minimize.
[2023-03-16 08:15:20] [INFO ] Deduced a trap composed of 64 places in 4839 ms of which 1 ms to minimize.
[2023-03-16 08:15:26] [INFO ] Deduced a trap composed of 96 places in 4690 ms of which 1 ms to minimize.
[2023-03-16 08:15:32] [INFO ] Deduced a trap composed of 128 places in 4976 ms of which 1 ms to minimize.
[2023-03-16 08:15:37] [INFO ] Deduced a trap composed of 64 places in 4583 ms of which 1 ms to minimize.
[2023-03-16 08:15:42] [INFO ] Deduced a trap composed of 96 places in 3287 ms of which 1 ms to minimize.
[2023-03-16 08:15:45] [INFO ] Deduced a trap composed of 128 places in 2242 ms of which 0 ms to minimize.
[2023-03-16 08:15:47] [INFO ] Trap strengthening (SAT) tested/added 10/9 trap constraints in 53568 ms
[2023-03-16 08:15:48] [INFO ] After 74983ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 1107 ms.
[2023-03-16 08:15:49] [INFO ] After 76329ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 571 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 573 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 08:15:53] [INFO ] Flatten gal took : 2746 ms
[2023-03-16 08:15:56] [INFO ] Flatten gal took : 3177 ms
[2023-03-16 08:16:02] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 1323 ms. Remains 1428 /1429 variables (removed 1) and now considering 151084/151085 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1327 ms. Remains : 1428/1429 places, 151084/151085 transitions.
[2023-03-16 08:16:07] [INFO ] Flatten gal took : 3077 ms
[2023-03-16 08:16:11] [INFO ] Flatten gal took : 3474 ms
[2023-03-16 08:16:17] [INFO ] Input system was already deterministic with 151084 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 562 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 565 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 08:16:21] [INFO ] Flatten gal took : 2777 ms
[2023-03-16 08:16:24] [INFO ] Flatten gal took : 2995 ms
[2023-03-16 08:16:30] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 567 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 569 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 08:16:34] [INFO ] Flatten gal took : 2748 ms
[2023-03-16 08:16:37] [INFO ] Flatten gal took : 3181 ms
[2023-03-16 08:16:43] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 579 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 581 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 08:16:47] [INFO ] Flatten gal took : 2742 ms
[2023-03-16 08:16:50] [INFO ] Flatten gal took : 3175 ms
[2023-03-16 08:16:56] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 570 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 572 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 08:17:00] [INFO ] Flatten gal took : 2787 ms
[2023-03-16 08:17:03] [INFO ] Flatten gal took : 2987 ms
[2023-03-16 08:17:09] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 566 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 568 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 08:17:13] [INFO ] Flatten gal took : 2735 ms
[2023-03-16 08:17:16] [INFO ] Flatten gal took : 3148 ms
[2023-03-16 08:17:22] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 1131 ms. Remains 1428 /1429 variables (removed 1) and now considering 151084/151085 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1135 ms. Remains : 1428/1429 places, 151084/151085 transitions.
[2023-03-16 08:17:27] [INFO ] Flatten gal took : 3044 ms
[2023-03-16 08:17:31] [INFO ] Flatten gal took : 3485 ms
[2023-03-16 08:17:37] [INFO ] Input system was already deterministic with 151084 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 572 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 575 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 08:17:41] [INFO ] Flatten gal took : 2787 ms
[2023-03-16 08:17:44] [INFO ] Flatten gal took : 3001 ms
[2023-03-16 08:17:50] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 566 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 569 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 08:17:54] [INFO ] Flatten gal took : 2727 ms
[2023-03-16 08:17:57] [INFO ] Flatten gal took : 3204 ms
[2023-03-16 08:18:03] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 564 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 566 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 08:18:07] [INFO ] Flatten gal took : 2747 ms
[2023-03-16 08:18:10] [INFO ] Flatten gal took : 3170 ms
[2023-03-16 08:18:16] [INFO ] Input system was already deterministic with 151085 transitions.
[2023-03-16 08:18:20] [INFO ] Flatten gal took : 3027 ms
[2023-03-16 08:18:23] [INFO ] Flatten gal took : 3029 ms
[2023-03-16 08:18:23] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2023-03-16 08:18:23] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 1429 places, 151085 transitions and 604235 arcs took 298 ms.
Total runtime 1804600 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT RERS17pb114-PT-1
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393232 kB
MemFree: 240792 kB
After kill :
MemTotal: 16393232 kB
MemFree: 16240104 kB
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 370 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 375 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 380 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 385 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 390 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 395 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 400 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 405 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 410 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 415 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 420 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 425 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 430 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 435 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 440 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 445 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 450 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 455 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 460 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 465 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 470 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 475 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 480 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 485 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 490 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 495 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 500 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 505 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 510 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 515 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 520 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 525 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 530 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 535 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 540 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 545 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 550 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 555 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 560 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 565 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 570 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 575 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 580 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 585 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 590 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 595 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 600 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 605 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 610 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 615 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 620 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 625 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 630 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 635 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 640 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 645 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 650 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 655 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 660 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 665 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 670 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 675 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 680 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 685 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 690 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 695 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 700 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 705 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 710 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 715 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 720 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 725 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 730 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 735 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 740 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 745 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 750 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 755 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 760 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 765 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 770 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 775 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 780 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 785 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 790 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 795 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 800 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 805 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 810 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 815 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 820 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 825 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 830 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 835 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 840 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 845 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 850 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 855 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 860 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 865 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 870 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 875 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 880 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 885 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 890 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 895 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 900 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 905 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 911 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 916 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 921 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 926 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 931 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 936 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 941 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 578.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 946 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 951 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 956 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 961 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 966 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 971 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 976 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 981 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 986 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 991 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 996 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1001 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1006 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1011 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1016 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1021 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1026 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1031 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1036 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1041 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1046 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1051 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1056 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1061 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1066 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1071 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1076 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1081 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1086 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1091 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1096 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1101 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1106 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1111 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1116 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1121 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1126 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1131 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1136 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1141 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1146 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1151 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1156 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1161 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1166 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1171 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1176 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1181 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1186 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1191 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1196 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1201 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1206 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1211 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1216 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1221 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1226 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1231 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1236 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1241 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1246 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1251 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1256 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1261 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1266 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1271 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1276 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1281 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1286 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1291 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1296 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1301 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1306 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1311 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1316 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1321 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1326 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1331 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1336 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1341 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1346 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1351 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1356 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1361 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1366 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1371 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1376 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1381 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1386 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1391 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1396 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1401 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1406 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1411 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1416 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1421 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1426 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1431 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1436 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1441 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1446 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1451 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1456 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1461 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1466 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1471 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1476 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 536.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1481 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1486 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1491 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1496 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1501 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1506 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1511 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1516 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1521 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1526 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1531 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1536 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1541 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1546 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1551 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1556 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1561 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1566 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1571 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1576 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1581 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1586 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1591 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1596 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1601 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1606 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1611 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1616 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1621 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1626 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1631 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1636 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1641 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1646 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1651 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1656 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1661 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1666 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1671 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1676 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1681 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1686 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1691 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1696 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1701 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1706 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1711 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1716 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1721 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1726 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1731 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1736 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1741 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1746 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1751 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1756 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1761 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1766 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1771 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1776 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1781 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1786 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-04: EF 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-06: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-13: DISJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-1-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1791 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: caught signal Terminated - aborting LoLA
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb114-PT-1-CTLFireability-00: CTL unknown AGGR
RERS17pb114-PT-1-CTLFireability-01: CTL unknown AGGR
RERS17pb114-PT-1-CTLFireability-02: CTL unknown AGGR
RERS17pb114-PT-1-CTLFireability-03: CTL unknown AGGR
RERS17pb114-PT-1-CTLFireability-04: EF unknown AGGR
RERS17pb114-PT-1-CTLFireability-05: CTL unknown AGGR
RERS17pb114-PT-1-CTLFireability-06: CONJ unknown CONJ
RERS17pb114-PT-1-CTLFireability-07: CTL unknown AGGR
RERS17pb114-PT-1-CTLFireability-08: DISJ unknown DISJ
RERS17pb114-PT-1-CTLFireability-09: CTL unknown AGGR
RERS17pb114-PT-1-CTLFireability-10: CTL unknown AGGR
RERS17pb114-PT-1-CTLFireability-11: CTL unknown AGGR
RERS17pb114-PT-1-CTLFireability-12: EG unknown AGGR
RERS17pb114-PT-1-CTLFireability-13: DISJ unknown DISJ
RERS17pb114-PT-1-CTLFireability-14: CTL unknown AGGR
RERS17pb114-PT-1-CTLFireability-15: CTL unknown AGGR
Time elapsed: 1793 secs. Pages in use: 0
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RERS17pb114-PT-1"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is RERS17pb114-PT-1, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r327-tall-167889199100074"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/RERS17pb114-PT-1.tgz
mv RERS17pb114-PT-1 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;