Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r327-tall-167889199100026.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...........................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is RERS17pb113-PT-4, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r327-tall-167889199100026
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 15M
-rw-r--r-- 1 mcc users 7.3K Feb 26 18:11 CTLCardinality.txt
-rw-r--r-- 1 mcc users 80K Feb 26 18:11 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.5K Feb 26 18:10 CTLFireability.txt
-rw-r--r-- 1 mcc users 53K Feb 26 18:10 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 16:37 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:37 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Feb 25 16:37 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:37 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 26 18:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 110K Feb 26 18:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 14K Feb 26 18:14 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 89K Feb 26 18:14 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:37 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:37 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 15M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-00
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-01
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-02
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-03
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-04
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-05
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-06
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-07
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-08
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-09
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-10
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-11
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-12
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-13
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-14
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678937276002

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RERS17pb113-PT-4
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-16 03:27:57] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-16 03:27:57] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-16 03:27:58] [INFO ] Load time of PNML (sax parser for PT used): 745 ms
[2023-03-16 03:27:58] [INFO ] Transformed 639 places.
[2023-03-16 03:27:58] [INFO ] Transformed 31353 transitions.
[2023-03-16 03:27:58] [INFO ] Parsed PT model containing 639 places and 31353 transitions and 125418 arcs in 973 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 29 ms.
Support contains 207 out of 639 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 639/639 places, 31353/31353 transitions.
Ensure Unique test removed 12 places
Iterating post reduction 0 with 12 rules applied. Total rules applied 12 place count 627 transition count 31353
Applied a total of 12 rules in 185 ms. Remains 627 /639 variables (removed 12) and now considering 31353/31353 (removed 0) transitions.
[2023-03-16 03:27:59] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
// Phase 1: matrix 18326 rows 627 cols
[2023-03-16 03:27:59] [INFO ] Computed 13 place invariants in 119 ms
[2023-03-16 03:28:00] [INFO ] Implicit Places using invariants in 1591 ms returned []
Implicit Place search using SMT only with invariants took 1616 ms to find 0 implicit places.
[2023-03-16 03:28:00] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 03:28:00] [INFO ] Invariant cache hit.
[2023-03-16 03:28:08] [INFO ] Dead Transitions using invariants and state equation in 8261 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 627/639 places, 31353/31353 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10075 ms. Remains : 627/639 places, 31353/31353 transitions.
Support contains 207 out of 627 places after structural reductions.
[2023-03-16 03:28:10] [INFO ] Flatten gal took : 1093 ms
[2023-03-16 03:28:11] [INFO ] Flatten gal took : 804 ms
[2023-03-16 03:28:12] [INFO ] Input system was already deterministic with 31353 transitions.
Support contains 195 out of 627 places (down from 207) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 779 ms. (steps per millisecond=12 ) properties (out of 84) seen :18
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 48 ms. (steps per millisecond=20 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 66) seen :0
Running SMT prover for 66 properties.
[2023-03-16 03:28:14] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 03:28:14] [INFO ] Invariant cache hit.
[2023-03-16 03:28:16] [INFO ] [Real]Absence check using 13 positive place invariants in 8 ms returned sat
[2023-03-16 03:28:39] [INFO ] After 24208ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:66
[2023-03-16 03:28:40] [INFO ] [Nat]Absence check using 13 positive place invariants in 9 ms returned sat
[2023-03-16 03:29:04] [INFO ] After 23747ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :66
[2023-03-16 03:29:04] [INFO ] State equation strengthened by 829 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 03:29:04] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 03:29:04] [INFO ] After 25309ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:66
Fused 66 Parikh solutions to 11 different solutions.
Parikh walk visited 0 properties in 95 ms.
Support contains 165 out of 627 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 334 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 352 ms. Remains : 627/627 places, 31353/31353 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 509 ms. (steps per millisecond=19 ) properties (out of 66) seen :6
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Interrupted probabilistic random walk after 19471 steps, run timeout after 3001 ms. (steps per millisecond=6 ) properties seen :{}
Probabilistic random walk after 19471 steps, saw 17580 distinct states, run finished after 3003 ms. (steps per millisecond=6 ) properties seen :0
Running SMT prover for 60 properties.
[2023-03-16 03:29:09] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 03:29:09] [INFO ] Invariant cache hit.
[2023-03-16 03:29:10] [INFO ] [Real]Absence check using 13 positive place invariants in 7 ms returned sat
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.checkResults(DeadlockTester.java:797)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:631)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 03:29:34] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 03:29:34] [INFO ] After 25032ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Fused 60 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 150 out of 627 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 212 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 212 ms. Remains : 627/627 places, 31353/31353 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 631 ms. (steps per millisecond=15 ) properties (out of 60) seen :4
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 56) seen :0
Interrupted probabilistic random walk after 22343 steps, run timeout after 3001 ms. (steps per millisecond=7 ) properties seen :{}
Probabilistic random walk after 22343 steps, saw 20137 distinct states, run finished after 3002 ms. (steps per millisecond=7 ) properties seen :0
Running SMT prover for 56 properties.
[2023-03-16 03:29:39] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 03:29:39] [INFO ] Invariant cache hit.
[2023-03-16 03:29:40] [INFO ] [Real]Absence check using 13 positive place invariants in 8 ms returned sat
[2023-03-16 03:30:04] [INFO ] After 24173ms SMT Verify possible using state equation in real domain returned unsat :0 sat :19 real:36
[2023-03-16 03:30:05] [INFO ] State equation strengthened by 829 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 03:30:05] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 03:30:05] [INFO ] After 25415ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Fused 56 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 142 out of 627 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 180 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 181 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 03:30:05] [INFO ] Flatten gal took : 630 ms
[2023-03-16 03:30:06] [INFO ] Flatten gal took : 668 ms
[2023-03-16 03:30:08] [INFO ] Input system was already deterministic with 31353 transitions.
Computed a total of 1 stabilizing places and 1 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 239 ms. Remains 626 /627 variables (removed 1) and now considering 31352/31353 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 240 ms. Remains : 626/627 places, 31352/31353 transitions.
[2023-03-16 03:30:09] [INFO ] Flatten gal took : 629 ms
[2023-03-16 03:30:09] [INFO ] Flatten gal took : 723 ms
[2023-03-16 03:30:11] [INFO ] Input system was already deterministic with 31352 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 304 ms. (steps per millisecond=32 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=400 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 24751 steps, run timeout after 3002 ms. (steps per millisecond=8 ) properties seen :{}
Probabilistic random walk after 24751 steps, saw 22287 distinct states, run finished after 3002 ms. (steps per millisecond=8 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-16 03:30:14] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
// Phase 1: matrix 18325 rows 626 cols
[2023-03-16 03:30:14] [INFO ] Computed 13 place invariants in 71 ms
[2023-03-16 03:30:14] [INFO ] [Real]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 03:30:36] [INFO ] After 21872ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-16 03:30:36] [INFO ] [Nat]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 03:30:55] [INFO ] After 18815ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-16 03:30:55] [INFO ] State equation strengthened by 268 read => feed constraints.
[2023-03-16 03:31:01] [INFO ] After 6012ms SMT Verify possible using 268 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-16 03:31:01] [INFO ] After 6013ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 6 ms.
[2023-03-16 03:31:01] [INFO ] After 25049ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 5 ms.
Support contains 2 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 218 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 219 ms. Remains : 626/626 places, 31352/31352 transitions.
Finished random walk after 5482 steps, including 0 resets, run visited all 2 properties in 214 ms. (steps per millisecond=25 )
Interrupted random walk after 921461 steps, including 2 resets, run timeout after 30001 ms. (steps per millisecond=30 ) properties seen 0
Incomplete Best-First random walk after 1000001 steps, including 2 resets, run finished after 2138 ms. (steps per millisecond=467 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 894537 steps, run timeout after 96001 ms. (steps per millisecond=9 ) properties seen :{}
Probabilistic random walk after 894537 steps, saw 799368 distinct states, run finished after 96001 ms. (steps per millisecond=9 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-16 03:33:10] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:33:10] [INFO ] Invariant cache hit.
[2023-03-16 03:33:10] [INFO ] [Real]Absence check using 13 positive place invariants in 9 ms returned sat
[2023-03-16 03:33:29] [INFO ] After 19229ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-16 03:33:29] [INFO ] [Nat]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 03:33:46] [INFO ] After 16746ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-16 03:33:46] [INFO ] State equation strengthened by 268 read => feed constraints.
[2023-03-16 03:33:50] [INFO ] After 4029ms SMT Verify possible using 268 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-16 03:33:51] [INFO ] Deduced a trap composed of 40 places in 426 ms of which 4 ms to minimize.
[2023-03-16 03:33:52] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 1258 ms
[2023-03-16 03:33:52] [INFO ] After 5626ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 501 ms.
[2023-03-16 03:33:52] [INFO ] After 23057ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 5 ms.
Support contains 2 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 199 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 199 ms. Remains : 626/626 places, 31352/31352 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 182 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 03:33:53] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:33:53] [INFO ] Invariant cache hit.
[2023-03-16 03:33:55] [INFO ] Implicit Places using invariants in 1945 ms returned []
Implicit Place search using SMT only with invariants took 1946 ms to find 0 implicit places.
[2023-03-16 03:33:55] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:33:55] [INFO ] Invariant cache hit.
[2023-03-16 03:34:03] [INFO ] Dead Transitions using invariants and state equation in 8370 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 10502 ms. Remains : 626/626 places, 31352/31352 transitions.
Finished random walk after 1580 steps, including 0 resets, run visited all 2 properties in 55 ms. (steps per millisecond=28 )
Ensure Unique test removed 13027 transitions
Reduce isomorphic transitions removed 13027 transitions.
Iterating post reduction 0 with 13027 rules applied. Total rules applied 13027 place count 626 transition count 18325
Applied a total of 13027 rules in 666 ms. Remains 626 /626 variables (removed 0) and now considering 18325/31352 (removed 13027) transitions.
Running SMT prover for 1 properties.
// Phase 1: matrix 18325 rows 626 cols
[2023-03-16 03:34:04] [INFO ] Computed 13 place invariants in 56 ms
[2023-03-16 03:34:04] [INFO ] [Real]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 03:34:18] [INFO ] After 13864ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-16 03:34:18] [INFO ] [Nat]Absence check using 13 positive place invariants in 5 ms returned sat
[2023-03-16 03:34:32] [INFO ] After 13771ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-16 03:34:32] [INFO ] After 14389ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 420 ms.
[2023-03-16 03:34:33] [INFO ] After 14893ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 80 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 82 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 03:34:33] [INFO ] Flatten gal took : 580 ms
[2023-03-16 03:34:34] [INFO ] Flatten gal took : 663 ms
[2023-03-16 03:34:35] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 71 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 72 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 03:34:36] [INFO ] Flatten gal took : 583 ms
[2023-03-16 03:34:37] [INFO ] Flatten gal took : 687 ms
[2023-03-16 03:34:38] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 178 ms. Remains 626 /627 variables (removed 1) and now considering 31352/31353 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 179 ms. Remains : 626/627 places, 31352/31353 transitions.
[2023-03-16 03:34:39] [INFO ] Flatten gal took : 577 ms
[2023-03-16 03:34:40] [INFO ] Flatten gal took : 668 ms
[2023-03-16 03:34:41] [INFO ] Input system was already deterministic with 31352 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 176 ms. Remains 626 /627 variables (removed 1) and now considering 31352/31353 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 177 ms. Remains : 626/627 places, 31352/31353 transitions.
[2023-03-16 03:34:42] [INFO ] Flatten gal took : 567 ms
[2023-03-16 03:34:43] [INFO ] Flatten gal took : 682 ms
[2023-03-16 03:34:44] [INFO ] Input system was already deterministic with 31352 transitions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 95 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 96 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 03:34:45] [INFO ] Flatten gal took : 579 ms
[2023-03-16 03:34:45] [INFO ] Flatten gal took : 685 ms
[2023-03-16 03:34:47] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 69 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 69 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 03:34:48] [INFO ] Flatten gal took : 571 ms
[2023-03-16 03:34:48] [INFO ] Flatten gal took : 668 ms
[2023-03-16 03:34:50] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 173 ms. Remains 626 /627 variables (removed 1) and now considering 31352/31353 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 175 ms. Remains : 626/627 places, 31352/31353 transitions.
[2023-03-16 03:34:51] [INFO ] Flatten gal took : 598 ms
[2023-03-16 03:34:51] [INFO ] Flatten gal took : 637 ms
[2023-03-16 03:34:52] [INFO ] Input system was already deterministic with 31352 transitions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 72 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 72 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 03:34:53] [INFO ] Flatten gal took : 574 ms
[2023-03-16 03:34:54] [INFO ] Flatten gal took : 670 ms
[2023-03-16 03:34:55] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 72 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 73 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 03:34:56] [INFO ] Flatten gal took : 578 ms
[2023-03-16 03:34:57] [INFO ] Flatten gal took : 681 ms
[2023-03-16 03:34:58] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 162 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 163 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 03:34:59] [INFO ] Flatten gal took : 606 ms
[2023-03-16 03:34:59] [INFO ] Flatten gal took : 639 ms
[2023-03-16 03:35:01] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 71 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 71 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 03:35:02] [INFO ] Flatten gal took : 572 ms
[2023-03-16 03:35:02] [INFO ] Flatten gal took : 668 ms
[2023-03-16 03:35:03] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 70 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 71 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 03:35:04] [INFO ] Flatten gal took : 568 ms
[2023-03-16 03:35:05] [INFO ] Flatten gal took : 661 ms
[2023-03-16 03:35:06] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 158 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 159 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 03:35:07] [INFO ] Flatten gal took : 583 ms
[2023-03-16 03:35:08] [INFO ] Flatten gal took : 665 ms
[2023-03-16 03:35:09] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 69 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 70 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 03:35:10] [INFO ] Flatten gal took : 578 ms
[2023-03-16 03:35:10] [INFO ] Flatten gal took : 667 ms
[2023-03-16 03:35:12] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 166 ms. Remains 626 /627 variables (removed 1) and now considering 31352/31353 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 167 ms. Remains : 626/627 places, 31352/31353 transitions.
[2023-03-16 03:35:13] [INFO ] Flatten gal took : 579 ms
[2023-03-16 03:35:13] [INFO ] Flatten gal took : 668 ms
[2023-03-16 03:35:14] [INFO ] Input system was already deterministic with 31352 transitions.
[2023-03-16 03:35:15] [INFO ] Flatten gal took : 645 ms
[2023-03-16 03:35:16] [INFO ] Flatten gal took : 683 ms
[2023-03-16 03:35:16] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2023-03-16 03:35:16] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 627 places, 31353 transitions and 125406 arcs took 90 ms.
Total runtime 439011 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT RERS17pb113-PT-4
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

BK_STOP 1678938214063

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

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RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-03: SP ACTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

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RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-03: SP ACTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-03: SP ACTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
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RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 2 0 0 0
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RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
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/home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin//../BenchKit_head.sh: line 63: 537 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RERS17pb113-PT-4"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is RERS17pb113-PT-4, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r327-tall-167889199100026"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RERS17pb113-PT-4.tgz
mv RERS17pb113-PT-4 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;