Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r327-tall-167889199100020.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is RERS17pb113-PT-3, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r327-tall-167889199100020
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 15M
-rw-r--r-- 1 mcc users 7.4K Feb 26 18:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 82K Feb 26 18:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.6K Feb 26 18:13 CTLFireability.txt
-rw-r--r-- 1 mcc users 55K Feb 26 18:13 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 16:37 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 16:37 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.2K Feb 25 16:37 LTLFireability.txt
-rw-r--r-- 1 mcc users 20K Feb 25 16:37 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 26 18:20 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 144K Feb 26 18:20 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 5.6K Feb 26 18:19 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 30K Feb 26 18:19 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:37 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:37 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 15M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RERS17pb113-PT-3-LTLFireability-00
FORMULA_NAME RERS17pb113-PT-3-LTLFireability-01
FORMULA_NAME RERS17pb113-PT-3-LTLFireability-02
FORMULA_NAME RERS17pb113-PT-3-LTLFireability-03
FORMULA_NAME RERS17pb113-PT-3-LTLFireability-04
FORMULA_NAME RERS17pb113-PT-3-LTLFireability-05
FORMULA_NAME RERS17pb113-PT-3-LTLFireability-06
FORMULA_NAME RERS17pb113-PT-3-LTLFireability-07
FORMULA_NAME RERS17pb113-PT-3-LTLFireability-08
FORMULA_NAME RERS17pb113-PT-3-LTLFireability-09
FORMULA_NAME RERS17pb113-PT-3-LTLFireability-10
FORMULA_NAME RERS17pb113-PT-3-LTLFireability-11
FORMULA_NAME RERS17pb113-PT-3-LTLFireability-12
FORMULA_NAME RERS17pb113-PT-3-LTLFireability-13
FORMULA_NAME RERS17pb113-PT-3-LTLFireability-14
FORMULA_NAME RERS17pb113-PT-3-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1678934266988

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=LTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RERS17pb113-PT-3
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-16 02:37:48] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-16 02:37:48] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-16 02:37:49] [INFO ] Load time of PNML (sax parser for PT used): 608 ms
[2023-03-16 02:37:49] [INFO ] Transformed 639 places.
[2023-03-16 02:37:49] [INFO ] Transformed 31353 transitions.
[2023-03-16 02:37:49] [INFO ] Parsed PT model containing 639 places and 31353 transitions and 125418 arcs in 802 ms.
Parsed 16 properties from file /home/mcc/execution/LTLFireability.xml in 15 ms.
Working with output stream class java.io.PrintStream
Initial state reduction rules removed 7 formulas.
FORMULA RERS17pb113-PT-3-LTLFireability-01 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA RERS17pb113-PT-3-LTLFireability-03 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA RERS17pb113-PT-3-LTLFireability-08 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA RERS17pb113-PT-3-LTLFireability-09 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA RERS17pb113-PT-3-LTLFireability-11 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA RERS17pb113-PT-3-LTLFireability-12 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA RERS17pb113-PT-3-LTLFireability-13 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 44 out of 639 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 639/639 places, 31353/31353 transitions.
Ensure Unique test removed 12 places
Iterating post reduction 0 with 12 rules applied. Total rules applied 12 place count 627 transition count 31353
Applied a total of 12 rules in 247 ms. Remains 627 /639 variables (removed 12) and now considering 31353/31353 (removed 0) transitions.
[2023-03-16 02:37:50] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
// Phase 1: matrix 18326 rows 627 cols
[2023-03-16 02:37:50] [INFO ] Computed 13 place invariants in 136 ms
[2023-03-16 02:37:52] [INFO ] Implicit Places using invariants in 2182 ms returned []
Implicit Place search using SMT only with invariants took 2208 ms to find 0 implicit places.
[2023-03-16 02:37:52] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 02:37:52] [INFO ] Invariant cache hit.
[2023-03-16 02:38:01] [INFO ] Dead Transitions using invariants and state equation in 9062 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 627/639 places, 31353/31353 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11531 ms. Remains : 627/639 places, 31353/31353 transitions.
Support contains 44 out of 627 places after structural reductions.
[2023-03-16 02:38:03] [INFO ] Flatten gal took : 971 ms
[2023-03-16 02:38:04] [INFO ] Flatten gal took : 869 ms
[2023-03-16 02:38:05] [INFO ] Input system was already deterministic with 31353 transitions.
Support contains 42 out of 627 places (down from 44) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 992 ms. (steps per millisecond=10 ) properties (out of 24) seen :7
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=76 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 17) seen :0
Running SMT prover for 17 properties.
[2023-03-16 02:38:07] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 02:38:07] [INFO ] Invariant cache hit.
[2023-03-16 02:38:07] [INFO ] [Real]Absence check using 13 positive place invariants in 10 ms returned sat
[2023-03-16 02:38:29] [INFO ] After 22394ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:17
[2023-03-16 02:38:30] [INFO ] [Nat]Absence check using 13 positive place invariants in 8 ms returned sat
[2023-03-16 02:38:54] [INFO ] After 24583ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :15
[2023-03-16 02:38:55] [INFO ] State equation strengthened by 829 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStructuralLTLCheck(LTLPropertySolver.java:71)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:762)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 02:38:55] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 02:38:55] [INFO ] After 25288ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:17
Fused 17 Parikh solutions to 16 different solutions.
Parikh walk visited 0 properties in 142 ms.
Support contains 30 out of 627 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 301 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 306 ms. Remains : 627/627 places, 31353/31353 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 568 ms. (steps per millisecond=17 ) properties (out of 17) seen :3
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 55 ms. (steps per millisecond=181 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 49 ms. (steps per millisecond=204 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 48 ms. (steps per millisecond=208 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 46 ms. (steps per millisecond=217 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 43 ms. (steps per millisecond=232 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 45 ms. (steps per millisecond=222 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 46 ms. (steps per millisecond=217 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 45 ms. (steps per millisecond=222 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 45 ms. (steps per millisecond=222 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 50 ms. (steps per millisecond=200 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 51 ms. (steps per millisecond=196 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 51 ms. (steps per millisecond=196 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 55 ms. (steps per millisecond=181 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 52 ms. (steps per millisecond=192 ) properties (out of 14) seen :0
Running SMT prover for 14 properties.
[2023-03-16 02:38:56] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 02:38:56] [INFO ] Invariant cache hit.
[2023-03-16 02:38:57] [INFO ] [Real]Absence check using 13 positive place invariants in 7 ms returned sat
[2023-03-16 02:39:21] [INFO ] After 24203ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:14
[2023-03-16 02:39:21] [INFO ] [Nat]Absence check using 13 positive place invariants in 7 ms returned sat
[2023-03-16 02:39:43] [INFO ] After 22166ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :14
[2023-03-16 02:39:44] [INFO ] State equation strengthened by 829 read => feed constraints.
[2023-03-16 02:39:46] [INFO ] After 2141ms SMT Verify possible using 829 Read/Feed constraints in natural domain returned unsat :0 sat :13
[2023-03-16 02:39:46] [INFO ] After 2143ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :13
Attempting to minimize the solution found.
Minimization took 10 ms.
[2023-03-16 02:39:46] [INFO ] After 25049ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :13
Parikh walk visited 0 properties in 55 ms.
Support contains 26 out of 627 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 0 with 1 rules applied. Total rules applied 1 place count 626 transition count 31352
Applied a total of 1 rules in 403 ms. Remains 626 /627 variables (removed 1) and now considering 31352/31353 (removed 1) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 403 ms. Remains : 626/627 places, 31352/31353 transitions.
Computed a total of 1 stabilizing places and 1 stable transitions
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!(F((G(p0)||G((F((!p1||X(!p2))) U p3)))))'
Support contains 8 out of 627 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 321 ms. Remains 626 /627 variables (removed 1) and now considering 31352/31353 (removed 1) transitions.
[2023-03-16 02:39:47] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
// Phase 1: matrix 18325 rows 626 cols
[2023-03-16 02:39:47] [INFO ] Computed 13 place invariants in 83 ms
[2023-03-16 02:39:49] [INFO ] Implicit Places using invariants in 2281 ms returned []
Implicit Place search using SMT only with invariants took 2282 ms to find 0 implicit places.
[2023-03-16 02:39:49] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:39:49] [INFO ] Invariant cache hit.
[2023-03-16 02:39:58] [INFO ] Dead Transitions using invariants and state equation in 8576 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 11183 ms. Remains : 626/627 places, 31352/31353 transitions.
Stuttering acceptance computed with spot in 282 ms :[(AND (NOT p0) (NOT p3)), (AND (NOT p0) (NOT p3)), (AND (NOT p3) p1 (NOT p0) p2)]
Running random walk in product with property : RERS17pb113-PT-3-LTLFireability-00 automaton TGBA Formula[mat=[[{ cond=true, acceptance={} source=0 dest: 0}, { cond=(NOT p3), acceptance={} source=0 dest: 1}, { cond=(AND (NOT p3) p1), acceptance={} source=0 dest: 2}], [{ cond=(AND p0 (NOT p3)), acceptance={1} source=1 dest: 1}, { cond=(AND (NOT p0) (NOT p3)), acceptance={0, 1} source=1 dest: 1}, { cond=(AND (NOT p3) p1), acceptance={} source=1 dest: 2}], [{ cond=(AND p0 p3 p1 p2), acceptance={} source=2 dest: 2}, { cond=(AND (NOT p0) p3 p1 p2), acceptance={0} source=2 dest: 2}, { cond=(AND p0 (NOT p3) p1 p2), acceptance={1} source=2 dest: 2}, { cond=(AND (NOT p0) (NOT p3) p1 p2), acceptance={0, 1} source=2 dest: 2}]], initial=0, aps=[p3:(AND (GEQ s62 1) (GEQ s360 1)), p1:(AND (GEQ s77 1) (GEQ s233 1)), p0:(AND (GEQ s290 1) (GEQ s385 1)), p2:(AND (GEQ s305 1) (GEQ s523 1))], nbAcceptance=2, properties=[trans-labels, explicit-labels, trans-acc, no-univ-branch, stutter-invariant], stateDesc=[null, null, null][true, true, true]]
Product exploration explored 100000 steps with 0 reset in 3316 ms.
Product exploration explored 100000 steps with 0 reset in 3326 ms.
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Knowledge obtained : [(AND (NOT p3) (NOT p1) (NOT p0) (NOT p2)), (X (NOT (AND (NOT p3) p1))), (X (NOT (AND (NOT p0) p3 p1 p2))), (X (NOT (AND p0 (NOT p3) p1 p2))), (X (NOT (AND (NOT p0) (NOT p3) p1 p2))), (X (AND (NOT p0) (NOT p3))), (X (NOT (AND p0 (NOT p3)))), (X (NOT (AND p0 p3 p1 p2))), (X (X (NOT (AND (NOT p3) p1)))), (X (X (NOT (AND (NOT p0) p3 p1 p2)))), (X (X (NOT (AND p0 (NOT p3) p1 p2)))), (X (X (NOT (AND (NOT p0) (NOT p3) p1 p2)))), (X (X (AND (NOT p0) (NOT p3)))), (X (X (NOT (AND p0 (NOT p3))))), (X (X (NOT (AND p0 p3 p1 p2))))]
False Knowledge obtained : []
Knowledge based reduction with 15 factoid took 787 ms. Reduced automaton from 3 states, 10 edges and 4 AP (stutter insensitive) to 3 states, 10 edges and 4 AP (stutter insensitive).
Stuttering acceptance computed with spot in 151 ms :[(AND (NOT p0) (NOT p3)), (AND (NOT p0) (NOT p3)), (AND (NOT p3) p1 (NOT p0) p2)]
Incomplete random walk after 10000 steps, including 2 resets, run finished after 547 ms. (steps per millisecond=18 ) properties (out of 8) seen :2
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 39 ms. (steps per millisecond=256 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 44 ms. (steps per millisecond=227 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 35 ms. (steps per millisecond=285 ) properties (out of 6) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=270 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 55 ms. (steps per millisecond=181 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=270 ) properties (out of 5) seen :0
Running SMT prover for 5 properties.
[2023-03-16 02:40:07] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:40:07] [INFO ] Invariant cache hit.
[2023-03-16 02:40:07] [INFO ] [Real]Absence check using 13 positive place invariants in 11 ms returned sat
[2023-03-16 02:40:31] [INFO ] After 23418ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:5
[2023-03-16 02:40:31] [INFO ] [Nat]Absence check using 13 positive place invariants in 7 ms returned sat
[2023-03-16 02:40:47] [INFO ] After 16602ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :5
[2023-03-16 02:40:47] [INFO ] State equation strengthened by 268 read => feed constraints.
[2023-03-16 02:40:56] [INFO ] After 8213ms SMT Verify possible using 268 Read/Feed constraints in natural domain returned unsat :0 sat :5
[2023-03-16 02:40:56] [INFO ] After 8213ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :5
Attempting to minimize the solution found.
Minimization took 5 ms.
[2023-03-16 02:40:56] [INFO ] After 25072ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :5
Parikh walk visited 0 properties in 21 ms.
Support contains 8 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 168 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 169 ms. Remains : 626/626 places, 31352/31352 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 432 ms. (steps per millisecond=23 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=312 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 34 ms. (steps per millisecond=294 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 34 ms. (steps per millisecond=294 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 35 ms. (steps per millisecond=285 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 66 ms. (steps per millisecond=151 ) properties (out of 5) seen :0
Interrupted probabilistic random walk after 21383 steps, run timeout after 3001 ms. (steps per millisecond=7 ) properties seen :{}
Probabilistic random walk after 21383 steps, saw 19029 distinct states, run finished after 3003 ms. (steps per millisecond=7 ) properties seen :0
Running SMT prover for 5 properties.
[2023-03-16 02:40:59] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:40:59] [INFO ] Invariant cache hit.
[2023-03-16 02:41:00] [INFO ] [Real]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 02:41:21] [INFO ] After 21841ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:5
[2023-03-16 02:41:22] [INFO ] [Nat]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 02:41:37] [INFO ] After 15632ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :5
[2023-03-16 02:41:37] [INFO ] State equation strengthened by 268 read => feed constraints.
[2023-03-16 02:41:46] [INFO ] After 8694ms SMT Verify possible using 268 Read/Feed constraints in natural domain returned unsat :0 sat :5
[2023-03-16 02:41:49] [INFO ] Deduced a trap composed of 64 places in 2579 ms of which 8 ms to minimize.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.refineWithTraps(DeadlockTester.java:1255)
at fr.lip6.move.gal.structural.smt.DeadlockTester.refineResultsWithTraps(DeadlockTester.java:736)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:656)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.addInvarianceKnowledge(LTLPropertySolver.java:701)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.applyKnowledgeBasedReductions(LTLPropertySolver.java:568)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.checkLTLProperty(LTLPropertySolver.java:251)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStutteringLTLTest(LTLPropertySolver.java:225)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStructuralLTLCheck(LTLPropertySolver.java:76)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:762)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 02:41:49] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 02:41:49] [INFO ] After 27642ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:5
Parikh walk visited 0 properties in 18 ms.
Support contains 8 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 174 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 174 ms. Remains : 626/626 places, 31352/31352 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 174 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 02:41:49] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:41:49] [INFO ] Invariant cache hit.
[2023-03-16 02:41:51] [INFO ] Implicit Places using invariants in 1882 ms returned []
Implicit Place search using SMT only with invariants took 1883 ms to find 0 implicit places.
[2023-03-16 02:41:51] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:41:51] [INFO ] Invariant cache hit.
[2023-03-16 02:42:00] [INFO ] Dead Transitions using invariants and state equation in 8457 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 10520 ms. Remains : 626/626 places, 31352/31352 transitions.
Knowledge obtained : [(AND (NOT p3) (NOT p1) (NOT p0) (NOT p2)), (X (NOT (AND (NOT p3) p1))), (X (NOT (AND (NOT p0) p3 p1 p2))), (X (NOT (AND p0 (NOT p3) p1 p2))), (X (NOT (AND (NOT p0) (NOT p3) p1 p2))), (X (AND (NOT p0) (NOT p3))), (X (NOT (AND p0 (NOT p3)))), (X (NOT (AND p0 p3 p1 p2))), (X (X (NOT (AND (NOT p3) p1)))), (X (X (NOT (AND (NOT p0) p3 p1 p2)))), (X (X (NOT (AND p0 (NOT p3) p1 p2)))), (X (X (NOT (AND (NOT p0) (NOT p3) p1 p2)))), (X (X (AND (NOT p0) (NOT p3)))), (X (X (NOT (AND p0 (NOT p3))))), (X (X (NOT (AND p0 p3 p1 p2))))]
False Knowledge obtained : [(F (NOT (AND (NOT p0) (NOT p3)))), (F (AND p0 (NOT p3))), (F (AND p1 (NOT p3)))]
Knowledge based reduction with 15 factoid took 836 ms. Reduced automaton from 3 states, 10 edges and 4 AP (stutter insensitive) to 3 states, 10 edges and 4 AP (stutter insensitive).
Stuttering acceptance computed with spot in 142 ms :[(AND (NOT p0) (NOT p3)), (AND (NOT p0) (NOT p3)), (AND (NOT p3) p1 (NOT p0) p2)]
Stuttering acceptance computed with spot in 144 ms :[(AND (NOT p0) (NOT p3)), (AND (NOT p0) (NOT p3)), (AND (NOT p3) p1 (NOT p0) p2)]
[2023-03-16 02:42:01] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:42:01] [INFO ] Invariant cache hit.
Could not prove EG (AND (NOT p0) (NOT p3))
Support contains 8 out of 626 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 169 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 02:42:16] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:42:16] [INFO ] Invariant cache hit.
[2023-03-16 02:42:18] [INFO ] Implicit Places using invariants in 1809 ms returned []
Implicit Place search using SMT only with invariants took 1811 ms to find 0 implicit places.
[2023-03-16 02:42:18] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:42:18] [INFO ] Invariant cache hit.
[2023-03-16 02:42:27] [INFO ] Dead Transitions using invariants and state equation in 8558 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 10541 ms. Remains : 626/626 places, 31352/31352 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Knowledge obtained : [(AND (NOT p3) (NOT p1) (NOT p0) (NOT p2)), (X (NOT (AND p1 p2 p0 (NOT p3)))), (X (NOT (AND p1 p2 (NOT p0) p3))), (X (AND (NOT p0) (NOT p3))), (X (NOT (AND p1 p2 p0 p3))), (X (NOT (AND p1 (NOT p3)))), (X (NOT (AND p0 (NOT p3)))), (X (NOT (AND p1 p2 (NOT p0) (NOT p3)))), (X (X (NOT (AND p1 p2 p0 (NOT p3))))), (X (X (NOT (AND p1 p2 (NOT p0) p3)))), (X (X (AND (NOT p0) (NOT p3)))), (X (X (NOT (AND p1 p2 p0 p3)))), (X (X (NOT (AND p1 (NOT p3))))), (X (X (NOT (AND p0 (NOT p3))))), (X (X (NOT (AND p1 p2 (NOT p0) (NOT p3)))))]
False Knowledge obtained : []
Knowledge based reduction with 15 factoid took 640 ms. Reduced automaton from 3 states, 10 edges and 4 AP (stutter insensitive) to 3 states, 10 edges and 4 AP (stutter insensitive).
Stuttering acceptance computed with spot in 144 ms :[(AND (NOT p0) (NOT p3)), (AND (NOT p0) (NOT p3)), (AND (NOT p3) p1 (NOT p0) p2)]
Incomplete random walk after 10000 steps, including 2 resets, run finished after 523 ms. (steps per millisecond=19 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 40 ms. (steps per millisecond=250 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 39 ms. (steps per millisecond=256 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 38 ms. (steps per millisecond=263 ) properties (out of 8) seen :2
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 38 ms. (steps per millisecond=263 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 36 ms. (steps per millisecond=277 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 44 ms. (steps per millisecond=227 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=270 ) properties (out of 6) seen :0
Running SMT prover for 6 properties.
[2023-03-16 02:42:28] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:42:28] [INFO ] Invariant cache hit.
[2023-03-16 02:42:29] [INFO ] [Real]Absence check using 13 positive place invariants in 8 ms returned sat
[2023-03-16 02:42:52] [INFO ] After 23005ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:6
[2023-03-16 02:42:52] [INFO ] [Nat]Absence check using 13 positive place invariants in 7 ms returned sat
[2023-03-16 02:43:09] [INFO ] After 17503ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :6
[2023-03-16 02:43:09] [INFO ] State equation strengthened by 268 read => feed constraints.
[2023-03-16 02:43:17] [INFO ] After 7247ms SMT Verify possible using 268 Read/Feed constraints in natural domain returned unsat :0 sat :5
[2023-03-16 02:43:17] [INFO ] After 7248ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :5
Attempting to minimize the solution found.
Minimization took 14 ms.
[2023-03-16 02:43:17] [INFO ] After 25049ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :5
Parikh walk visited 0 properties in 28 ms.
Support contains 8 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 173 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 174 ms. Remains : 626/626 places, 31352/31352 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 536 ms. (steps per millisecond=18 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 40 ms. (steps per millisecond=250 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=270 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 39 ms. (steps per millisecond=256 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 42 ms. (steps per millisecond=238 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 40 ms. (steps per millisecond=250 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 43 ms. (steps per millisecond=232 ) properties (out of 6) seen :0
Interrupted probabilistic random walk after 21134 steps, run timeout after 3001 ms. (steps per millisecond=7 ) properties seen :{}
Probabilistic random walk after 21134 steps, saw 18806 distinct states, run finished after 3003 ms. (steps per millisecond=7 ) properties seen :0
Running SMT prover for 6 properties.
[2023-03-16 02:43:21] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:43:21] [INFO ] Invariant cache hit.
[2023-03-16 02:43:21] [INFO ] [Real]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 02:43:43] [INFO ] After 22639ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:6
[2023-03-16 02:43:44] [INFO ] [Nat]Absence check using 13 positive place invariants in 5 ms returned sat
[2023-03-16 02:44:01] [INFO ] After 17296ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :6
[2023-03-16 02:44:01] [INFO ] State equation strengthened by 268 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.checkResults(DeadlockTester.java:797)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:644)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.addInvarianceKnowledge(LTLPropertySolver.java:701)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.applyKnowledgeBasedReductions(LTLPropertySolver.java:568)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.checkLTLProperty(LTLPropertySolver.java:261)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStutteringLTLTest(LTLPropertySolver.java:225)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStructuralLTLCheck(LTLPropertySolver.java:76)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:762)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 02:44:08] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 02:44:08] [INFO ] After 25047ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:6
Parikh walk visited 0 properties in 23 ms.
Support contains 8 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 171 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 171 ms. Remains : 626/626 places, 31352/31352 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 171 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 02:44:09] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:44:09] [INFO ] Invariant cache hit.
[2023-03-16 02:44:11] [INFO ] Implicit Places using invariants in 1877 ms returned []
Implicit Place search using SMT only with invariants took 1878 ms to find 0 implicit places.
[2023-03-16 02:44:11] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:44:11] [INFO ] Invariant cache hit.
[2023-03-16 02:44:19] [INFO ] Dead Transitions using invariants and state equation in 8204 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 10257 ms. Remains : 626/626 places, 31352/31352 transitions.
Knowledge obtained : [(AND (NOT p3) (NOT p1) (NOT p0) (NOT p2)), (X (NOT (AND p1 p2 p0 (NOT p3)))), (X (NOT (AND p1 p2 (NOT p0) p3))), (X (AND (NOT p0) (NOT p3))), (X (NOT (AND p1 p2 p0 p3))), (X (NOT (AND p1 (NOT p3)))), (X (NOT (AND p0 (NOT p3)))), (X (NOT (AND p1 p2 (NOT p0) (NOT p3)))), (X (X (NOT (AND p1 p2 p0 (NOT p3))))), (X (X (NOT (AND p1 p2 (NOT p0) p3)))), (X (X (AND (NOT p0) (NOT p3)))), (X (X (NOT (AND p1 p2 p0 p3)))), (X (X (NOT (AND p1 (NOT p3))))), (X (X (NOT (AND p0 (NOT p3))))), (X (X (NOT (AND p1 p2 (NOT p0) (NOT p3)))))]
False Knowledge obtained : [(F (NOT (AND (NOT p0) (NOT p3)))), (F (AND p0 (NOT p3)))]
Knowledge based reduction with 15 factoid took 719 ms. Reduced automaton from 3 states, 10 edges and 4 AP (stutter insensitive) to 3 states, 10 edges and 4 AP (stutter insensitive).
Stuttering acceptance computed with spot in 151 ms :[(AND (NOT p0) (NOT p3)), (AND (NOT p0) (NOT p3)), (AND (NOT p3) p1 (NOT p0) p2)]
Stuttering acceptance computed with spot in 126 ms :[(AND (NOT p0) (NOT p3)), (AND (NOT p0) (NOT p3)), (AND (NOT p3) p1 (NOT p0) p2)]
[2023-03-16 02:44:20] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:44:20] [INFO ] Invariant cache hit.
Could not prove EG (AND (NOT p0) (NOT p3))
Stuttering acceptance computed with spot in 133 ms :[(AND (NOT p0) (NOT p3)), (AND (NOT p0) (NOT p3)), (AND (NOT p3) p1 (NOT p0) p2)]
Product exploration explored 100000 steps with 0 reset in 3019 ms.
Product exploration explored 100000 steps with 0 reset in 3091 ms.
Support contains 8 out of 626 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 161 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 02:44:42] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:44:42] [INFO ] Invariant cache hit.
[2023-03-16 02:44:43] [INFO ] Implicit Places using invariants in 1910 ms returned []
Implicit Place search using SMT only with invariants took 1911 ms to find 0 implicit places.
[2023-03-16 02:44:43] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:44:43] [INFO ] Invariant cache hit.
[2023-03-16 02:44:52] [INFO ] Dead Transitions using invariants and state equation in 8280 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 10353 ms. Remains : 626/626 places, 31352/31352 transitions.
Treatment of property RERS17pb113-PT-3-LTLFireability-00 finished in 306180 ms.
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!(F((!(!p0 U (p1 U G(!X(p2))))&&!p0)))'
Support contains 6 out of 627 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 71 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
[2023-03-16 02:44:53] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
// Phase 1: matrix 18326 rows 627 cols
[2023-03-16 02:44:53] [INFO ] Computed 13 place invariants in 52 ms
[2023-03-16 02:44:55] [INFO ] Implicit Places using invariants in 1889 ms returned []
Implicit Place search using SMT only with invariants took 1890 ms to find 0 implicit places.
[2023-03-16 02:44:55] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 02:44:55] [INFO ] Invariant cache hit.
[2023-03-16 02:45:03] [INFO ] Dead Transitions using invariants and state equation in 8573 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10537 ms. Remains : 627/627 places, 31353/31353 transitions.
Stuttering acceptance computed with spot in 163 ms :[(OR (NOT p2) p0), (NOT p2), false, false]
Running random walk in product with property : RERS17pb113-PT-3-LTLFireability-02 automaton TGBA Formula[mat=[[{ cond=p0, acceptance={0} source=0 dest: 0}, { cond=(NOT p0), acceptance={} source=0 dest: 1}, { cond=(NOT p0), acceptance={} source=0 dest: 2}], [{ cond=(NOT p2), acceptance={0} source=1 dest: 1}], [{ cond=p2, acceptance={} source=2 dest: 1}, { cond=(NOT p0), acceptance={} source=2 dest: 2}, { cond=(AND p0 p1), acceptance={} source=2 dest: 3}], [{ cond=p2, acceptance={} source=3 dest: 1}, { cond=p1, acceptance={} source=3 dest: 3}]], initial=0, aps=[p0:(AND (GEQ s64 1) (GEQ s121 1)), p2:(AND (GEQ s0 1) (GEQ s430 1)), p1:(AND (GEQ s109 1) (GEQ s479 1))], nbAcceptance=1, properties=[trans-labels, explicit-labels, trans-acc, no-univ-branch, stutter-sensitive], stateDesc=[null, null, null, null][false, false, false, false]]
Product exploration explored 100000 steps with 0 reset in 3367 ms.
Product exploration explored 100000 steps with 0 reset in 3119 ms.
Computed a total of 1 stabilizing places and 1 stable transitions
Computed a total of 1 stabilizing places and 1 stable transitions
Knowledge obtained : [(AND (NOT p0) (NOT p2) (NOT p1)), (X (NOT p2)), (X (NOT (AND p0 p1))), (X (NOT p0)), (X (X (NOT p2))), (X (X (NOT (AND p0 p1)))), (X (X (NOT p0))), (X (X (NOT p1)))]
False Knowledge obtained : []
Knowledge based reduction with 8 factoid took 416 ms. Reduced automaton from 4 states, 9 edges and 3 AP (stutter sensitive) to 4 states, 8 edges and 3 AP (stutter sensitive).
Stuttering acceptance computed with spot in 164 ms :[(NOT p2), (NOT p2), false, false]
Incomplete random walk after 10000 steps, including 2 resets, run finished after 441 ms. (steps per millisecond=22 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 36 ms. (steps per millisecond=277 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 34 ms. (steps per millisecond=294 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 36 ms. (steps per millisecond=277 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 36 ms. (steps per millisecond=277 ) properties (out of 4) seen :0
Interrupted probabilistic random walk after 23950 steps, run timeout after 3002 ms. (steps per millisecond=7 ) properties seen :{}
Probabilistic random walk after 23950 steps, saw 21451 distinct states, run finished after 3002 ms. (steps per millisecond=7 ) properties seen :0
Running SMT prover for 4 properties.
[2023-03-16 02:45:15] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 02:45:15] [INFO ] Invariant cache hit.
[2023-03-16 02:45:15] [INFO ] [Real]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 02:45:34] [INFO ] After 19782ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:4
[2023-03-16 02:45:34] [INFO ] [Nat]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 02:45:54] [INFO ] After 19977ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :4
[2023-03-16 02:45:55] [INFO ] State equation strengthened by 829 read => feed constraints.
[2023-03-16 02:45:59] [INFO ] After 4785ms SMT Verify possible using 829 Read/Feed constraints in natural domain returned unsat :0 sat :3
[2023-03-16 02:45:59] [INFO ] After 4788ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :3
Attempting to minimize the solution found.
Minimization took 10 ms.
[2023-03-16 02:45:59] [INFO ] After 25045ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :3
Parikh walk visited 0 properties in 16 ms.
Support contains 6 out of 627 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 0 with 1 rules applied. Total rules applied 1 place count 626 transition count 31352
Applied a total of 1 rules in 374 ms. Remains 626 /627 variables (removed 1) and now considering 31352/31353 (removed 1) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 375 ms. Remains : 626/627 places, 31352/31353 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 519 ms. (steps per millisecond=19 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 46 ms. (steps per millisecond=217 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 46 ms. (steps per millisecond=217 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 44 ms. (steps per millisecond=227 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 45 ms. (steps per millisecond=222 ) properties (out of 4) seen :0
Interrupted probabilistic random walk after 20109 steps, run timeout after 3001 ms. (steps per millisecond=6 ) properties seen :{}
Probabilistic random walk after 20109 steps, saw 17905 distinct states, run finished after 3001 ms. (steps per millisecond=6 ) properties seen :0
Running SMT prover for 4 properties.
[2023-03-16 02:46:04] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
// Phase 1: matrix 18325 rows 626 cols
[2023-03-16 02:46:04] [INFO ] Computed 13 place invariants in 53 ms
[2023-03-16 02:46:04] [INFO ] [Real]Absence check using 13 positive place invariants in 8 ms returned sat
[2023-03-16 02:46:28] [INFO ] After 24195ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:4
[2023-03-16 02:46:28] [INFO ] [Nat]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 02:46:52] [INFO ] After 23615ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :4
[2023-03-16 02:46:52] [INFO ] State equation strengthened by 268 read => feed constraints.
[2023-03-16 02:46:53] [INFO ] After 1187ms SMT Verify possible using 268 Read/Feed constraints in natural domain returned unsat :0 sat :3
[2023-03-16 02:46:53] [INFO ] After 1188ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :3
Attempting to minimize the solution found.
Minimization took 7 ms.
[2023-03-16 02:46:53] [INFO ] After 25045ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :3
Parikh walk visited 0 properties in 18 ms.
Support contains 6 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 175 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 176 ms. Remains : 626/626 places, 31352/31352 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 176 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 02:46:53] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:46:53] [INFO ] Invariant cache hit.
[2023-03-16 02:46:55] [INFO ] Implicit Places using invariants in 1819 ms returned []
Implicit Place search using SMT only with invariants took 1820 ms to find 0 implicit places.
[2023-03-16 02:46:55] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:46:55] [INFO ] Invariant cache hit.
[2023-03-16 02:47:04] [INFO ] Dead Transitions using invariants and state equation in 8531 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 10533 ms. Remains : 626/626 places, 31352/31352 transitions.
Knowledge obtained : [(AND (NOT p0) (NOT p2) (NOT p1)), (X (NOT p2)), (X (NOT (AND p0 p1))), (X (NOT p0)), (X (X (NOT p2))), (X (X (NOT (AND p0 p1)))), (X (X (NOT p0))), (X (X (NOT p1)))]
False Knowledge obtained : []
Knowledge based reduction with 8 factoid took 404 ms. Reduced automaton from 4 states, 8 edges and 3 AP (stutter sensitive) to 4 states, 8 edges and 3 AP (stutter sensitive).
Stuttering acceptance computed with spot in 160 ms :[(NOT p2), (NOT p2), false, false]
Stuttering acceptance computed with spot in 143 ms :[(NOT p2), (NOT p2), false, false]
[2023-03-16 02:47:04] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
// Phase 1: matrix 18326 rows 627 cols
[2023-03-16 02:47:05] [INFO ] Computed 13 place invariants in 57 ms
Could not prove EG (NOT p2)
Support contains 6 out of 627 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 74 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
[2023-03-16 02:47:20] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 02:47:20] [INFO ] Invariant cache hit.
[2023-03-16 02:47:22] [INFO ] Implicit Places using invariants in 1947 ms returned []
Implicit Place search using SMT only with invariants took 1948 ms to find 0 implicit places.
[2023-03-16 02:47:22] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 02:47:22] [INFO ] Invariant cache hit.
[2023-03-16 02:47:30] [INFO ] Dead Transitions using invariants and state equation in 8523 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10548 ms. Remains : 627/627 places, 31353/31353 transitions.
Computed a total of 1 stabilizing places and 1 stable transitions
Computed a total of 1 stabilizing places and 1 stable transitions
Knowledge obtained : [(AND (NOT p2) (NOT p0) (NOT p1)), (X (NOT p2)), (X (NOT p0)), (X (NOT (AND p0 p1))), (X (X (NOT p2))), (X (X (NOT p0))), (X (X (NOT (AND p0 p1)))), (X (X (NOT p1)))]
False Knowledge obtained : []
Knowledge based reduction with 8 factoid took 354 ms. Reduced automaton from 4 states, 8 edges and 3 AP (stutter sensitive) to 4 states, 8 edges and 3 AP (stutter sensitive).
Stuttering acceptance computed with spot in 146 ms :[(NOT p2), (NOT p2), false, false]
Incomplete random walk after 10000 steps, including 2 resets, run finished after 405 ms. (steps per millisecond=24 ) properties (out of 4) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=312 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=312 ) properties (out of 3) seen :0
Running SMT prover for 3 properties.
[2023-03-16 02:47:31] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 02:47:31] [INFO ] Invariant cache hit.
[2023-03-16 02:47:32] [INFO ] [Real]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 02:47:52] [INFO ] After 20194ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:3
[2023-03-16 02:47:52] [INFO ] [Nat]Absence check using 13 positive place invariants in 7 ms returned sat
[2023-03-16 02:48:12] [INFO ] After 19789ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :3
[2023-03-16 02:48:12] [INFO ] State equation strengthened by 829 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Broken pipe ...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.checkResults(DeadlockTester.java:797)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:644)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.addInvarianceKnowledge(LTLPropertySolver.java:701)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.applyKnowledgeBasedReductions(LTLPropertySolver.java:568)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.checkLTLProperty(LTLPropertySolver.java:261)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStutteringLTLTest(LTLPropertySolver.java:225)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStructuralLTLCheck(LTLPropertySolver.java:76)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:762)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 02:48:17] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 02:48:17] [INFO ] After 25036ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:3
Parikh walk visited 0 properties in 13 ms.
Support contains 6 out of 627 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 0 with 1 rules applied. Total rules applied 1 place count 626 transition count 31352
Applied a total of 1 rules in 311 ms. Remains 626 /627 variables (removed 1) and now considering 31352/31353 (removed 1) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 312 ms. Remains : 626/627 places, 31352/31353 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 487 ms. (steps per millisecond=20 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 41 ms. (steps per millisecond=243 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 39 ms. (steps per millisecond=256 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 41 ms. (steps per millisecond=243 ) properties (out of 3) seen :0
Interrupted probabilistic random walk after 20602 steps, run timeout after 3001 ms. (steps per millisecond=6 ) properties seen :{}
Probabilistic random walk after 20602 steps, saw 18340 distinct states, run finished after 3001 ms. (steps per millisecond=6 ) properties seen :0
Running SMT prover for 3 properties.
[2023-03-16 02:48:21] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
// Phase 1: matrix 18325 rows 626 cols
[2023-03-16 02:48:21] [INFO ] Computed 13 place invariants in 54 ms
[2023-03-16 02:48:21] [INFO ] [Real]Absence check using 13 positive place invariants in 7 ms returned sat
[2023-03-16 02:48:45] [INFO ] After 24006ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:3
[2023-03-16 02:48:45] [INFO ] [Nat]Absence check using 13 positive place invariants in 7 ms returned sat
[2023-03-16 02:49:08] [INFO ] After 23167ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :3
[2023-03-16 02:49:08] [INFO ] State equation strengthened by 268 read => feed constraints.
[2023-03-16 02:49:10] [INFO ] After 1634ms SMT Verify possible using 268 Read/Feed constraints in natural domain returned unsat :0 sat :2
[2023-03-16 02:49:10] [INFO ] After 1635ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 7 ms.
[2023-03-16 02:49:10] [INFO ] After 25037ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
Parikh walk visited 0 properties in 13 ms.
Support contains 6 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 163 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 163 ms. Remains : 626/626 places, 31352/31352 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 161 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 02:49:10] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:49:10] [INFO ] Invariant cache hit.
[2023-03-16 02:49:12] [INFO ] Implicit Places using invariants in 1949 ms returned []
Implicit Place search using SMT only with invariants took 1950 ms to find 0 implicit places.
[2023-03-16 02:49:12] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:49:12] [INFO ] Invariant cache hit.
[2023-03-16 02:49:21] [INFO ] Dead Transitions using invariants and state equation in 8529 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 10643 ms. Remains : 626/626 places, 31352/31352 transitions.
Knowledge obtained : [(AND (NOT p2) (NOT p0) (NOT p1)), (X (NOT p2)), (X (NOT p0)), (X (NOT (AND p0 p1))), (X (X (NOT p2))), (X (X (NOT p0))), (X (X (NOT (AND p0 p1)))), (X (X (NOT p1)))]
False Knowledge obtained : [(F p1)]
Knowledge based reduction with 8 factoid took 436 ms. Reduced automaton from 4 states, 8 edges and 3 AP (stutter sensitive) to 4 states, 8 edges and 3 AP (stutter sensitive).
Stuttering acceptance computed with spot in 156 ms :[(NOT p2), (NOT p2), false, false]
Stuttering acceptance computed with spot in 163 ms :[(NOT p2), (NOT p2), false, false]
[2023-03-16 02:49:21] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
// Phase 1: matrix 18326 rows 627 cols
[2023-03-16 02:49:22] [INFO ] Computed 13 place invariants in 54 ms
Could not prove EG (NOT p2)
Stuttering acceptance computed with spot in 163 ms :[(NOT p2), (NOT p2), false, false]
Product exploration explored 100000 steps with 0 reset in 3137 ms.
Product exploration explored 100000 steps with 0 reset in 3198 ms.
Applying partial POR strategy [false, true, false, false]
Stuttering acceptance computed with spot in 151 ms :[(NOT p2), (NOT p2), false, false]
Support contains 6 out of 627 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 238 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
[2023-03-16 02:49:44] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 02:49:44] [INFO ] Invariant cache hit.
[2023-03-16 02:49:52] [INFO ] Dead Transitions using invariants and state equation in 8686 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 8925 ms. Remains : 627/627 places, 31353/31353 transitions.
Support contains 6 out of 627 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 76 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
[2023-03-16 02:49:52] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 02:49:52] [INFO ] Invariant cache hit.
[2023-03-16 02:49:54] [INFO ] Implicit Places using invariants in 1874 ms returned []
Implicit Place search using SMT only with invariants took 1875 ms to find 0 implicit places.
[2023-03-16 02:49:54] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 02:49:54] [INFO ] Invariant cache hit.
[2023-03-16 02:50:03] [INFO ] Dead Transitions using invariants and state equation in 8620 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10574 ms. Remains : 627/627 places, 31353/31353 transitions.
Treatment of property RERS17pb113-PT-3-LTLFireability-02 finished in 310971 ms.
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!((X(G(p0)) U (G(p2)&&p1)))'
Support contains 6 out of 627 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 74 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
[2023-03-16 02:50:04] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 02:50:04] [INFO ] Invariant cache hit.
[2023-03-16 02:50:06] [INFO ] Implicit Places using invariants in 1931 ms returned []
Implicit Place search using SMT only with invariants took 1932 ms to find 0 implicit places.
[2023-03-16 02:50:06] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 02:50:06] [INFO ] Invariant cache hit.
[2023-03-16 02:50:14] [INFO ] Dead Transitions using invariants and state equation in 8308 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10316 ms. Remains : 627/627 places, 31353/31353 transitions.
Stuttering acceptance computed with spot in 166 ms :[(OR (NOT p2) (NOT p1)), (NOT p0), (NOT p2), true, (AND (NOT p2) p0)]
Running random walk in product with property : RERS17pb113-PT-3-LTLFireability-04 automaton TGBA Formula[mat=[[{ cond=(OR (NOT p1) (NOT p2)), acceptance={0} source=0 dest: 0}, { cond=(OR (NOT p1) (NOT p2)), acceptance={} source=0 dest: 1}, { cond=(AND p1 p2), acceptance={} source=0 dest: 2}], [{ cond=p0, acceptance={} source=1 dest: 1}, { cond=(NOT p0), acceptance={} source=1 dest: 3}], [{ cond=(AND (NOT p2) p0), acceptance={0} source=2 dest: 0}, { cond=(AND (NOT p2) p0), acceptance={} source=2 dest: 1}, { cond=p2, acceptance={} source=2 dest: 2}, { cond=(AND (NOT p2) (NOT p0)), acceptance={} source=2 dest: 3}, { cond=(AND p2 (NOT p0)), acceptance={} source=2 dest: 4}], [{ cond=true, acceptance={0} source=3 dest: 3}], [{ cond=(AND (NOT p2) p0), acceptance={} source=4 dest: 3}, { cond=(AND p2 p0), acceptance={} source=4 dest: 4}]], initial=0, aps=[p1:(AND (GEQ s238 1) (GEQ s392 1)), p2:(AND (GEQ s86 1) (GEQ s132 1)), p0:(OR (AND (GEQ s26 1) (GEQ s284 1)) (AND (GEQ s86 1) (GEQ s132 1)))], nbAcceptance=1, properties=[trans-labels, explicit-labels, trans-acc, no-univ-branch, stutter-sensitive], stateDesc=[null, null, null, null, null][false, false, false, false, false]]
Entered a terminal (fully accepting) state of product in 2 steps with 0 reset in 1 ms.
FORMULA RERS17pb113-PT-3-LTLFireability-04 FALSE TECHNIQUES STUTTER_TEST
Treatment of property RERS17pb113-PT-3-LTLFireability-04 finished in 10581 ms.
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!(X(G((X(X(G(p1)))||p0))))'
Support contains 4 out of 627 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 76 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
[2023-03-16 02:50:15] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 02:50:15] [INFO ] Invariant cache hit.
[2023-03-16 02:50:16] [INFO ] Implicit Places using invariants in 1905 ms returned []
Implicit Place search using SMT only with invariants took 1906 ms to find 0 implicit places.
[2023-03-16 02:50:16] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 02:50:16] [INFO ] Invariant cache hit.
[2023-03-16 02:50:25] [INFO ] Dead Transitions using invariants and state equation in 8465 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10448 ms. Remains : 627/627 places, 31353/31353 transitions.
Stuttering acceptance computed with spot in 171 ms :[true, (NOT p1), (AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0)), (NOT p1)]
Running random walk in product with property : RERS17pb113-PT-3-LTLFireability-05 automaton TGBA Formula[mat=[[{ cond=true, acceptance={0} source=0 dest: 0}], [{ cond=true, acceptance={} source=1 dest: 4}], [{ cond=true, acceptance={} source=2 dest: 3}], [{ cond=(NOT p0), acceptance={} source=3 dest: 1}, { cond=p0, acceptance={} source=3 dest: 3}], [{ cond=(NOT p1), acceptance={} source=4 dest: 0}, { cond=p1, acceptance={} source=4 dest: 4}]], initial=2, aps=[p0:(OR (LT s471 1) (LT s605 1)), p1:(OR (LT s76 1) (LT s277 1))], nbAcceptance=1, properties=[trans-labels, explicit-labels, trans-acc, complete, deterministic, no-univ-branch, unambiguous, semi-deterministic, stutter-sensitive, terminal, very-weak, weak, inherently-weak], stateDesc=[null, null, null, null, null][false, false, false, false, false]]
Product exploration explored 100000 steps with 0 reset in 3286 ms.
Product exploration explored 100000 steps with 0 reset in 3806 ms.
Computed a total of 1 stabilizing places and 1 stable transitions
Computed a total of 1 stabilizing places and 1 stable transitions
Knowledge obtained : [(AND p0 p1), (X p0), true, (X (X p0))]
False Knowledge obtained : []
Knowledge based reduction with 4 factoid took 156 ms. Reduced automaton from 5 states, 7 edges and 2 AP (stutter sensitive) to 5 states, 7 edges and 2 AP (stutter sensitive).
Stuttering acceptance computed with spot in 159 ms :[true, (NOT p1), (NOT p1), (AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0))]
Incomplete random walk after 10000 steps, including 2 resets, run finished after 376 ms. (steps per millisecond=26 ) properties (out of 2) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-16 02:50:33] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 02:50:33] [INFO ] Invariant cache hit.
[2023-03-16 02:50:33] [INFO ] [Real]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 02:50:50] [INFO ] After 16842ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-16 02:50:50] [INFO ] State equation strengthened by 829 read => feed constraints.
[2023-03-16 02:50:58] [INFO ] After 7958ms SMT Verify possible using 829 Read/Feed constraints in real domain returned unsat :0 sat :0
[2023-03-16 02:50:58] [INFO ] After 25026ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 6 ms.
Support contains 2 out of 627 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 0 with 1 rules applied. Total rules applied 1 place count 626 transition count 31352
Applied a total of 1 rules in 347 ms. Remains 626 /627 variables (removed 1) and now considering 31352/31353 (removed 1) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 348 ms. Remains : 626/627 places, 31352/31353 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 308 ms. (steps per millisecond=32 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=370 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 22785 steps, run timeout after 3001 ms. (steps per millisecond=7 ) properties seen :{}
Probabilistic random walk after 22785 steps, saw 20262 distinct states, run finished after 3001 ms. (steps per millisecond=7 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-16 02:51:02] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
// Phase 1: matrix 18325 rows 626 cols
[2023-03-16 02:51:02] [INFO ] Computed 13 place invariants in 53 ms
[2023-03-16 02:51:02] [INFO ] [Real]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 02:51:23] [INFO ] After 20671ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-16 02:51:23] [INFO ] State equation strengthened by 268 read => feed constraints.
[2023-03-16 02:51:27] [INFO ] After 4171ms SMT Verify possible using 268 Read/Feed constraints in real domain returned unsat :0 sat :0
[2023-03-16 02:51:27] [INFO ] After 25031ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 11 ms.
Support contains 2 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 161 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 162 ms. Remains : 626/626 places, 31352/31352 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 160 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 02:51:27] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:51:27] [INFO ] Invariant cache hit.
[2023-03-16 02:51:29] [INFO ] Implicit Places using invariants in 1954 ms returned []
Implicit Place search using SMT only with invariants took 1969 ms to find 0 implicit places.
[2023-03-16 02:51:29] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:51:29] [INFO ] Invariant cache hit.
[2023-03-16 02:51:38] [INFO ] Dead Transitions using invariants and state equation in 8637 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 10770 ms. Remains : 626/626 places, 31352/31352 transitions.
Ensure Unique test removed 13027 transitions
Reduce isomorphic transitions removed 13027 transitions.
Iterating post reduction 0 with 13027 rules applied. Total rules applied 13027 place count 626 transition count 18325
Applied a total of 13027 rules in 667 ms. Remains 626 /626 variables (removed 0) and now considering 18325/31352 (removed 13027) transitions.
Running SMT prover for 1 properties.
// Phase 1: matrix 18325 rows 626 cols
[2023-03-16 02:51:39] [INFO ] Computed 13 place invariants in 52 ms
[2023-03-16 02:51:39] [INFO ] [Real]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 02:51:55] [INFO ] After 16116ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-16 02:51:55] [INFO ] [Nat]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 02:52:11] [INFO ] After 15908ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-16 02:52:12] [INFO ] After 16842ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 675 ms.
[2023-03-16 02:52:13] [INFO ] After 17613ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Knowledge obtained : [(AND p0 p1), (X p0), true, (X (X p0))]
False Knowledge obtained : [(F (NOT p1))]
Knowledge based reduction with 4 factoid took 278 ms. Reduced automaton from 5 states, 7 edges and 2 AP (stutter sensitive) to 5 states, 7 edges and 2 AP (stutter sensitive).
Stuttering acceptance computed with spot in 164 ms :[true, (NOT p1), (NOT p1), (AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0))]
Stuttering acceptance computed with spot in 157 ms :[true, (NOT p1), (NOT p1), (AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0))]
Support contains 4 out of 627 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 73 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
[2023-03-16 02:52:13] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
// Phase 1: matrix 18326 rows 627 cols
[2023-03-16 02:52:13] [INFO ] Computed 13 place invariants in 53 ms
[2023-03-16 02:52:15] [INFO ] Implicit Places using invariants in 1990 ms returned []
Implicit Place search using SMT only with invariants took 1991 ms to find 0 implicit places.
[2023-03-16 02:52:15] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 02:52:15] [INFO ] Invariant cache hit.
[2023-03-16 02:52:24] [INFO ] Dead Transitions using invariants and state equation in 8612 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10679 ms. Remains : 627/627 places, 31353/31353 transitions.
Computed a total of 1 stabilizing places and 1 stable transitions
Computed a total of 1 stabilizing places and 1 stable transitions
Knowledge obtained : [(AND p1 p0), (X p0), true, (X (X p0))]
False Knowledge obtained : []
Knowledge based reduction with 4 factoid took 172 ms. Reduced automaton from 5 states, 7 edges and 2 AP (stutter sensitive) to 5 states, 7 edges and 2 AP (stutter sensitive).
Stuttering acceptance computed with spot in 164 ms :[true, (NOT p1), (NOT p1), (AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0))]
Incomplete random walk after 10000 steps, including 2 resets, run finished after 380 ms. (steps per millisecond=26 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=312 ) properties (out of 2) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-16 02:52:25] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 02:52:25] [INFO ] Invariant cache hit.
[2023-03-16 02:52:25] [INFO ] [Real]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 02:52:42] [INFO ] After 17097ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-16 02:52:42] [INFO ] State equation strengthened by 829 read => feed constraints.
[2023-03-16 02:52:50] [INFO ] After 7633ms SMT Verify possible using 829 Read/Feed constraints in real domain returned unsat :0 sat :0
[2023-03-16 02:52:50] [INFO ] After 25029ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 9 ms.
Support contains 2 out of 627 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 0 with 1 rules applied. Total rules applied 1 place count 626 transition count 31352
Applied a total of 1 rules in 347 ms. Remains 626 /627 variables (removed 1) and now considering 31352/31353 (removed 1) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 348 ms. Remains : 626/627 places, 31352/31353 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 309 ms. (steps per millisecond=32 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=370 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 21944 steps, run timeout after 3001 ms. (steps per millisecond=7 ) properties seen :{}
Probabilistic random walk after 21944 steps, saw 19514 distinct states, run finished after 3003 ms. (steps per millisecond=7 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-16 02:52:54] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
// Phase 1: matrix 18325 rows 626 cols
[2023-03-16 02:52:54] [INFO ] Computed 13 place invariants in 55 ms
[2023-03-16 02:52:54] [INFO ] [Real]Absence check using 13 positive place invariants in 7 ms returned sat
[2023-03-16 02:53:15] [INFO ] After 20776ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-16 02:53:15] [INFO ] State equation strengthened by 268 read => feed constraints.
[2023-03-16 02:53:19] [INFO ] After 4068ms SMT Verify possible using 268 Read/Feed constraints in real domain returned unsat :0 sat :0
[2023-03-16 02:53:19] [INFO ] After 25029ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 7 ms.
Support contains 2 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 181 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 181 ms. Remains : 626/626 places, 31352/31352 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 176 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 02:53:19] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:53:19] [INFO ] Invariant cache hit.
[2023-03-16 02:53:21] [INFO ] Implicit Places using invariants in 1852 ms returned []
Implicit Place search using SMT only with invariants took 1865 ms to find 0 implicit places.
[2023-03-16 02:53:21] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:53:21] [INFO ] Invariant cache hit.
[2023-03-16 02:53:29] [INFO ] Dead Transitions using invariants and state equation in 8319 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 10365 ms. Remains : 626/626 places, 31352/31352 transitions.
Ensure Unique test removed 13027 transitions
Reduce isomorphic transitions removed 13027 transitions.
Iterating post reduction 0 with 13027 rules applied. Total rules applied 13027 place count 626 transition count 18325
Applied a total of 13027 rules in 552 ms. Remains 626 /626 variables (removed 0) and now considering 18325/31352 (removed 13027) transitions.
Running SMT prover for 1 properties.
// Phase 1: matrix 18325 rows 626 cols
[2023-03-16 02:53:30] [INFO ] Computed 13 place invariants in 49 ms
[2023-03-16 02:53:30] [INFO ] [Real]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 02:53:46] [INFO ] After 16273ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-16 02:53:46] [INFO ] [Nat]Absence check using 13 positive place invariants in 10 ms returned sat
[2023-03-16 02:54:02] [INFO ] After 15962ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-16 02:54:03] [INFO ] After 16893ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 624 ms.
[2023-03-16 02:54:04] [INFO ] After 17622ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Knowledge obtained : [(AND p1 p0), (X p0), true, (X (X p0))]
False Knowledge obtained : [(F (NOT p1))]
Knowledge based reduction with 4 factoid took 194 ms. Reduced automaton from 5 states, 7 edges and 2 AP (stutter sensitive) to 5 states, 7 edges and 2 AP (stutter sensitive).
Stuttering acceptance computed with spot in 159 ms :[true, (NOT p1), (NOT p1), (AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0))]
Stuttering acceptance computed with spot in 141 ms :[true, (NOT p1), (NOT p1), (AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0))]
Stuttering acceptance computed with spot in 157 ms :[true, (NOT p1), (NOT p1), (AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0))]
Product exploration explored 100000 steps with 0 reset in 3464 ms.
Product exploration explored 100000 steps with 0 reset in 3618 ms.
Applying partial POR strategy [true, true, false, false, false]
Stuttering acceptance computed with spot in 163 ms :[true, (NOT p1), (NOT p1), (AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0))]
Support contains 4 out of 627 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 185 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
[2023-03-16 02:54:12] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
// Phase 1: matrix 18326 rows 627 cols
[2023-03-16 02:54:12] [INFO ] Computed 13 place invariants in 54 ms
[2023-03-16 02:54:21] [INFO ] Dead Transitions using invariants and state equation in 8866 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 9052 ms. Remains : 627/627 places, 31353/31353 transitions.
Support contains 4 out of 627 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 73 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
[2023-03-16 02:54:21] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 02:54:21] [INFO ] Invariant cache hit.
[2023-03-16 02:54:23] [INFO ] Implicit Places using invariants in 1957 ms returned []
Implicit Place search using SMT only with invariants took 1958 ms to find 0 implicit places.
[2023-03-16 02:54:23] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 02:54:23] [INFO ] Invariant cache hit.
[2023-03-16 02:54:32] [INFO ] Dead Transitions using invariants and state equation in 8547 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10580 ms. Remains : 627/627 places, 31353/31353 transitions.
Treatment of property RERS17pb113-PT-3-LTLFireability-05 finished in 258271 ms.
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!((p0 U (G(F(p0)) U ((p2 U p3)&&p1))))'
Support contains 6 out of 627 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 330 ms. Remains 626 /627 variables (removed 1) and now considering 31352/31353 (removed 1) transitions.
[2023-03-16 02:54:33] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
// Phase 1: matrix 18325 rows 626 cols
[2023-03-16 02:54:33] [INFO ] Computed 13 place invariants in 53 ms
[2023-03-16 02:54:35] [INFO ] Implicit Places using invariants in 1887 ms returned []
Implicit Place search using SMT only with invariants took 1888 ms to find 0 implicit places.
[2023-03-16 02:54:35] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:54:35] [INFO ] Invariant cache hit.
[2023-03-16 02:54:44] [INFO ] Dead Transitions using invariants and state equation in 8704 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 10924 ms. Remains : 626/627 places, 31352/31353 transitions.
Stuttering acceptance computed with spot in 307 ms :[(OR (NOT p1) (NOT p3)), (NOT p0), (NOT p0), (OR (NOT p1) (NOT p3)), (NOT p3), (NOT p3)]
Running random walk in product with property : RERS17pb113-PT-3-LTLFireability-06 automaton TGBA Formula[mat=[[{ cond=(OR (AND (NOT p1) p0) (AND (NOT p3) (NOT p2) p0)), acceptance={0} source=0 dest: 0}, { cond=(OR (AND (NOT p1) (NOT p0)) (AND (NOT p3) (NOT p2) (NOT p0))), acceptance={} source=0 dest: 1}, { cond=(OR (AND (NOT p1) (NOT p0)) (AND (NOT p3) (NOT p2) (NOT p0))), acceptance={} source=0 dest: 2}, { cond=(OR (AND (NOT p1) (NOT p0)) (AND (NOT p3) (NOT p2) (NOT p0))), acceptance={} source=0 dest: 3}, { cond=(AND p1 (NOT p3) p2 (NOT p0)), acceptance={} source=0 dest: 4}, { cond=(AND p1 (NOT p3) p2 p0), acceptance={0} source=0 dest: 5}], [{ cond=(NOT p0), acceptance={0} source=1 dest: 1}], [{ cond=(NOT p0), acceptance={} source=2 dest: 1}, { cond=true, acceptance={} source=2 dest: 2}], [{ cond=(OR (AND (NOT p1) (NOT p0)) (AND (NOT p3) (NOT p2) (NOT p0))), acceptance={} source=3 dest: 1}, { cond=(OR (NOT p1) (AND (NOT p3) (NOT p2))), acceptance={} source=3 dest: 2}, { cond=(OR (NOT p1) (AND (NOT p3) (NOT p2))), acceptance={0} source=3 dest: 3}, { cond=(AND p1 (NOT p3) p2), acceptance={0} source=3 dest: 4}], [{ cond=(AND (NOT p3) (NOT p2) (NOT p0)), acceptance={} source=4 dest: 1}, { cond=(AND (NOT p3) (NOT p2)), acceptance={} source=4 dest: 2}, { cond=(AND (NOT p3) (NOT p2)), acceptance={0} source=4 dest: 3}, { cond=(AND (NOT p3) p2), acceptance={0} source=4 dest: 4}], [{ cond=(AND (NOT p3) (NOT p2) p0), acceptance={0} source=5 dest: 0}, { cond=(AND (NOT p3) (NOT p2) (NOT p0)), acceptance={} source=5 dest: 1}, { cond=(AND (NOT p3) (NOT p2) (NOT p0)), acceptance={} source=5 dest: 2}, { cond=(AND (NOT p3) (NOT p2) (NOT p0)), acceptance={} source=5 dest: 3}, { cond=(AND (NOT p3) p2 (NOT p0)), acceptance={} source=5 dest: 4}, { cond=(AND (NOT p3) p2 p0), acceptance={0} source=5 dest: 5}]], initial=0, aps=[p1:(AND (GEQ s335 1) (GEQ s465 1)), p0:(AND (GEQ s27 1) (GEQ s206 1)), p3:(AND (GEQ s27 1) (GEQ s206 1) (GEQ s335 1) (GEQ s465 1)), p2:(AND (GEQ s232 1) (...], nbAcceptance=1, properties=[trans-labels, explicit-labels, trans-acc, no-univ-branch, stutter-invariant], stateDesc=[null, null, null, null, null, null][true, true, true, true, true, true]]
Product exploration explored 100000 steps with 0 reset in 3156 ms.
Product exploration explored 100000 steps with 0 reset in 3228 ms.
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Knowledge obtained : [(AND (NOT p1) (NOT p0) (NOT p3) (NOT p2)), (X (NOT (AND p1 (NOT p3) p2 (NOT p0)))), (X (OR (NOT p1) (AND (NOT p3) (NOT p2)))), (X (NOT (AND p1 (NOT p3) p2))), (X (AND (NOT p3) (NOT p2) (NOT p0))), (X (NOT (AND (NOT p3) p2))), (X (NOT (AND (NOT p3) p2 p0))), (X (AND (NOT p3) (NOT p2))), (X (NOT p0)), (X (OR (AND (NOT p1) (NOT p0)) (AND (NOT p3) (NOT p2) (NOT p0)))), (X (NOT (AND p1 (NOT p3) p2 p0))), (X (NOT (AND (NOT p3) p2 (NOT p0)))), (X (NOT (OR (AND (NOT p1) p0) (AND (NOT p3) (NOT p2) p0)))), (X (NOT (AND (NOT p3) (NOT p2) p0))), (X (X (NOT (AND p1 (NOT p3) p2 (NOT p0))))), (X (X (OR (NOT p1) (AND (NOT p3) (NOT p2))))), (X (X (NOT (AND p1 (NOT p3) p2)))), (X (X (AND (NOT p3) (NOT p2) (NOT p0)))), (X (X (NOT (AND (NOT p3) p2)))), (X (X (NOT (AND (NOT p3) p2 p0)))), (X (X (AND (NOT p3) (NOT p2)))), (X (X (NOT p0))), (X (X (OR (AND (NOT p1) (NOT p0)) (AND (NOT p3) (NOT p2) (NOT p0))))), (X (X (NOT (AND p1 (NOT p3) p2 p0)))), (X (X (NOT (AND (NOT p3) p2 (NOT p0))))), true, (X (X (NOT (OR (AND (NOT p1) p0) (AND (NOT p3) (NOT p2) p0))))), (X (X (NOT (AND (NOT p3) (NOT p2) p0))))]
False Knowledge obtained : []
Knowledge based reduction with 28 factoid took 1512 ms. Reduced automaton from 6 states, 23 edges and 4 AP (stutter insensitive) to 5 states, 14 edges and 4 AP (stutter sensitive).
Stuttering acceptance computed with spot in 260 ms :[(OR (NOT p0) (NOT p3) (NOT p1)), (NOT p0), (NOT p0), (OR (NOT p3) (NOT p1)), (NOT p3)]
Incomplete random walk after 10000 steps, including 2 resets, run finished after 437 ms. (steps per millisecond=22 ) properties (out of 7) seen :3
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 36 ms. (steps per millisecond=277 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 60 ms. (steps per millisecond=166 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 50 ms. (steps per millisecond=200 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=270 ) properties (out of 4) seen :0
Running SMT prover for 4 properties.
[2023-03-16 02:54:53] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:54:53] [INFO ] Invariant cache hit.
[2023-03-16 02:54:53] [INFO ] [Real]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 02:55:08] [INFO ] After 14662ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:4
[2023-03-16 02:55:08] [INFO ] [Nat]Absence check using 13 positive place invariants in 8 ms returned sat
[2023-03-16 02:55:33] [INFO ] After 24875ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :3
[2023-03-16 02:55:33] [INFO ] State equation strengthened by 268 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.addInvarianceKnowledge(LTLPropertySolver.java:701)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.applyKnowledgeBasedReductions(LTLPropertySolver.java:568)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.checkLTLProperty(LTLPropertySolver.java:251)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStutteringLTLTest(LTLPropertySolver.java:225)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStructuralLTLCheck(LTLPropertySolver.java:76)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:762)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 02:55:33] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 02:55:33] [INFO ] After 25143ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:4
Fused 4 Parikh solutions to 3 different solutions.
Parikh walk visited 0 properties in 9 ms.
Support contains 6 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 177 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 178 ms. Remains : 626/626 places, 31352/31352 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 544 ms. (steps per millisecond=18 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=270 ) properties (out of 4) seen :2
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=270 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=270 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-16 02:55:34] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:55:34] [INFO ] Invariant cache hit.
[2023-03-16 02:55:34] [INFO ] [Real]Absence check using 13 positive place invariants in 7 ms returned sat
[2023-03-16 02:55:56] [INFO ] After 22266ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-16 02:55:56] [INFO ] [Nat]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 02:56:20] [INFO ] After 23939ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-16 02:56:20] [INFO ] State equation strengthened by 268 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Broken pipe ...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.checkResults(DeadlockTester.java:797)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:644)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.addInvarianceKnowledge(LTLPropertySolver.java:701)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.applyKnowledgeBasedReductions(LTLPropertySolver.java:568)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.checkLTLProperty(LTLPropertySolver.java:251)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStutteringLTLTest(LTLPropertySolver.java:225)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStructuralLTLCheck(LTLPropertySolver.java:76)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:762)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 02:56:21] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 02:56:21] [INFO ] After 25025ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:2
Parikh walk visited 0 properties in 9 ms.
Support contains 6 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 157 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 157 ms. Remains : 626/626 places, 31352/31352 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 413 ms. (steps per millisecond=24 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=270 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=270 ) properties (out of 2) seen :0
Interrupted probabilistic random walk after 21025 steps, run timeout after 3002 ms. (steps per millisecond=7 ) properties seen :{}
Probabilistic random walk after 21025 steps, saw 18707 distinct states, run finished after 3002 ms. (steps per millisecond=7 ) properties seen :0
Running SMT prover for 2 properties.
[2023-03-16 02:56:25] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:56:25] [INFO ] Invariant cache hit.
[2023-03-16 02:56:25] [INFO ] [Real]Absence check using 13 positive place invariants in 7 ms returned sat
[2023-03-16 02:56:47] [INFO ] After 22209ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-16 02:56:47] [INFO ] [Nat]Absence check using 13 positive place invariants in 7 ms returned sat
[2023-03-16 02:57:11] [INFO ] After 23671ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-16 02:57:11] [INFO ] State equation strengthened by 268 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Broken pipe ...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.checkResults(DeadlockTester.java:797)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:644)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.addInvarianceKnowledge(LTLPropertySolver.java:701)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.applyKnowledgeBasedReductions(LTLPropertySolver.java:568)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.checkLTLProperty(LTLPropertySolver.java:251)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStutteringLTLTest(LTLPropertySolver.java:225)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStructuralLTLCheck(LTLPropertySolver.java:76)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:762)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 02:57:12] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 02:57:12] [INFO ] After 25032ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:2
Parikh walk visited 0 properties in 10 ms.
Support contains 6 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 180 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 180 ms. Remains : 626/626 places, 31352/31352 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 178 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 02:57:12] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:57:12] [INFO ] Invariant cache hit.
[2023-03-16 02:57:14] [INFO ] Implicit Places using invariants in 1930 ms returned []
Implicit Place search using SMT only with invariants took 1940 ms to find 0 implicit places.
[2023-03-16 02:57:14] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:57:14] [INFO ] Invariant cache hit.
[2023-03-16 02:57:23] [INFO ] Dead Transitions using invariants and state equation in 8754 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 10876 ms. Remains : 626/626 places, 31352/31352 transitions.
Knowledge obtained : [(AND (NOT p1) (NOT p0) (NOT p3) (NOT p2)), (X (NOT (AND p1 (NOT p3) p2 (NOT p0)))), (X (OR (NOT p1) (AND (NOT p3) (NOT p2)))), (X (NOT (AND p1 (NOT p3) p2))), (X (AND (NOT p3) (NOT p2) (NOT p0))), (X (NOT (AND (NOT p3) p2))), (X (NOT (AND (NOT p3) p2 p0))), (X (AND (NOT p3) (NOT p2))), (X (NOT p0)), (X (OR (AND (NOT p1) (NOT p0)) (AND (NOT p3) (NOT p2) (NOT p0)))), (X (NOT (AND p1 (NOT p3) p2 p0))), (X (NOT (AND (NOT p3) p2 (NOT p0)))), (X (NOT (OR (AND (NOT p1) p0) (AND (NOT p3) (NOT p2) p0)))), (X (NOT (AND (NOT p3) (NOT p2) p0))), (X (X (NOT (AND p1 (NOT p3) p2 (NOT p0))))), (X (X (OR (NOT p1) (AND (NOT p3) (NOT p2))))), (X (X (NOT (AND p1 (NOT p3) p2)))), (X (X (AND (NOT p3) (NOT p2) (NOT p0)))), (X (X (NOT (AND (NOT p3) p2)))), (X (X (NOT (AND (NOT p3) p2 p0)))), (X (X (AND (NOT p3) (NOT p2)))), (X (X (NOT p0))), (X (X (OR (AND (NOT p1) (NOT p0)) (AND (NOT p3) (NOT p2) (NOT p0))))), (X (X (NOT (AND p1 (NOT p3) p2 p0)))), (X (X (NOT (AND (NOT p3) p2 (NOT p0))))), true, (X (X (NOT (OR (AND (NOT p1) p0) (AND (NOT p3) (NOT p2) p0))))), (X (X (NOT (AND (NOT p3) (NOT p2) p0))))]
False Knowledge obtained : [(F (NOT (AND (NOT p0) (NOT p2) (NOT p3)))), (F (AND p2 (NOT p3))), (F (NOT (AND (NOT p2) (NOT p3)))), (F p0), (F (NOT (OR (AND (NOT p0) (NOT p2) (NOT p3)) (AND (NOT p0) (NOT p1)))))]
Knowledge based reduction with 28 factoid took 1596 ms. Reduced automaton from 5 states, 14 edges and 4 AP (stutter sensitive) to 5 states, 14 edges and 4 AP (stutter sensitive).
Stuttering acceptance computed with spot in 219 ms :[(OR (NOT p0) (NOT p3) (NOT p1)), (NOT p0), (NOT p0), (OR (NOT p3) (NOT p1)), (NOT p3)]
Stuttering acceptance computed with spot in 230 ms :[(OR (NOT p0) (NOT p3) (NOT p1)), (NOT p0), (NOT p0), (OR (NOT p3) (NOT p1)), (NOT p3)]
[2023-03-16 02:57:25] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:57:25] [INFO ] Invariant cache hit.
Could not prove EG (NOT p0)
[2023-03-16 02:57:40] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:57:40] [INFO ] Invariant cache hit.
Could not prove EG (NOT p3)
[2023-03-16 02:57:55] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:57:56] [INFO ] Invariant cache hit.
Could not prove EG (NOT p1)
Support contains 6 out of 626 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 74 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 02:58:11] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:58:11] [INFO ] Invariant cache hit.
[2023-03-16 02:58:13] [INFO ] Implicit Places using invariants in 1973 ms returned []
Implicit Place search using SMT only with invariants took 1974 ms to find 0 implicit places.
[2023-03-16 02:58:13] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:58:13] [INFO ] Invariant cache hit.
[2023-03-16 02:58:21] [INFO ] Dead Transitions using invariants and state equation in 8340 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10390 ms. Remains : 626/626 places, 31352/31352 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Knowledge obtained : [(AND (NOT p0) (NOT p2) (NOT p3) (NOT p1)), (X (NOT (AND p2 (NOT p3) p1))), (X (OR (AND (NOT p2) (NOT p3)) (NOT p1))), (X (NOT p0)), (X (OR (AND (NOT p0) (NOT p2) (NOT p3)) (AND (NOT p0) (NOT p1)))), true, (X (X (NOT (AND p2 (NOT p3) p1)))), (X (X (OR (AND (NOT p2) (NOT p3)) (NOT p1)))), (X (X (NOT (AND p2 (NOT p3))))), (X (X (NOT p0))), (X (X (AND (NOT p0) (NOT p2) (NOT p3)))), (X (X (OR (AND (NOT p0) (NOT p2) (NOT p3)) (AND (NOT p0) (NOT p1))))), (X (X (AND (NOT p2) (NOT p3))))]
False Knowledge obtained : []
Knowledge based reduction with 13 factoid took 623 ms. Reduced automaton from 5 states, 14 edges and 4 AP (stutter sensitive) to 5 states, 14 edges and 4 AP (stutter sensitive).
Stuttering acceptance computed with spot in 202 ms :[(OR (NOT p0) (NOT p1) (NOT p3)), (NOT p0), (NOT p0), (OR (NOT p1) (NOT p3)), (NOT p3)]
Incomplete random walk after 10000 steps, including 2 resets, run finished after 521 ms. (steps per millisecond=19 ) properties (out of 7) seen :3
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 41 ms. (steps per millisecond=243 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 46 ms. (steps per millisecond=217 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 38 ms. (steps per millisecond=263 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 46 ms. (steps per millisecond=217 ) properties (out of 4) seen :0
Running SMT prover for 4 properties.
[2023-03-16 02:58:23] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:58:23] [INFO ] Invariant cache hit.
[2023-03-16 02:58:23] [INFO ] [Real]Absence check using 13 positive place invariants in 7 ms returned sat
[2023-03-16 02:58:37] [INFO ] After 14188ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:4
[2023-03-16 02:58:37] [INFO ] [Nat]Absence check using 13 positive place invariants in 7 ms returned sat
[2023-03-16 02:59:02] [INFO ] After 24754ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :4
[2023-03-16 02:59:02] [INFO ] State equation strengthened by 268 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.addInvarianceKnowledge(LTLPropertySolver.java:701)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.applyKnowledgeBasedReductions(LTLPropertySolver.java:568)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.checkLTLProperty(LTLPropertySolver.java:261)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStutteringLTLTest(LTLPropertySolver.java:225)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStructuralLTLCheck(LTLPropertySolver.java:76)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:762)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 02:59:02] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 02:59:02] [INFO ] After 25028ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:4
Parikh walk visited 0 properties in 23 ms.
Support contains 6 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 158 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 159 ms. Remains : 626/626 places, 31352/31352 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 554 ms. (steps per millisecond=18 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 46 ms. (steps per millisecond=217 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 50 ms. (steps per millisecond=200 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 47 ms. (steps per millisecond=212 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 48 ms. (steps per millisecond=208 ) properties (out of 4) seen :0
Interrupted probabilistic random walk after 19468 steps, run timeout after 3001 ms. (steps per millisecond=6 ) properties seen :{}
Probabilistic random walk after 19468 steps, saw 17344 distinct states, run finished after 3001 ms. (steps per millisecond=6 ) properties seen :0
Running SMT prover for 4 properties.
[2023-03-16 02:59:06] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:59:06] [INFO ] Invariant cache hit.
[2023-03-16 02:59:06] [INFO ] [Real]Absence check using 13 positive place invariants in 7 ms returned sat
[2023-03-16 02:59:21] [INFO ] After 14747ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:4
[2023-03-16 02:59:21] [INFO ] [Nat]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 02:59:46] [INFO ] After 24908ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :4
[2023-03-16 02:59:46] [INFO ] State equation strengthened by 268 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.addInvarianceKnowledge(LTLPropertySolver.java:701)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.applyKnowledgeBasedReductions(LTLPropertySolver.java:568)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.checkLTLProperty(LTLPropertySolver.java:261)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStutteringLTLTest(LTLPropertySolver.java:225)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStructuralLTLCheck(LTLPropertySolver.java:76)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:762)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 02:59:46] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 02:59:46] [INFO ] After 25165ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:4
Parikh walk visited 0 properties in 16 ms.
Support contains 6 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 179 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 179 ms. Remains : 626/626 places, 31352/31352 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 178 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 02:59:46] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:59:46] [INFO ] Invariant cache hit.
[2023-03-16 02:59:48] [INFO ] Implicit Places using invariants in 1958 ms returned []
Implicit Place search using SMT only with invariants took 1958 ms to find 0 implicit places.
[2023-03-16 02:59:48] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 02:59:48] [INFO ] Invariant cache hit.
[2023-03-16 02:59:57] [INFO ] Dead Transitions using invariants and state equation in 8696 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 10835 ms. Remains : 626/626 places, 31352/31352 transitions.
Ensure Unique test removed 13027 transitions
Reduce isomorphic transitions removed 13027 transitions.
Iterating post reduction 0 with 13027 rules applied. Total rules applied 13027 place count 626 transition count 18325
Applied a total of 13027 rules in 574 ms. Remains 626 /626 variables (removed 0) and now considering 18325/31352 (removed 13027) transitions.
Running SMT prover for 4 properties.
// Phase 1: matrix 18325 rows 626 cols
[2023-03-16 02:59:58] [INFO ] Computed 13 place invariants in 52 ms
[2023-03-16 02:59:58] [INFO ] [Real]Absence check using 13 positive place invariants in 8 ms returned sat
[2023-03-16 03:00:16] [INFO ] After 18168ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:4
[2023-03-16 03:00:16] [INFO ] [Nat]Absence check using 13 positive place invariants in 7 ms returned sat
[2023-03-16 03:00:40] [INFO ] After 23908ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :4
[2023-03-16 03:00:43] [INFO ] After 26986ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :4
Attempting to minimize the solution found.
Minimization took 2169 ms.
[2023-03-16 03:00:45] [INFO ] After 29294ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :4
Knowledge obtained : [(AND (NOT p0) (NOT p2) (NOT p3) (NOT p1)), (X (NOT (AND p2 (NOT p3) p1))), (X (OR (AND (NOT p2) (NOT p3)) (NOT p1))), (X (NOT p0)), (X (OR (AND (NOT p0) (NOT p2) (NOT p3)) (AND (NOT p0) (NOT p1)))), true, (X (X (NOT (AND p2 (NOT p3) p1)))), (X (X (OR (AND (NOT p2) (NOT p3)) (NOT p1)))), (X (X (NOT (AND p2 (NOT p3))))), (X (X (NOT p0))), (X (X (AND (NOT p0) (NOT p2) (NOT p3)))), (X (X (OR (AND (NOT p0) (NOT p2) (NOT p3)) (AND (NOT p0) (NOT p1))))), (X (X (AND (NOT p2) (NOT p3))))]
False Knowledge obtained : [(F (NOT (AND (NOT p0) (NOT p2) (NOT p3)))), (F (AND p2 (NOT p3))), (F (NOT (AND (NOT p2) (NOT p3))))]
Knowledge based reduction with 13 factoid took 774 ms. Reduced automaton from 5 states, 14 edges and 4 AP (stutter sensitive) to 5 states, 14 edges and 4 AP (stutter sensitive).
Stuttering acceptance computed with spot in 223 ms :[(OR (NOT p0) (NOT p1) (NOT p3)), (NOT p0), (NOT p0), (OR (NOT p1) (NOT p3)), (NOT p3)]
Stuttering acceptance computed with spot in 229 ms :[(OR (NOT p0) (NOT p1) (NOT p3)), (NOT p0), (NOT p0), (OR (NOT p1) (NOT p3)), (NOT p3)]
[2023-03-16 03:00:46] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
// Phase 1: matrix 18325 rows 626 cols
[2023-03-16 03:00:47] [INFO ] Computed 13 place invariants in 56 ms
Could not prove EG (NOT p0)
[2023-03-16 03:01:02] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:01:02] [INFO ] Invariant cache hit.
Could not prove EG (NOT p1)
[2023-03-16 03:01:17] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:01:17] [INFO ] Invariant cache hit.
Could not prove EG (NOT p3)
Stuttering acceptance computed with spot in 222 ms :[(OR (NOT p0) (NOT p1) (NOT p3)), (NOT p0), (NOT p0), (OR (NOT p1) (NOT p3)), (NOT p3)]
Product exploration explored 100000 steps with 0 reset in 3086 ms.
Product exploration explored 100000 steps with 0 reset in 3152 ms.
Applying partial POR strategy [false, true, true, true, true]
Stuttering acceptance computed with spot in 328 ms :[(OR (NOT p0) (NOT p1) (NOT p3)), (NOT p0), (NOT p0), (OR (NOT p1) (NOT p3)), (NOT p3)]
Support contains 6 out of 626 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 159 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 03:01:39] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:01:39] [INFO ] Invariant cache hit.
[2023-03-16 03:01:48] [INFO ] Dead Transitions using invariants and state equation in 8723 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 8882 ms. Remains : 626/626 places, 31352/31352 transitions.
Support contains 6 out of 626 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 74 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 03:01:48] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:01:48] [INFO ] Invariant cache hit.
[2023-03-16 03:01:50] [INFO ] Implicit Places using invariants in 1969 ms returned []
Implicit Place search using SMT only with invariants took 1970 ms to find 0 implicit places.
[2023-03-16 03:01:50] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:01:50] [INFO ] Invariant cache hit.
[2023-03-16 03:01:58] [INFO ] Dead Transitions using invariants and state equation in 8670 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10718 ms. Remains : 626/626 places, 31352/31352 transitions.
Treatment of property RERS17pb113-PT-3-LTLFireability-06 finished in 446603 ms.
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!((F((!p0||X(F(!p1)))) U G(p1)))'
Support contains 4 out of 627 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 170 ms. Remains 626 /627 variables (removed 1) and now considering 31352/31353 (removed 1) transitions.
[2023-03-16 03:02:00] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:02:00] [INFO ] Invariant cache hit.
[2023-03-16 03:02:01] [INFO ] Implicit Places using invariants in 1955 ms returned []
Implicit Place search using SMT only with invariants took 1956 ms to find 0 implicit places.
[2023-03-16 03:02:01] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:02:01] [INFO ] Invariant cache hit.
[2023-03-16 03:02:10] [INFO ] Dead Transitions using invariants and state equation in 8714 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 10841 ms. Remains : 626/627 places, 31352/31353 transitions.
Stuttering acceptance computed with spot in 68 ms :[(NOT p1), (AND p1 p0)]
Running random walk in product with property : RERS17pb113-PT-3-LTLFireability-07 automaton TGBA Formula[mat=[[{ cond=p1, acceptance={} source=0 dest: 0}, { cond=(NOT p1), acceptance={0} source=0 dest: 0}, { cond=(AND (NOT p1) p0), acceptance={} source=0 dest: 1}], [{ cond=(AND p1 p0), acceptance={0} source=1 dest: 1}]], initial=0, aps=[p1:(AND (GEQ s97 1) (GEQ s174 1)), p0:(AND (NOT (AND (GEQ s97 1) (GEQ s174 1))) (NOT (AND (GEQ s575 1) (GEQ s614 1))))], nbAcceptance=1, properties=[trans-labels, explicit-labels, trans-acc, no-univ-branch, stutter-invariant], stateDesc=[null, null][true, true]]
Product exploration explored 100000 steps with 33304 reset in 2102 ms.
Product exploration explored 100000 steps with 33345 reset in 2057 ms.
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Knowledge obtained : [(AND (NOT p1) p0), (X (NOT (AND p1 p0))), (X (AND (NOT p1) p0)), (X (NOT p1)), (X (X (NOT (AND p1 p0)))), (X (X (AND (NOT p1) p0))), (X (X (NOT p1)))]
False Knowledge obtained : []
Knowledge based reduction with 7 factoid took 298 ms. Reduced automaton from 2 states, 4 edges and 2 AP (stutter insensitive) to 2 states, 4 edges and 2 AP (stutter insensitive).
Stuttering acceptance computed with spot in 69 ms :[(NOT p1), (AND p1 p0)]
Incomplete random walk after 10000 steps, including 2 resets, run finished after 493 ms. (steps per millisecond=20 ) properties (out of 3) seen :2
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 39 ms. (steps per millisecond=256 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-16 03:02:16] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:02:16] [INFO ] Invariant cache hit.
[2023-03-16 03:02:16] [INFO ] After 78ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0
Fused 1 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Found 1 invariant AP formulas.
Knowledge obtained : [(AND (NOT p1) p0), (X (NOT (AND p1 p0))), (X (AND (NOT p1) p0)), (X (NOT p1)), (X (X (NOT (AND p1 p0)))), (X (X (AND (NOT p1) p0))), (X (X (NOT p1))), (G (NOT (AND p0 p1)))]
False Knowledge obtained : [(F p1), (F (NOT (AND p0 (NOT p1))))]
Knowledge based reduction with 8 factoid took 342 ms. Reduced automaton from 2 states, 4 edges and 2 AP (stutter insensitive) to 1 states, 2 edges and 1 AP (stutter insensitive).
Stuttering acceptance computed with spot in 36 ms :[(NOT p1)]
Stuttering acceptance computed with spot in 31 ms :[(NOT p1)]
[2023-03-16 03:02:16] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:02:16] [INFO ] Invariant cache hit.
Could not prove EG (NOT p1)
Support contains 2 out of 626 places. Attempting structural reductions.
Property had overlarge support with respect to TGBA, discarding it for now.
Starting structural reductions in SI_LTL mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 201 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 03:02:31] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:02:31] [INFO ] Invariant cache hit.
[2023-03-16 03:02:34] [INFO ] Implicit Places using invariants in 2132 ms returned []
Implicit Place search using SMT only with invariants took 2133 ms to find 0 implicit places.
[2023-03-16 03:02:34] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:02:34] [INFO ] Invariant cache hit.
[2023-03-16 03:02:43] [INFO ] Dead Transitions using invariants and state equation in 9002 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 11338 ms. Remains : 626/626 places, 31352/31352 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Knowledge obtained : [(NOT p1), (X (NOT p1)), (X (X (NOT p1)))]
False Knowledge obtained : []
Knowledge based reduction with 3 factoid took 115 ms. Reduced automaton from 1 states, 2 edges and 1 AP (stutter insensitive) to 1 states, 2 edges and 1 AP (stutter insensitive).
Stuttering acceptance computed with spot in 38 ms :[(NOT p1)]
Finished random walk after 5096 steps, including 1 resets, run visited all 1 properties in 168 ms. (steps per millisecond=30 )
Knowledge obtained : [(NOT p1), (X (NOT p1)), (X (X (NOT p1)))]
False Knowledge obtained : [(F p1)]
Knowledge based reduction with 3 factoid took 140 ms. Reduced automaton from 1 states, 2 edges and 1 AP (stutter insensitive) to 1 states, 2 edges and 1 AP (stutter insensitive).
Stuttering acceptance computed with spot in 35 ms :[(NOT p1)]
Stuttering acceptance computed with spot in 41 ms :[(NOT p1)]
[2023-03-16 03:02:43] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:02:44] [INFO ] Invariant cache hit.
Could not prove EG (NOT p1)
Stuttering acceptance computed with spot in 40 ms :[(NOT p1)]
Product exploration explored 100000 steps with 0 reset in 3187 ms.
Product exploration explored 100000 steps with 0 reset in 3337 ms.
Support contains 2 out of 626 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 163 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 03:03:05] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:03:05] [INFO ] Invariant cache hit.
[2023-03-16 03:03:07] [INFO ] Implicit Places using invariants in 1969 ms returned []
Implicit Place search using SMT only with invariants took 1979 ms to find 0 implicit places.
[2023-03-16 03:03:07] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:03:07] [INFO ] Invariant cache hit.
[2023-03-16 03:03:16] [INFO ] Dead Transitions using invariants and state equation in 8451 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 10595 ms. Remains : 626/626 places, 31352/31352 transitions.
Treatment of property RERS17pb113-PT-3-LTLFireability-07 finished in 77433 ms.
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!((G(p0) U (!X(p0) U p1)))'
Support contains 4 out of 627 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 80 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
[2023-03-16 03:03:17] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
// Phase 1: matrix 18326 rows 627 cols
[2023-03-16 03:03:17] [INFO ] Computed 13 place invariants in 50 ms
[2023-03-16 03:03:19] [INFO ] Implicit Places using invariants in 2011 ms returned []
Implicit Place search using SMT only with invariants took 2012 ms to find 0 implicit places.
[2023-03-16 03:03:19] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 03:03:19] [INFO ] Invariant cache hit.
[2023-03-16 03:03:27] [INFO ] Dead Transitions using invariants and state equation in 8265 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10359 ms. Remains : 627/627 places, 31353/31353 transitions.
Stuttering acceptance computed with spot in 176 ms :[(NOT p1), (OR (NOT p1) p0), false, true, (NOT p0)]
Running random walk in product with property : RERS17pb113-PT-3-LTLFireability-10 automaton TGBA Formula[mat=[[{ cond=(AND (NOT p1) p0), acceptance={0} source=0 dest: 0}, { cond=(AND (NOT p1) (NOT p0)), acceptance={0} source=0 dest: 1}, { cond=(AND (NOT p1) p0), acceptance={0} source=0 dest: 2}], [{ cond=(AND (NOT p1) (NOT p0)), acceptance={0} source=1 dest: 1}, { cond=p0, acceptance={0} source=1 dest: 3}], [{ cond=p0, acceptance={} source=2 dest: 4}], [{ cond=true, acceptance={0} source=3 dest: 3}], [{ cond=(NOT p0), acceptance={} source=4 dest: 3}, { cond=p0, acceptance={} source=4 dest: 4}]], initial=0, aps=[p1:(AND (GEQ s316 1) (GEQ s539 1)), p0:(AND (GEQ s26 1) (GEQ s476 1))], nbAcceptance=1, properties=[trans-labels, explicit-labels, trans-acc, no-univ-branch, stutter-sensitive, very-weak, weak, inherently-weak], stateDesc=[null, null, null, null, null][false, false, false, false, false]]
Product exploration explored 100000 steps with 1 reset in 3109 ms.
Product exploration explored 100000 steps with 4 reset in 3130 ms.
Computed a total of 1 stabilizing places and 1 stable transitions
Computed a total of 1 stabilizing places and 1 stable transitions
Knowledge obtained : [(AND (NOT p1) (NOT p0)), (X (NOT (AND (NOT p1) p0))), (X (AND (NOT p1) (NOT p0))), (X (NOT p0)), true, (X (X (NOT (AND (NOT p1) p0)))), (X (X (AND (NOT p1) (NOT p0)))), (X (X (NOT p0)))]
False Knowledge obtained : []
Knowledge based reduction with 8 factoid took 293 ms. Reduced automaton from 5 states, 9 edges and 2 AP (stutter sensitive) to 3 states, 4 edges and 2 AP (stutter sensitive).
Stuttering acceptance computed with spot in 76 ms :[(OR (NOT p1) p0), (OR (NOT p1) p0), true]
Incomplete random walk after 10000 steps, including 2 resets, run finished after 420 ms. (steps per millisecond=23 ) properties (out of 2) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-16 03:03:35] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 03:03:35] [INFO ] Invariant cache hit.
[2023-03-16 03:03:35] [INFO ] [Real]Absence check using 13 positive place invariants in 7 ms returned sat
[2023-03-16 03:03:58] [INFO ] After 23265ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-16 03:03:58] [INFO ] [Nat]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 03:04:21] [INFO ] After 22921ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-16 03:04:21] [INFO ] State equation strengthened by 829 read => feed constraints.
[2023-03-16 03:04:23] [INFO ] After 1896ms SMT Verify possible using 829 Read/Feed constraints in natural domain returned unsat :0 sat :0
[2023-03-16 03:04:23] [INFO ] After 25037ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 5 ms.
Support contains 2 out of 627 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 0 with 1 rules applied. Total rules applied 1 place count 626 transition count 31352
Applied a total of 1 rules in 347 ms. Remains 626 /627 variables (removed 1) and now considering 31352/31353 (removed 1) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 347 ms. Remains : 626/627 places, 31352/31353 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 301 ms. (steps per millisecond=33 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=344 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 22299 steps, run timeout after 3001 ms. (steps per millisecond=7 ) properties seen :{}
Probabilistic random walk after 22299 steps, saw 19831 distinct states, run finished after 3002 ms. (steps per millisecond=7 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-16 03:04:27] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
// Phase 1: matrix 18325 rows 626 cols
[2023-03-16 03:04:27] [INFO ] Computed 13 place invariants in 50 ms
[2023-03-16 03:04:27] [INFO ] [Real]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 03:04:45] [INFO ] After 18084ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-16 03:04:45] [INFO ] State equation strengthened by 268 read => feed constraints.
[2023-03-16 03:04:52] [INFO ] After 6763ms SMT Verify possible using 268 Read/Feed constraints in real domain returned unsat :0 sat :0
[2023-03-16 03:04:52] [INFO ] After 25031ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 9 ms.
Support contains 2 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 156 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 156 ms. Remains : 626/626 places, 31352/31352 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 155 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 03:04:52] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:04:52] [INFO ] Invariant cache hit.
[2023-03-16 03:04:54] [INFO ] Implicit Places using invariants in 2003 ms returned []
Implicit Place search using SMT only with invariants took 2004 ms to find 0 implicit places.
[2023-03-16 03:04:54] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:04:54] [INFO ] Invariant cache hit.
[2023-03-16 03:05:03] [INFO ] Dead Transitions using invariants and state equation in 8575 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 10739 ms. Remains : 626/626 places, 31352/31352 transitions.
Ensure Unique test removed 13027 transitions
Reduce isomorphic transitions removed 13027 transitions.
Iterating post reduction 0 with 13027 rules applied. Total rules applied 13027 place count 626 transition count 18325
Applied a total of 13027 rules in 552 ms. Remains 626 /626 variables (removed 0) and now considering 18325/31352 (removed 13027) transitions.
Running SMT prover for 1 properties.
// Phase 1: matrix 18325 rows 626 cols
[2023-03-16 03:05:04] [INFO ] Computed 13 place invariants in 52 ms
[2023-03-16 03:05:04] [INFO ] [Real]Absence check using 13 positive place invariants in 5 ms returned sat
[2023-03-16 03:05:23] [INFO ] After 19521ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-16 03:05:23] [INFO ] [Nat]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 03:05:38] [INFO ] After 14968ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-16 03:05:39] [INFO ] After 15635ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 386 ms.
[2023-03-16 03:05:39] [INFO ] After 16107ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Knowledge obtained : [(AND (NOT p1) (NOT p0)), (X (NOT (AND (NOT p1) p0))), (X (AND (NOT p1) (NOT p0))), (X (NOT p0)), true, (X (X (NOT (AND (NOT p1) p0)))), (X (X (AND (NOT p1) (NOT p0)))), (X (X (NOT p0)))]
False Knowledge obtained : [(F (NOT (AND (NOT p1) (NOT p0))))]
Knowledge based reduction with 8 factoid took 386 ms. Reduced automaton from 3 states, 4 edges and 2 AP (stutter sensitive) to 3 states, 4 edges and 2 AP (stutter sensitive).
Stuttering acceptance computed with spot in 113 ms :[(OR (NOT p1) p0), (OR (NOT p1) p0), true]
Stuttering acceptance computed with spot in 76 ms :[(OR (NOT p1) p0), (OR (NOT p1) p0), true]
[2023-03-16 03:05:40] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
// Phase 1: matrix 18326 rows 627 cols
[2023-03-16 03:05:40] [INFO ] Computed 13 place invariants in 54 ms
Could not prove EG (NOT p1)
Support contains 4 out of 627 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 76 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
[2023-03-16 03:05:55] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 03:05:55] [INFO ] Invariant cache hit.
[2023-03-16 03:05:57] [INFO ] Implicit Places using invariants in 1966 ms returned []
Implicit Place search using SMT only with invariants took 1967 ms to find 0 implicit places.
[2023-03-16 03:05:57] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 03:05:57] [INFO ] Invariant cache hit.
[2023-03-16 03:06:06] [INFO ] Dead Transitions using invariants and state equation in 8790 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10833 ms. Remains : 627/627 places, 31353/31353 transitions.
Computed a total of 1 stabilizing places and 1 stable transitions
Computed a total of 1 stabilizing places and 1 stable transitions
Knowledge obtained : [(AND (NOT p1) (NOT p0)), (X (AND (NOT p1) (NOT p0))), (X (NOT p0)), true, (X (X (AND (NOT p1) (NOT p0)))), (X (X (NOT p0)))]
False Knowledge obtained : []
Knowledge based reduction with 6 factoid took 214 ms. Reduced automaton from 3 states, 4 edges and 2 AP (stutter sensitive) to 3 states, 4 edges and 2 AP (stutter sensitive).
Stuttering acceptance computed with spot in 94 ms :[(OR (NOT p1) p0), (OR (NOT p1) p0), true]
Incomplete random walk after 10000 steps, including 2 resets, run finished after 414 ms. (steps per millisecond=24 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 36 ms. (steps per millisecond=277 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=270 ) properties (out of 2) seen :0
Interrupted probabilistic random walk after 24423 steps, run timeout after 3002 ms. (steps per millisecond=8 ) properties seen :{}
Probabilistic random walk after 24423 steps, saw 21886 distinct states, run finished after 3003 ms. (steps per millisecond=8 ) properties seen :0
Running SMT prover for 2 properties.
[2023-03-16 03:06:10] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 03:06:10] [INFO ] Invariant cache hit.
[2023-03-16 03:06:10] [INFO ] [Real]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 03:06:10] [INFO ] After 127ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-16 03:06:10] [INFO ] [Nat]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 03:06:35] [INFO ] After 24926ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-16 03:06:35] [INFO ] State equation strengthened by 829 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.addInvarianceKnowledge(LTLPropertySolver.java:701)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.applyKnowledgeBasedReductions(LTLPropertySolver.java:568)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.checkLTLProperty(LTLPropertySolver.java:261)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStutteringLTLTest(LTLPropertySolver.java:225)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.runStructuralLTLCheck(LTLPropertySolver.java:76)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:762)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 03:06:35] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 03:06:35] [INFO ] After 25165ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:2
Parikh walk visited 0 properties in 8 ms.
Support contains 4 out of 627 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 0 with 1 rules applied. Total rules applied 1 place count 626 transition count 31352
Applied a total of 1 rules in 309 ms. Remains 626 /627 variables (removed 1) and now considering 31352/31353 (removed 1) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 309 ms. Remains : 626/627 places, 31352/31353 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 419 ms. (steps per millisecond=23 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=270 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 36 ms. (steps per millisecond=277 ) properties (out of 2) seen :0
Interrupted probabilistic random walk after 21708 steps, run timeout after 3001 ms. (steps per millisecond=7 ) properties seen :{}
Probabilistic random walk after 21708 steps, saw 19313 distinct states, run finished after 3001 ms. (steps per millisecond=7 ) properties seen :0
Running SMT prover for 2 properties.
[2023-03-16 03:06:39] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
// Phase 1: matrix 18325 rows 626 cols
[2023-03-16 03:06:39] [INFO ] Computed 13 place invariants in 53 ms
[2023-03-16 03:06:39] [INFO ] [Real]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 03:06:39] [INFO ] After 123ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-16 03:06:39] [INFO ] [Nat]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 03:07:04] [INFO ] After 25021ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0
Fused 2 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 4 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 157 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 157 ms. Remains : 626/626 places, 31352/31352 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 156 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 03:07:05] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:07:05] [INFO ] Invariant cache hit.
[2023-03-16 03:07:07] [INFO ] Implicit Places using invariants in 1993 ms returned []
Implicit Place search using SMT only with invariants took 1993 ms to find 0 implicit places.
[2023-03-16 03:07:07] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:07:07] [INFO ] Invariant cache hit.
[2023-03-16 03:07:15] [INFO ] Dead Transitions using invariants and state equation in 8556 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 10708 ms. Remains : 626/626 places, 31352/31352 transitions.
Ensure Unique test removed 13027 transitions
Reduce isomorphic transitions removed 13027 transitions.
Iterating post reduction 0 with 13027 rules applied. Total rules applied 13027 place count 626 transition count 18325
Applied a total of 13027 rules in 566 ms. Remains 626 /626 variables (removed 0) and now considering 18325/31352 (removed 13027) transitions.
Running SMT prover for 2 properties.
// Phase 1: matrix 18325 rows 626 cols
[2023-03-16 03:07:16] [INFO ] Computed 13 place invariants in 55 ms
[2023-03-16 03:07:16] [INFO ] [Real]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 03:07:16] [INFO ] After 104ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-16 03:07:16] [INFO ] [Nat]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 03:07:35] [INFO ] After 19325ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-16 03:07:38] [INFO ] After 21574ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 1284 ms.
[2023-03-16 03:07:39] [INFO ] After 22963ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
Knowledge obtained : [(AND (NOT p1) (NOT p0)), (X (AND (NOT p1) (NOT p0))), (X (NOT p0)), true, (X (X (AND (NOT p1) (NOT p0)))), (X (X (NOT p0)))]
False Knowledge obtained : []
Knowledge based reduction with 6 factoid took 231 ms. Reduced automaton from 3 states, 4 edges and 2 AP (stutter sensitive) to 3 states, 4 edges and 2 AP (stutter sensitive).
Stuttering acceptance computed with spot in 87 ms :[(OR (NOT p1) p0), (OR (NOT p1) p0), true]
Stuttering acceptance computed with spot in 84 ms :[(OR (NOT p1) p0), (OR (NOT p1) p0), true]
[2023-03-16 03:07:39] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
// Phase 1: matrix 18326 rows 627 cols
[2023-03-16 03:07:40] [INFO ] Computed 13 place invariants in 54 ms
Could not prove EG (NOT p1)
Stuttering acceptance computed with spot in 86 ms :[(OR (NOT p1) p0), (OR (NOT p1) p0), true]
Entered a terminal (fully accepting) state of product in 24802 steps with 0 reset in 766 ms.
FORMULA RERS17pb113-PT-3-LTLFireability-10 FALSE TECHNIQUES STUTTER_TEST
Treatment of property RERS17pb113-PT-3-LTLFireability-10 finished in 278686 ms.
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!(X((F(p1)&&X(p2)&&F(!p1)&&p0)))'
Support contains 4 out of 627 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 77 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
[2023-03-16 03:07:56] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 03:07:56] [INFO ] Invariant cache hit.
[2023-03-16 03:07:57] [INFO ] Implicit Places using invariants in 1910 ms returned []
Implicit Place search using SMT only with invariants took 1910 ms to find 0 implicit places.
[2023-03-16 03:07:57] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 03:07:57] [INFO ] Invariant cache hit.
[2023-03-16 03:08:06] [INFO ] Dead Transitions using invariants and state equation in 8808 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10795 ms. Remains : 627/627 places, 31353/31353 transitions.
Stuttering acceptance computed with spot in 219 ms :[true, true, true, (NOT p1), (NOT p2), p1]
Running random walk in product with property : RERS17pb113-PT-3-LTLFireability-14 automaton TGBA Formula[mat=[[{ cond=true, acceptance={} source=0 dest: 1}], [{ cond=(NOT p0), acceptance={} source=1 dest: 2}, { cond=(AND p0 (NOT p1)), acceptance={} source=1 dest: 3}, { cond=p0, acceptance={} source=1 dest: 4}, { cond=(AND p0 p1), acceptance={} source=1 dest: 5}], [{ cond=true, acceptance={} source=2 dest: 2}], [{ cond=(NOT p1), acceptance={} source=3 dest: 3}], [{ cond=(NOT p2), acceptance={} source=4 dest: 2}], [{ cond=p1, acceptance={} source=5 dest: 5}]], initial=0, aps=[p0:(AND (GEQ s35 1) (GEQ s355 1)), p1:(AND (GEQ s35 1) (GEQ s355 1)), p2:(OR (LT s268 1) (LT s597 1))], nbAcceptance=0, properties=[trans-labels, explicit-labels, trans-acc, no-univ-branch, stutter-sensitive, very-weak, weak, inherently-weak], stateDesc=[null, null, null, null, null, null][false, false, false, false, false, false]]
Entered a terminal (fully accepting) state of product in 1 steps with 0 reset in 1 ms.
FORMULA RERS17pb113-PT-3-LTLFireability-14 FALSE TECHNIQUES STUTTER_TEST
Treatment of property RERS17pb113-PT-3-LTLFireability-14 finished in 11105 ms.
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!(F(p0))'
Support contains 2 out of 627 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 175 ms. Remains 626 /627 variables (removed 1) and now considering 31352/31353 (removed 1) transitions.
[2023-03-16 03:08:07] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
// Phase 1: matrix 18325 rows 626 cols
[2023-03-16 03:08:07] [INFO ] Computed 13 place invariants in 54 ms
[2023-03-16 03:08:09] [INFO ] Implicit Places using invariants in 2012 ms returned []
Implicit Place search using SMT only with invariants took 2013 ms to find 0 implicit places.
[2023-03-16 03:08:09] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:08:09] [INFO ] Invariant cache hit.
[2023-03-16 03:08:17] [INFO ] Dead Transitions using invariants and state equation in 8632 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 10822 ms. Remains : 626/627 places, 31352/31353 transitions.
Stuttering acceptance computed with spot in 42 ms :[(NOT p0)]
Running random walk in product with property : RERS17pb113-PT-3-LTLFireability-15 automaton TGBA Formula[mat=[[{ cond=(NOT p0), acceptance={0} source=0 dest: 0}]], initial=0, aps=[p0:(AND (GEQ s65 1) (GEQ s284 1))], nbAcceptance=1, properties=[trans-labels, explicit-labels, trans-acc, colored, deterministic, no-univ-branch, unambiguous, semi-deterministic, stutter-invariant, very-weak, weak, inherently-weak], stateDesc=[null][true]]
Product exploration explored 100000 steps with 0 reset in 3144 ms.
Product exploration explored 100000 steps with 0 reset in 3206 ms.
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Knowledge obtained : [(NOT p0), (X (NOT p0)), (X (X (NOT p0)))]
False Knowledge obtained : []
Knowledge based reduction with 3 factoid took 132 ms. Reduced automaton from 1 states, 1 edges and 1 AP (stutter insensitive) to 1 states, 1 edges and 1 AP (stutter insensitive).
Stuttering acceptance computed with spot in 36 ms :[(NOT p0)]
Incomplete random walk after 10000 steps, including 2 resets, run finished after 334 ms. (steps per millisecond=29 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 22684 steps, run timeout after 3001 ms. (steps per millisecond=7 ) properties seen :{}
Probabilistic random walk after 22684 steps, saw 20178 distinct states, run finished after 3002 ms. (steps per millisecond=7 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-16 03:08:28] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:08:28] [INFO ] Invariant cache hit.
[2023-03-16 03:08:28] [INFO ] [Real]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 03:08:44] [INFO ] After 16745ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-16 03:08:44] [INFO ] [Nat]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 03:09:03] [INFO ] After 18614ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-16 03:09:03] [INFO ] State equation strengthened by 268 read => feed constraints.
[2023-03-16 03:09:09] [INFO ] After 6236ms SMT Verify possible using 268 Read/Feed constraints in natural domain returned unsat :0 sat :0
[2023-03-16 03:09:09] [INFO ] After 25033ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 6 ms.
Support contains 2 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 159 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 160 ms. Remains : 626/626 places, 31352/31352 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 322 ms. (steps per millisecond=31 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=333 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 22556 steps, run timeout after 3002 ms. (steps per millisecond=7 ) properties seen :{}
Probabilistic random walk after 22556 steps, saw 20062 distinct states, run finished after 3002 ms. (steps per millisecond=7 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-16 03:09:13] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:09:13] [INFO ] Invariant cache hit.
[2023-03-16 03:09:13] [INFO ] [Real]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 03:09:29] [INFO ] After 16141ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-16 03:09:29] [INFO ] [Nat]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 03:09:48] [INFO ] After 18855ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-16 03:09:48] [INFO ] State equation strengthened by 268 read => feed constraints.
[2023-03-16 03:09:54] [INFO ] After 5997ms SMT Verify possible using 268 Read/Feed constraints in natural domain returned unsat :0 sat :0
[2023-03-16 03:09:54] [INFO ] After 25038ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 12 ms.
Support contains 2 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 181 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 181 ms. Remains : 626/626 places, 31352/31352 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 179 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 03:09:54] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:09:55] [INFO ] Invariant cache hit.
[2023-03-16 03:09:56] [INFO ] Implicit Places using invariants in 1980 ms returned []
Implicit Place search using SMT only with invariants took 1981 ms to find 0 implicit places.
[2023-03-16 03:09:56] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:09:56] [INFO ] Invariant cache hit.
[2023-03-16 03:10:05] [INFO ] Dead Transitions using invariants and state equation in 8591 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 10757 ms. Remains : 626/626 places, 31352/31352 transitions.
Knowledge obtained : [(NOT p0), (X (NOT p0)), (X (X (NOT p0)))]
False Knowledge obtained : []
Knowledge based reduction with 3 factoid took 123 ms. Reduced automaton from 1 states, 1 edges and 1 AP (stutter insensitive) to 1 states, 1 edges and 1 AP (stutter insensitive).
Stuttering acceptance computed with spot in 44 ms :[(NOT p0)]
Stuttering acceptance computed with spot in 42 ms :[(NOT p0)]
[2023-03-16 03:10:05] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:10:05] [INFO ] Invariant cache hit.
Could not prove EG (NOT p0)
Support contains 2 out of 626 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 165 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 03:10:21] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:10:21] [INFO ] Invariant cache hit.
[2023-03-16 03:10:23] [INFO ] Implicit Places using invariants in 1902 ms returned []
Implicit Place search using SMT only with invariants took 1903 ms to find 0 implicit places.
[2023-03-16 03:10:23] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:10:23] [INFO ] Invariant cache hit.
[2023-03-16 03:10:31] [INFO ] Dead Transitions using invariants and state equation in 8539 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 10609 ms. Remains : 626/626 places, 31352/31352 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Knowledge obtained : [(NOT p0), (X (NOT p0)), (X (X (NOT p0)))]
False Knowledge obtained : []
Knowledge based reduction with 3 factoid took 128 ms. Reduced automaton from 1 states, 1 edges and 1 AP (stutter insensitive) to 1 states, 1 edges and 1 AP (stutter insensitive).
Stuttering acceptance computed with spot in 32 ms :[(NOT p0)]
Incomplete random walk after 10000 steps, including 2 resets, run finished after 327 ms. (steps per millisecond=30 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=344 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 22429 steps, run timeout after 3001 ms. (steps per millisecond=7 ) properties seen :{}
Probabilistic random walk after 22429 steps, saw 19948 distinct states, run finished after 3001 ms. (steps per millisecond=7 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-16 03:10:35] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:10:35] [INFO ] Invariant cache hit.
[2023-03-16 03:10:35] [INFO ] [Real]Absence check using 13 positive place invariants in 7 ms returned sat
[2023-03-16 03:10:51] [INFO ] After 16527ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-16 03:10:51] [INFO ] [Nat]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 03:11:10] [INFO ] After 18343ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-16 03:11:10] [INFO ] State equation strengthened by 268 read => feed constraints.
[2023-03-16 03:11:16] [INFO ] After 6504ms SMT Verify possible using 268 Read/Feed constraints in natural domain returned unsat :0 sat :0
[2023-03-16 03:11:16] [INFO ] After 25038ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 5 ms.
Support contains 2 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 161 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 162 ms. Remains : 626/626 places, 31352/31352 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 326 ms. (steps per millisecond=30 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=344 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 21913 steps, run timeout after 3001 ms. (steps per millisecond=7 ) properties seen :{}
Probabilistic random walk after 21913 steps, saw 19487 distinct states, run finished after 3002 ms. (steps per millisecond=7 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-16 03:11:20] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:11:20] [INFO ] Invariant cache hit.
[2023-03-16 03:11:20] [INFO ] [Real]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 03:11:36] [INFO ] After 16186ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-16 03:11:36] [INFO ] [Nat]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 03:11:55] [INFO ] After 18278ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-16 03:11:55] [INFO ] State equation strengthened by 268 read => feed constraints.
[2023-03-16 03:12:01] [INFO ] After 6567ms SMT Verify possible using 268 Read/Feed constraints in natural domain returned unsat :0 sat :0
[2023-03-16 03:12:01] [INFO ] After 25037ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 10 ms.
Support contains 2 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 182 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 183 ms. Remains : 626/626 places, 31352/31352 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 180 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 03:12:02] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:12:02] [INFO ] Invariant cache hit.
[2023-03-16 03:12:04] [INFO ] Implicit Places using invariants in 1962 ms returned []
Implicit Place search using SMT only with invariants took 1963 ms to find 0 implicit places.
[2023-03-16 03:12:04] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:12:04] [INFO ] Invariant cache hit.
[2023-03-16 03:12:12] [INFO ] Dead Transitions using invariants and state equation in 8833 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 10980 ms. Remains : 626/626 places, 31352/31352 transitions.
Knowledge obtained : [(NOT p0), (X (NOT p0)), (X (X (NOT p0)))]
False Knowledge obtained : []
Knowledge based reduction with 3 factoid took 137 ms. Reduced automaton from 1 states, 1 edges and 1 AP (stutter insensitive) to 1 states, 1 edges and 1 AP (stutter insensitive).
Stuttering acceptance computed with spot in 35 ms :[(NOT p0)]
Stuttering acceptance computed with spot in 40 ms :[(NOT p0)]
[2023-03-16 03:12:13] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:12:13] [INFO ] Invariant cache hit.
Could not prove EG (NOT p0)
Stuttering acceptance computed with spot in 37 ms :[(NOT p0)]
Product exploration explored 100000 steps with 0 reset in 3100 ms.
Product exploration explored 100000 steps with 0 reset in 3193 ms.
Support contains 2 out of 626 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 164 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 03:12:34] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:12:34] [INFO ] Invariant cache hit.
[2023-03-16 03:12:36] [INFO ] Implicit Places using invariants in 2039 ms returned []
Implicit Place search using SMT only with invariants took 2040 ms to find 0 implicit places.
[2023-03-16 03:12:36] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:12:36] [INFO ] Invariant cache hit.
[2023-03-16 03:12:45] [INFO ] Dead Transitions using invariants and state equation in 8590 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 10795 ms. Remains : 626/626 places, 31352/31352 transitions.
Treatment of property RERS17pb113-PT-3-LTLFireability-15 finished in 279330 ms.
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!(F((G(p0)||G((F((!p1||X(!p2))) U p3)))))'
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!(F((!(!p0 U (p1 U G(!X(p2))))&&!p0)))'
Found a Shortening insensitive property : RERS17pb113-PT-3-LTLFireability-02
Stuttering acceptance computed with spot in 149 ms :[(OR (NOT p2) p0), (NOT p2), false, false]
Support contains 6 out of 627 places. Attempting structural reductions.
Starting structural reductions in LI_LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 179 ms. Remains 626 /627 variables (removed 1) and now considering 31352/31353 (removed 1) transitions.
[2023-03-16 03:12:46] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:12:46] [INFO ] Invariant cache hit.
[2023-03-16 03:12:48] [INFO ] Implicit Places using invariants in 1940 ms returned []
Implicit Place search using SMT only with invariants took 1940 ms to find 0 implicit places.
[2023-03-16 03:12:48] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:12:48] [INFO ] Invariant cache hit.
[2023-03-16 03:12:57] [INFO ] Dead Transitions using invariants and state equation in 8532 ms found 0 transitions.
Finished structural reductions in LI_LTL mode , in 1 iterations and 10652 ms. Remains : 626/627 places, 31352/31353 transitions.
Running random walk in product with property : RERS17pb113-PT-3-LTLFireability-02 automaton TGBA Formula[mat=[[{ cond=p0, acceptance={0} source=0 dest: 0}, { cond=(NOT p0), acceptance={} source=0 dest: 1}, { cond=(NOT p0), acceptance={} source=0 dest: 2}], [{ cond=(NOT p2), acceptance={0} source=1 dest: 1}], [{ cond=p2, acceptance={} source=2 dest: 1}, { cond=(NOT p0), acceptance={} source=2 dest: 2}, { cond=(AND p0 p1), acceptance={} source=2 dest: 3}], [{ cond=p2, acceptance={} source=3 dest: 1}, { cond=p1, acceptance={} source=3 dest: 3}]], initial=0, aps=[p0:(AND (GEQ s64 1) (GEQ s121 1)), p2:(AND (GEQ s0 1) (GEQ s430 1)), p1:(AND (GEQ s109 1) (GEQ s479 1))], nbAcceptance=1, properties=[trans-labels, explicit-labels, trans-acc, no-univ-branch, stutter-sensitive, cl-invariant], stateDesc=[null, null, null, null][false, false, false, false]]
Product exploration explored 100000 steps with 0 reset in 3152 ms.
Product exploration explored 100000 steps with 0 reset in 3218 ms.
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Knowledge obtained : [(AND (NOT p0) (NOT p2) (NOT p1)), (X (NOT p2)), (X (NOT (AND p0 p1))), (X (NOT p0)), (X (X (NOT p2))), (X (X (NOT (AND p0 p1)))), (X (X (NOT p0))), (X (X (NOT p1)))]
False Knowledge obtained : []
Knowledge based reduction with 8 factoid took 340 ms. Reduced automaton from 4 states, 9 edges and 3 AP (stutter sensitive) to 4 states, 8 edges and 3 AP (stutter sensitive).
Stuttering acceptance computed with spot in 151 ms :[(NOT p2), (NOT p2), false, false]
Incomplete random walk after 10000 steps, including 2 resets, run finished after 395 ms. (steps per millisecond=25 ) properties (out of 4) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=312 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=312 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=322 ) properties (out of 3) seen :0
Running SMT prover for 3 properties.
[2023-03-16 03:13:04] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:13:05] [INFO ] Invariant cache hit.
[2023-03-16 03:13:05] [INFO ] [Real]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 03:13:29] [INFO ] After 24296ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:3
[2023-03-16 03:13:29] [INFO ] [Nat]Absence check using 13 positive place invariants in 7 ms returned sat
[2023-03-16 03:13:53] [INFO ] After 24182ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :3
[2023-03-16 03:13:53] [INFO ] State equation strengthened by 268 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Broken pipe ...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.checkResults(DeadlockTester.java:797)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:644)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.addInvarianceKnowledge(LTLPropertySolver.java:701)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.applyKnowledgeBasedReductions(LTLPropertySolver.java:568)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.checkLTLProperty(LTLPropertySolver.java:251)
at fr.lip6.move.gal.application.solver.ltl.LTLLengthAwareSolver.runSLCLLTLTest(LTLLengthAwareSolver.java:100)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:764)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 03:13:54] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 03:13:54] [INFO ] After 25032ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:3
Parikh walk visited 0 properties in 18 ms.
Support contains 6 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 181 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 182 ms. Remains : 626/626 places, 31352/31352 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 394 ms. (steps per millisecond=25 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 41 ms. (steps per millisecond=243 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 41 ms. (steps per millisecond=243 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 39 ms. (steps per millisecond=256 ) properties (out of 3) seen :0
Interrupted probabilistic random walk after 20841 steps, run timeout after 3001 ms. (steps per millisecond=6 ) properties seen :{}
Probabilistic random walk after 20841 steps, saw 18544 distinct states, run finished after 3001 ms. (steps per millisecond=6 ) properties seen :0
Running SMT prover for 3 properties.
[2023-03-16 03:13:58] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:13:58] [INFO ] Invariant cache hit.
[2023-03-16 03:13:58] [INFO ] [Real]Absence check using 13 positive place invariants in 7 ms returned sat
[2023-03-16 03:14:23] [INFO ] After 25031ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-16 03:14:23] [INFO ] [Nat]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 03:14:48] [INFO ] After 24823ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :3
[2023-03-16 03:14:48] [INFO ] State equation strengthened by 268 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.addInvarianceKnowledge(LTLPropertySolver.java:701)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.applyKnowledgeBasedReductions(LTLPropertySolver.java:568)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.checkLTLProperty(LTLPropertySolver.java:251)
at fr.lip6.move.gal.application.solver.ltl.LTLLengthAwareSolver.runSLCLLTLTest(LTLLengthAwareSolver.java:100)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:764)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 03:14:48] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 03:14:48] [INFO ] After 25050ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:2
Parikh walk visited 0 properties in 13 ms.
Support contains 6 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 161 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 162 ms. Remains : 626/626 places, 31352/31352 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 162 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 03:14:48] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:14:48] [INFO ] Invariant cache hit.
[2023-03-16 03:14:50] [INFO ] Implicit Places using invariants in 2008 ms returned []
Implicit Place search using SMT only with invariants took 2009 ms to find 0 implicit places.
[2023-03-16 03:14:50] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:14:50] [INFO ] Invariant cache hit.
[2023-03-16 03:14:59] [INFO ] Dead Transitions using invariants and state equation in 8877 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 11050 ms. Remains : 626/626 places, 31352/31352 transitions.
Knowledge obtained : [(AND (NOT p0) (NOT p2) (NOT p1)), (X (NOT p2)), (X (NOT (AND p0 p1))), (X (NOT p0)), (X (X (NOT p2))), (X (X (NOT (AND p0 p1)))), (X (X (NOT p0))), (X (X (NOT p1)))]
False Knowledge obtained : [(F p1)]
Knowledge based reduction with 8 factoid took 406 ms. Reduced automaton from 4 states, 8 edges and 3 AP (stutter sensitive) to 4 states, 8 edges and 3 AP (stutter sensitive).
Stuttering acceptance computed with spot in 166 ms :[(NOT p2), (NOT p2), false, false]
Stuttering acceptance computed with spot in 156 ms :[(NOT p2), (NOT p2), false, false]
[2023-03-16 03:15:00] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:15:00] [INFO ] Invariant cache hit.
Could not prove EG (NOT p2)
Support contains 6 out of 626 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 75 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 03:15:15] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:15:15] [INFO ] Invariant cache hit.
[2023-03-16 03:15:17] [INFO ] Implicit Places using invariants in 2014 ms returned []
Implicit Place search using SMT only with invariants took 2019 ms to find 0 implicit places.
[2023-03-16 03:15:17] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:15:17] [INFO ] Invariant cache hit.
[2023-03-16 03:15:26] [INFO ] Dead Transitions using invariants and state equation in 9067 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11163 ms. Remains : 626/626 places, 31352/31352 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Knowledge obtained : [(AND (NOT p2) (NOT p0) (NOT p1)), (X (NOT p2)), (X (NOT p0)), (X (NOT (AND p0 p1))), (X (X (NOT p2))), (X (X (NOT p0))), (X (X (NOT (AND p0 p1)))), (X (X (NOT p1)))]
False Knowledge obtained : []
Knowledge based reduction with 8 factoid took 341 ms. Reduced automaton from 4 states, 8 edges and 3 AP (stutter sensitive) to 4 states, 8 edges and 3 AP (stutter sensitive).
Stuttering acceptance computed with spot in 153 ms :[(NOT p2), (NOT p2), false, false]
Incomplete random walk after 10000 steps, including 2 resets, run finished after 567 ms. (steps per millisecond=17 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 46 ms. (steps per millisecond=217 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 45 ms. (steps per millisecond=222 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 48 ms. (steps per millisecond=208 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 47 ms. (steps per millisecond=212 ) properties (out of 4) seen :0
Interrupted probabilistic random walk after 21098 steps, run timeout after 3002 ms. (steps per millisecond=7 ) properties seen :{}
Probabilistic random walk after 21098 steps, saw 18774 distinct states, run finished after 3002 ms. (steps per millisecond=7 ) properties seen :0
Running SMT prover for 4 properties.
[2023-03-16 03:15:31] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:15:31] [INFO ] Invariant cache hit.
[2023-03-16 03:15:31] [INFO ] [Real]Absence check using 13 positive place invariants in 7 ms returned sat
[2023-03-16 03:15:56] [INFO ] After 24884ms SMT Verify possible using state equation in real domain returned unsat :0 sat :2 real:2
[2023-03-16 03:15:56] [INFO ] State equation strengthened by 268 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.addInvarianceKnowledge(LTLPropertySolver.java:701)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.applyKnowledgeBasedReductions(LTLPropertySolver.java:568)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.checkLTLProperty(LTLPropertySolver.java:261)
at fr.lip6.move.gal.application.solver.ltl.LTLLengthAwareSolver.runSLCLLTLTest(LTLLengthAwareSolver.java:100)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:764)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 03:15:56] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 03:15:56] [INFO ] After 25141ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Fused 4 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 6 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 161 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 162 ms. Remains : 626/626 places, 31352/31352 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 569 ms. (steps per millisecond=17 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 48 ms. (steps per millisecond=208 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 47 ms. (steps per millisecond=212 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 48 ms. (steps per millisecond=208 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 46 ms. (steps per millisecond=217 ) properties (out of 4) seen :0
Interrupted probabilistic random walk after 20761 steps, run timeout after 3001 ms. (steps per millisecond=6 ) properties seen :{}
Probabilistic random walk after 20761 steps, saw 18474 distinct states, run finished after 3001 ms. (steps per millisecond=6 ) properties seen :0
Running SMT prover for 4 properties.
[2023-03-16 03:16:00] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:16:00] [INFO ] Invariant cache hit.
[2023-03-16 03:16:00] [INFO ] [Real]Absence check using 13 positive place invariants in 7 ms returned sat
[2023-03-16 03:16:25] [INFO ] After 25037ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:3
[2023-03-16 03:16:25] [INFO ] [Nat]Absence check using 13 positive place invariants in 7 ms returned sat
[2023-03-16 03:16:50] [INFO ] After 24827ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :4
[2023-03-16 03:16:50] [INFO ] State equation strengthened by 268 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.addInvarianceKnowledge(LTLPropertySolver.java:701)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.applyKnowledgeBasedReductions(LTLPropertySolver.java:568)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.checkLTLProperty(LTLPropertySolver.java:261)
at fr.lip6.move.gal.application.solver.ltl.LTLLengthAwareSolver.runSLCLLTLTest(LTLLengthAwareSolver.java:100)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:764)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 03:16:50] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 03:16:50] [INFO ] After 25069ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:3
Parikh walk visited 0 properties in 17 ms.
Support contains 6 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 160 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 160 ms. Remains : 626/626 places, 31352/31352 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 159 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 03:16:50] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:16:50] [INFO ] Invariant cache hit.
[2023-03-16 03:16:52] [INFO ] Implicit Places using invariants in 2015 ms returned []
Implicit Place search using SMT only with invariants took 2015 ms to find 0 implicit places.
[2023-03-16 03:16:52] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:16:52] [INFO ] Invariant cache hit.
[2023-03-16 03:17:01] [INFO ] Dead Transitions using invariants and state equation in 8592 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 10770 ms. Remains : 626/626 places, 31352/31352 transitions.
Ensure Unique test removed 13027 transitions
Reduce isomorphic transitions removed 13027 transitions.
Iterating post reduction 0 with 13027 rules applied. Total rules applied 13027 place count 626 transition count 18325
Applied a total of 13027 rules in 561 ms. Remains 626 /626 variables (removed 0) and now considering 18325/31352 (removed 13027) transitions.
Running SMT prover for 4 properties.
// Phase 1: matrix 18325 rows 626 cols
[2023-03-16 03:17:02] [INFO ] Computed 13 place invariants in 53 ms
[2023-03-16 03:17:02] [INFO ] [Real]Absence check using 13 positive place invariants in 7 ms returned sat
[2023-03-16 03:17:28] [INFO ] After 26695ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:4
[2023-03-16 03:17:28] [INFO ] [Nat]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 03:17:53] [INFO ] After 24914ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :4
[2023-03-16 03:17:56] [INFO ] After 27924ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :4
Attempting to minimize the solution found.
Minimization took 1984 ms.
[2023-03-16 03:17:58] [INFO ] After 30053ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :4
Knowledge obtained : [(AND (NOT p2) (NOT p0) (NOT p1)), (X (NOT p2)), (X (NOT p0)), (X (NOT (AND p0 p1))), (X (X (NOT p2))), (X (X (NOT p0))), (X (X (NOT (AND p0 p1)))), (X (X (NOT p1)))]
False Knowledge obtained : []
Knowledge based reduction with 8 factoid took 392 ms. Reduced automaton from 4 states, 8 edges and 3 AP (stutter sensitive) to 4 states, 8 edges and 3 AP (stutter sensitive).
Stuttering acceptance computed with spot in 142 ms :[(NOT p2), (NOT p2), false, false]
Stuttering acceptance computed with spot in 136 ms :[(NOT p2), (NOT p2), false, false]
[2023-03-16 03:17:59] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
// Phase 1: matrix 18325 rows 626 cols
[2023-03-16 03:17:59] [INFO ] Computed 13 place invariants in 54 ms
Could not prove EG (NOT p2)
Stuttering acceptance computed with spot in 152 ms :[(NOT p2), (NOT p2), false, false]
Product exploration explored 100000 steps with 0 reset in 3152 ms.
Product exploration explored 100000 steps with 0 reset in 3203 ms.
Applying partial POR strategy [false, true, false, false]
Stuttering acceptance computed with spot in 170 ms :[(NOT p2), (NOT p2), false, false]
Support contains 6 out of 626 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 156 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 03:18:21] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:18:21] [INFO ] Invariant cache hit.
[2023-03-16 03:18:30] [INFO ] Dead Transitions using invariants and state equation in 8563 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 8722 ms. Remains : 626/626 places, 31352/31352 transitions.
Support contains 6 out of 626 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 71 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 03:18:30] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:18:30] [INFO ] Invariant cache hit.
[2023-03-16 03:18:32] [INFO ] Implicit Places using invariants in 1788 ms returned []
Implicit Place search using SMT only with invariants took 1789 ms to find 0 implicit places.
[2023-03-16 03:18:32] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:18:32] [INFO ] Invariant cache hit.
[2023-03-16 03:18:40] [INFO ] Dead Transitions using invariants and state equation in 8390 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10264 ms. Remains : 626/626 places, 31352/31352 transitions.
Treatment of property RERS17pb113-PT-3-LTLFireability-02 finished in 355149 ms.
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!(X(G((X(X(G(p1)))||p0))))'
Found a Lengthening insensitive property : RERS17pb113-PT-3-LTLFireability-05
Stuttering acceptance computed with spot in 148 ms :[true, (NOT p1), (AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0)), (NOT p1)]
Support contains 4 out of 627 places. Attempting structural reductions.
Starting structural reductions in LI_LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 169 ms. Remains 626 /627 variables (removed 1) and now considering 31352/31353 (removed 1) transitions.
[2023-03-16 03:18:42] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:18:42] [INFO ] Invariant cache hit.
[2023-03-16 03:18:43] [INFO ] Implicit Places using invariants in 1911 ms returned []
Implicit Place search using SMT only with invariants took 1912 ms to find 0 implicit places.
[2023-03-16 03:18:43] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:18:43] [INFO ] Invariant cache hit.
[2023-03-16 03:18:52] [INFO ] Dead Transitions using invariants and state equation in 8811 ms found 0 transitions.
Finished structural reductions in LI_LTL mode , in 1 iterations and 10895 ms. Remains : 626/627 places, 31352/31353 transitions.
Running random walk in product with property : RERS17pb113-PT-3-LTLFireability-05 automaton TGBA Formula[mat=[[{ cond=true, acceptance={0} source=0 dest: 0}], [{ cond=true, acceptance={} source=1 dest: 4}], [{ cond=true, acceptance={} source=2 dest: 3}], [{ cond=(NOT p0), acceptance={} source=3 dest: 1}, { cond=p0, acceptance={} source=3 dest: 3}], [{ cond=(NOT p1), acceptance={} source=4 dest: 0}, { cond=p1, acceptance={} source=4 dest: 4}]], initial=2, aps=[p0:(OR (LT s471 1) (LT s605 1)), p1:(OR (LT s76 1) (LT s277 1))], nbAcceptance=1, properties=[trans-labels, explicit-labels, trans-acc, complete, deterministic, no-univ-branch, unambiguous, semi-deterministic, stutter-sensitive, terminal, very-weak, weak, inherently-weak, sl-invariant], stateDesc=[null, null, null, null, null][false, false, false, false, false]]
Product exploration explored 100000 steps with 0 reset in 3084 ms.
Product exploration explored 100000 steps with 0 reset in 3297 ms.
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Knowledge obtained : [(AND p0 p1), (X p0), true, (X (X p0))]
False Knowledge obtained : []
Knowledge based reduction with 4 factoid took 172 ms. Reduced automaton from 5 states, 7 edges and 2 AP (stutter sensitive) to 5 states, 7 edges and 2 AP (stutter sensitive).
Stuttering acceptance computed with spot in 165 ms :[true, (NOT p1), (NOT p1), (AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0))]
Incomplete random walk after 10000 steps, including 2 resets, run finished after 374 ms. (steps per millisecond=26 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=344 ) properties (out of 2) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=370 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-16 03:19:00] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:19:00] [INFO ] Invariant cache hit.
[2023-03-16 03:19:00] [INFO ] [Real]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 03:19:20] [INFO ] After 20343ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-16 03:19:20] [INFO ] State equation strengthened by 268 read => feed constraints.
[2023-03-16 03:19:25] [INFO ] After 4507ms SMT Verify possible using 268 Read/Feed constraints in real domain returned unsat :0 sat :0
[2023-03-16 03:19:25] [INFO ] After 25037ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 5 ms.
Support contains 2 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 153 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 154 ms. Remains : 626/626 places, 31352/31352 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 307 ms. (steps per millisecond=32 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=370 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 22868 steps, run timeout after 3001 ms. (steps per millisecond=7 ) properties seen :{}
Probabilistic random walk after 22868 steps, saw 20330 distinct states, run finished after 3001 ms. (steps per millisecond=7 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-16 03:19:28] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:19:28] [INFO ] Invariant cache hit.
[2023-03-16 03:19:28] [INFO ] [Real]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 03:19:48] [INFO ] After 19883ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-16 03:19:48] [INFO ] State equation strengthened by 268 read => feed constraints.
[2023-03-16 03:19:53] [INFO ] After 4957ms SMT Verify possible using 268 Read/Feed constraints in real domain returned unsat :0 sat :0
[2023-03-16 03:19:53] [INFO ] After 25037ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 10 ms.
Support contains 2 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 155 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 155 ms. Remains : 626/626 places, 31352/31352 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 156 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 03:19:54] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:19:54] [INFO ] Invariant cache hit.
[2023-03-16 03:19:55] [INFO ] Implicit Places using invariants in 1869 ms returned []
Implicit Place search using SMT only with invariants took 1870 ms to find 0 implicit places.
[2023-03-16 03:19:55] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:19:55] [INFO ] Invariant cache hit.
[2023-03-16 03:20:04] [INFO ] Dead Transitions using invariants and state equation in 8413 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 10445 ms. Remains : 626/626 places, 31352/31352 transitions.
Ensure Unique test removed 13027 transitions
Reduce isomorphic transitions removed 13027 transitions.
Iterating post reduction 0 with 13027 rules applied. Total rules applied 13027 place count 626 transition count 18325
Applied a total of 13027 rules in 603 ms. Remains 626 /626 variables (removed 0) and now considering 18325/31352 (removed 13027) transitions.
Running SMT prover for 1 properties.
// Phase 1: matrix 18325 rows 626 cols
[2023-03-16 03:20:05] [INFO ] Computed 13 place invariants in 50 ms
[2023-03-16 03:20:05] [INFO ] [Real]Absence check using 13 positive place invariants in 5 ms returned sat
[2023-03-16 03:20:20] [INFO ] After 15593ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-16 03:20:20] [INFO ] [Nat]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 03:20:36] [INFO ] After 15657ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-16 03:20:37] [INFO ] After 16532ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 605 ms.
[2023-03-16 03:20:37] [INFO ] After 17230ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Knowledge obtained : [(AND p0 p1), (X p0), true, (X (X p0))]
False Knowledge obtained : [(F (NOT p1))]
Knowledge based reduction with 4 factoid took 184 ms. Reduced automaton from 5 states, 7 edges and 2 AP (stutter sensitive) to 5 states, 7 edges and 2 AP (stutter sensitive).
Stuttering acceptance computed with spot in 177 ms :[true, (NOT p1), (NOT p1), (AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0))]
Stuttering acceptance computed with spot in 152 ms :[true, (NOT p1), (NOT p1), (AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0))]
Support contains 4 out of 626 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 74 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 03:20:38] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
// Phase 1: matrix 18325 rows 626 cols
[2023-03-16 03:20:38] [INFO ] Computed 13 place invariants in 50 ms
[2023-03-16 03:20:40] [INFO ] Implicit Places using invariants in 1947 ms returned []
Implicit Place search using SMT only with invariants took 1948 ms to find 0 implicit places.
[2023-03-16 03:20:40] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:20:40] [INFO ] Invariant cache hit.
[2023-03-16 03:20:49] [INFO ] Dead Transitions using invariants and state equation in 8482 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10505 ms. Remains : 626/626 places, 31352/31352 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Computed a total of 0 stabilizing places and 0 stable transitions
Knowledge obtained : [(AND p1 p0), (X p0), true, (X (X p0))]
False Knowledge obtained : []
Knowledge based reduction with 4 factoid took 181 ms. Reduced automaton from 5 states, 7 edges and 2 AP (stutter sensitive) to 5 states, 7 edges and 2 AP (stutter sensitive).
Stuttering acceptance computed with spot in 175 ms :[true, (NOT p1), (NOT p1), (AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0))]
Incomplete random walk after 10000 steps, including 2 resets, run finished after 371 ms. (steps per millisecond=26 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=333 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=312 ) properties (out of 2) seen :0
Interrupted probabilistic random walk after 22122 steps, run timeout after 3001 ms. (steps per millisecond=7 ) properties seen :{}
Probabilistic random walk after 22122 steps, saw 19671 distinct states, run finished after 3001 ms. (steps per millisecond=7 ) properties seen :0
Running SMT prover for 2 properties.
[2023-03-16 03:20:53] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:20:53] [INFO ] Invariant cache hit.
[2023-03-16 03:20:53] [INFO ] [Real]Absence check using 13 positive place invariants in 8 ms returned sat
[2023-03-16 03:21:07] [INFO ] After 14088ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-16 03:21:07] [INFO ] [Nat]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 03:21:21] [INFO ] After 13981ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-16 03:21:21] [INFO ] State equation strengthened by 268 read => feed constraints.
[2023-03-16 03:21:27] [INFO ] After 6558ms SMT Verify possible using 268 Read/Feed constraints in natural domain returned unsat :0 sat :2
[2023-03-16 03:21:30] [INFO ] Deduced a trap composed of 40 places in 750 ms of which 1 ms to minimize.
[2023-03-16 03:21:31] [INFO ] Deduced a trap composed of 40 places in 637 ms of which 1 ms to minimize.
[2023-03-16 03:21:31] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 2556 ms
[2023-03-16 03:21:34] [INFO ] Deduced a trap composed of 64 places in 2656 ms of which 1 ms to minimize.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.refineWithTraps(DeadlockTester.java:1255)
at fr.lip6.move.gal.structural.smt.DeadlockTester.refineResultsWithTraps(DeadlockTester.java:736)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:656)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.addInvarianceKnowledge(LTLPropertySolver.java:701)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.applyKnowledgeBasedReductions(LTLPropertySolver.java:568)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.checkLTLProperty(LTLPropertySolver.java:261)
at fr.lip6.move.gal.application.solver.ltl.LTLLengthAwareSolver.runSLCLLTLTest(LTLLengthAwareSolver.java:100)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:764)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 03:21:34] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 03:21:34] [INFO ] After 27694ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:2
Parikh walk visited 0 properties in 7 ms.
Support contains 4 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 173 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 175 ms. Remains : 626/626 places, 31352/31352 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 410 ms. (steps per millisecond=24 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 2) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-16 03:21:35] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:21:35] [INFO ] Invariant cache hit.
[2023-03-16 03:21:35] [INFO ] [Real]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 03:21:55] [INFO ] After 20179ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-16 03:21:55] [INFO ] State equation strengthened by 268 read => feed constraints.
[2023-03-16 03:22:00] [INFO ] After 4667ms SMT Verify possible using 268 Read/Feed constraints in real domain returned unsat :0 sat :0
[2023-03-16 03:22:00] [INFO ] After 25038ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 6 ms.
Support contains 2 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 157 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 158 ms. Remains : 626/626 places, 31352/31352 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 310 ms. (steps per millisecond=32 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=370 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 22659 steps, run timeout after 3002 ms. (steps per millisecond=7 ) properties seen :{}
Probabilistic random walk after 22659 steps, saw 20156 distinct states, run finished after 3002 ms. (steps per millisecond=7 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-16 03:22:04] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:22:04] [INFO ] Invariant cache hit.
[2023-03-16 03:22:04] [INFO ] [Real]Absence check using 13 positive place invariants in 5 ms returned sat
[2023-03-16 03:22:24] [INFO ] After 20512ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-16 03:22:24] [INFO ] State equation strengthened by 268 read => feed constraints.
[2023-03-16 03:22:29] [INFO ] After 4335ms SMT Verify possible using 268 Read/Feed constraints in real domain returned unsat :0 sat :0
[2023-03-16 03:22:29] [INFO ] After 25030ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 5 ms.
Support contains 2 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 179 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 180 ms. Remains : 626/626 places, 31352/31352 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 175 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 03:22:29] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:22:29] [INFO ] Invariant cache hit.
[2023-03-16 03:22:31] [INFO ] Implicit Places using invariants in 1841 ms returned []
Implicit Place search using SMT only with invariants took 1842 ms to find 0 implicit places.
[2023-03-16 03:22:31] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:22:31] [INFO ] Invariant cache hit.
[2023-03-16 03:22:39] [INFO ] Dead Transitions using invariants and state equation in 8340 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 10362 ms. Remains : 626/626 places, 31352/31352 transitions.
Knowledge obtained : [(AND p1 p0), (X p0), true, (X (X p0))]
False Knowledge obtained : [(F (NOT p1))]
Knowledge based reduction with 4 factoid took 196 ms. Reduced automaton from 5 states, 7 edges and 2 AP (stutter sensitive) to 5 states, 7 edges and 2 AP (stutter sensitive).
Stuttering acceptance computed with spot in 159 ms :[true, (NOT p1), (NOT p1), (AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0))]
Stuttering acceptance computed with spot in 160 ms :[true, (NOT p1), (NOT p1), (AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0))]
Stuttering acceptance computed with spot in 168 ms :[true, (NOT p1), (NOT p1), (AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0))]
Product exploration explored 100000 steps with 0 reset in 3007 ms.
Product exploration explored 100000 steps with 0 reset in 3047 ms.
Applying partial POR strategy [true, true, false, false, false]
Stuttering acceptance computed with spot in 158 ms :[true, (NOT p1), (NOT p1), (AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0))]
Support contains 4 out of 626 places. Attempting structural reductions.
Starting structural reductions in SI_LTL mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 152 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 03:22:46] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:22:46] [INFO ] Invariant cache hit.
[2023-03-16 03:22:55] [INFO ] Dead Transitions using invariants and state equation in 8365 ms found 0 transitions.
Finished structural reductions in SI_LTL mode , in 1 iterations and 8518 ms. Remains : 626/626 places, 31352/31352 transitions.
Support contains 4 out of 626 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 71 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
[2023-03-16 03:22:55] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:22:55] [INFO ] Invariant cache hit.
[2023-03-16 03:22:57] [INFO ] Implicit Places using invariants in 1840 ms returned []
Implicit Place search using SMT only with invariants took 1841 ms to find 0 implicit places.
[2023-03-16 03:22:57] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
[2023-03-16 03:22:57] [INFO ] Invariant cache hit.
[2023-03-16 03:23:05] [INFO ] Dead Transitions using invariants and state equation in 8321 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10234 ms. Remains : 626/626 places, 31352/31352 transitions.
Treatment of property RERS17pb113-PT-3-LTLFireability-05 finished in 264885 ms.
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!((p0 U (G(F(p0)) U ((p2 U p3)&&p1))))'
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!((F((!p0||X(F(!p1)))) U G(p1)))'
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins/fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!(F(p0))'
[2023-03-16 03:23:07] [INFO ] Flatten gal took : 634 ms
[2023-03-16 03:23:07] [INFO ] Export to MCC of 6 properties in file /home/mcc/execution/LTLFireability.sr.xml took 1 ms.
[2023-03-16 03:23:07] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 627 places, 31353 transitions and 125406 arcs took 93 ms.
Total runtime 2719059 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT RERS17pb113-PT-3
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/371
LTLFireability

FORMULA RERS17pb113-PT-3-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RERS17pb113-PT-3-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RERS17pb113-PT-3-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RERS17pb113-PT-3-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RERS17pb113-PT-3-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678937719419

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination LTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/371/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/371/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/371/LTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:430
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-00: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 11 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-00: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 16 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 6
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 21 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 26 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 6
lola: Created skeleton in 13.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 31 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 36 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 41 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 6
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 46 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 51 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 6
lola: Created skeleton in 12.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 56 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 61 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 66 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 6
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 71 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 76 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 6
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 81 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 86 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 91 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 96 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 101 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 106 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 111 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 116 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 121 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 126 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 131 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 136 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 141 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 146 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 6
lola: LAUNCH task # 1 (type EXCL) for 0 RERS17pb113-PT-3-LTLFireability-00
lola: time limit : 575 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for RERS17pb113-PT-3-LTLFireability-00
lola: result : false
lola: markings : 3492
lola: fired transitions : 3492
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 RERS17pb113-PT-3-LTLFireability-02
lola: time limit : 689 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 LTL EXCL 0/689 1/32 RERS17pb113-PT-3-LTLFireability-02 3246 m, 649 m/sec, 3245 t fired, .

Time elapsed: 151 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
lola: FINISHED task # 4 (type EXCL) for RERS17pb113-PT-3-LTLFireability-02
lola: result : false
lola: markings : 3492
lola: fired transitions : 3492
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 RERS17pb113-PT-3-LTLFireability-06
lola: time limit : 862 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 5/862 1/32 RERS17pb113-PT-3-LTLFireability-06 339 m, 67 m/sec, 338 t fired, .

Time elapsed: 156 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 10/862 1/32 RERS17pb113-PT-3-LTLFireability-06 733 m, 78 m/sec, 732 t fired, .

Time elapsed: 161 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 15/862 1/32 RERS17pb113-PT-3-LTLFireability-06 1138 m, 81 m/sec, 1137 t fired, .

Time elapsed: 166 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 20/862 1/32 RERS17pb113-PT-3-LTLFireability-06 1561 m, 84 m/sec, 1560 t fired, .

Time elapsed: 171 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 25/862 1/32 RERS17pb113-PT-3-LTLFireability-06 1977 m, 83 m/sec, 1976 t fired, .

Time elapsed: 176 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 30/862 1/32 RERS17pb113-PT-3-LTLFireability-06 2454 m, 95 m/sec, 2453 t fired, .

Time elapsed: 181 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 35/862 1/32 RERS17pb113-PT-3-LTLFireability-06 2909 m, 91 m/sec, 2908 t fired, .

Time elapsed: 186 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 40/862 1/32 RERS17pb113-PT-3-LTLFireability-06 3349 m, 88 m/sec, 3348 t fired, .

Time elapsed: 191 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 45/862 1/32 RERS17pb113-PT-3-LTLFireability-06 3795 m, 89 m/sec, 3794 t fired, .

Time elapsed: 196 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 50/862 1/32 RERS17pb113-PT-3-LTLFireability-06 4224 m, 85 m/sec, 4223 t fired, .

Time elapsed: 201 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 55/862 1/32 RERS17pb113-PT-3-LTLFireability-06 4639 m, 83 m/sec, 4638 t fired, .

Time elapsed: 206 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 60/862 1/32 RERS17pb113-PT-3-LTLFireability-06 5075 m, 87 m/sec, 5074 t fired, .

Time elapsed: 211 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 65/862 1/32 RERS17pb113-PT-3-LTLFireability-06 5577 m, 100 m/sec, 5576 t fired, .

Time elapsed: 216 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 70/862 1/32 RERS17pb113-PT-3-LTLFireability-06 6002 m, 85 m/sec, 6001 t fired, .

Time elapsed: 221 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 75/862 1/32 RERS17pb113-PT-3-LTLFireability-06 6497 m, 99 m/sec, 6496 t fired, .

Time elapsed: 226 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 80/862 1/32 RERS17pb113-PT-3-LTLFireability-06 6966 m, 93 m/sec, 6965 t fired, .

Time elapsed: 231 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 85/862 1/32 RERS17pb113-PT-3-LTLFireability-06 7437 m, 94 m/sec, 7436 t fired, .

Time elapsed: 236 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 90/862 1/32 RERS17pb113-PT-3-LTLFireability-06 7865 m, 85 m/sec, 7864 t fired, .

Time elapsed: 241 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 95/862 1/32 RERS17pb113-PT-3-LTLFireability-06 8300 m, 87 m/sec, 8299 t fired, .

Time elapsed: 246 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 100/862 1/32 RERS17pb113-PT-3-LTLFireability-06 8736 m, 87 m/sec, 8735 t fired, .

Time elapsed: 251 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 105/862 1/32 RERS17pb113-PT-3-LTLFireability-06 9196 m, 92 m/sec, 9195 t fired, .

Time elapsed: 256 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 110/862 1/32 RERS17pb113-PT-3-LTLFireability-06 9688 m, 98 m/sec, 9687 t fired, .

Time elapsed: 261 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 115/862 1/32 RERS17pb113-PT-3-LTLFireability-06 10119 m, 86 m/sec, 10118 t fired, .

Time elapsed: 266 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 120/862 1/32 RERS17pb113-PT-3-LTLFireability-06 10557 m, 87 m/sec, 10556 t fired, .

Time elapsed: 271 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 125/862 1/32 RERS17pb113-PT-3-LTLFireability-06 10998 m, 88 m/sec, 10997 t fired, .

Time elapsed: 276 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 130/862 1/32 RERS17pb113-PT-3-LTLFireability-06 11505 m, 101 m/sec, 11504 t fired, .

Time elapsed: 281 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 135/862 1/32 RERS17pb113-PT-3-LTLFireability-06 12012 m, 101 m/sec, 12011 t fired, .

Time elapsed: 286 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 140/862 1/32 RERS17pb113-PT-3-LTLFireability-06 12452 m, 88 m/sec, 12451 t fired, .

Time elapsed: 291 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 145/862 1/32 RERS17pb113-PT-3-LTLFireability-06 12983 m, 106 m/sec, 12982 t fired, .

Time elapsed: 296 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 150/862 1/32 RERS17pb113-PT-3-LTLFireability-06 13509 m, 105 m/sec, 13508 t fired, .

Time elapsed: 301 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 155/862 1/32 RERS17pb113-PT-3-LTLFireability-06 13976 m, 93 m/sec, 13975 t fired, .

Time elapsed: 306 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 160/862 1/32 RERS17pb113-PT-3-LTLFireability-06 14466 m, 98 m/sec, 14465 t fired, .

Time elapsed: 311 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 165/862 1/32 RERS17pb113-PT-3-LTLFireability-06 14922 m, 91 m/sec, 14921 t fired, .

Time elapsed: 316 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 170/862 1/32 RERS17pb113-PT-3-LTLFireability-06 15380 m, 91 m/sec, 15379 t fired, .

Time elapsed: 321 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 175/862 1/32 RERS17pb113-PT-3-LTLFireability-06 15881 m, 100 m/sec, 15880 t fired, .

Time elapsed: 326 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 180/862 1/32 RERS17pb113-PT-3-LTLFireability-06 16394 m, 102 m/sec, 16393 t fired, .

Time elapsed: 331 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 185/862 1/32 RERS17pb113-PT-3-LTLFireability-06 16882 m, 97 m/sec, 16881 t fired, .

Time elapsed: 336 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 190/862 1/32 RERS17pb113-PT-3-LTLFireability-06 17372 m, 98 m/sec, 17371 t fired, .

Time elapsed: 341 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 195/862 1/32 RERS17pb113-PT-3-LTLFireability-06 17834 m, 92 m/sec, 17833 t fired, .

Time elapsed: 346 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 200/862 1/32 RERS17pb113-PT-3-LTLFireability-06 18278 m, 88 m/sec, 18277 t fired, .

Time elapsed: 351 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 205/862 1/32 RERS17pb113-PT-3-LTLFireability-06 18750 m, 94 m/sec, 18749 t fired, .

Time elapsed: 356 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 210/862 1/32 RERS17pb113-PT-3-LTLFireability-06 19216 m, 93 m/sec, 19215 t fired, .

Time elapsed: 361 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 215/862 1/32 RERS17pb113-PT-3-LTLFireability-06 19685 m, 93 m/sec, 19684 t fired, .

Time elapsed: 366 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 220/862 1/32 RERS17pb113-PT-3-LTLFireability-06 20166 m, 96 m/sec, 20165 t fired, .

Time elapsed: 371 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 225/862 1/32 RERS17pb113-PT-3-LTLFireability-06 20662 m, 99 m/sec, 20661 t fired, .

Time elapsed: 376 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 230/862 1/32 RERS17pb113-PT-3-LTLFireability-06 21167 m, 101 m/sec, 21166 t fired, .

Time elapsed: 381 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 235/862 1/32 RERS17pb113-PT-3-LTLFireability-06 21652 m, 97 m/sec, 21651 t fired, .

Time elapsed: 386 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 240/862 1/32 RERS17pb113-PT-3-LTLFireability-06 22093 m, 88 m/sec, 22092 t fired, .

Time elapsed: 391 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 245/862 1/32 RERS17pb113-PT-3-LTLFireability-06 22542 m, 89 m/sec, 22541 t fired, .

Time elapsed: 396 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 250/862 1/32 RERS17pb113-PT-3-LTLFireability-06 23026 m, 96 m/sec, 23025 t fired, .

Time elapsed: 401 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 255/862 1/32 RERS17pb113-PT-3-LTLFireability-06 23515 m, 97 m/sec, 23514 t fired, .

Time elapsed: 406 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 260/862 1/32 RERS17pb113-PT-3-LTLFireability-06 23978 m, 92 m/sec, 23977 t fired, .

Time elapsed: 411 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 265/862 1/32 RERS17pb113-PT-3-LTLFireability-06 24453 m, 95 m/sec, 24452 t fired, .

Time elapsed: 416 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 270/862 1/32 RERS17pb113-PT-3-LTLFireability-06 24944 m, 98 m/sec, 24943 t fired, .

Time elapsed: 421 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 275/862 1/32 RERS17pb113-PT-3-LTLFireability-06 25435 m, 98 m/sec, 25434 t fired, .

Time elapsed: 426 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 280/862 1/32 RERS17pb113-PT-3-LTLFireability-06 25943 m, 101 m/sec, 25942 t fired, .

Time elapsed: 431 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 285/862 1/32 RERS17pb113-PT-3-LTLFireability-06 26428 m, 97 m/sec, 26427 t fired, .

Time elapsed: 436 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 290/862 1/32 RERS17pb113-PT-3-LTLFireability-06 26900 m, 94 m/sec, 26899 t fired, .

Time elapsed: 441 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 295/862 1/32 RERS17pb113-PT-3-LTLFireability-06 27404 m, 100 m/sec, 27403 t fired, .

Time elapsed: 446 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 300/862 1/32 RERS17pb113-PT-3-LTLFireability-06 27902 m, 99 m/sec, 27901 t fired, .

Time elapsed: 451 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 305/862 1/32 RERS17pb113-PT-3-LTLFireability-06 28358 m, 91 m/sec, 28357 t fired, .

Time elapsed: 456 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 310/862 1/32 RERS17pb113-PT-3-LTLFireability-06 28819 m, 92 m/sec, 28818 t fired, .

Time elapsed: 461 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 315/862 1/32 RERS17pb113-PT-3-LTLFireability-06 29292 m, 94 m/sec, 29291 t fired, .

Time elapsed: 466 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 320/862 1/32 RERS17pb113-PT-3-LTLFireability-06 29776 m, 96 m/sec, 29775 t fired, .

Time elapsed: 471 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 325/862 1/32 RERS17pb113-PT-3-LTLFireability-06 30290 m, 102 m/sec, 30289 t fired, .

Time elapsed: 476 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 330/862 1/32 RERS17pb113-PT-3-LTLFireability-06 30779 m, 97 m/sec, 30778 t fired, .

Time elapsed: 481 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 6
lola: FINISHED task # 10 (type EXCL) for RERS17pb113-PT-3-LTLFireability-06
lola: result : false
lola: markings : 30869
lola: fired transitions : 30869
lola: time used : 331.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 RERS17pb113-PT-3-LTLFireability-07
lola: time limit : 1039 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for RERS17pb113-PT-3-LTLFireability-07
lola: result : false
lola: markings : 6985
lola: fired transitions : 6988
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 RERS17pb113-PT-3-LTLFireability-05
lola: time limit : 1559 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 4/1559 2/32 RERS17pb113-PT-3-LTLFireability-05 122828 m, 24565 m/sec, 133849 t fired, .

Time elapsed: 486 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 9/1559 4/32 RERS17pb113-PT-3-LTLFireability-05 275776 m, 30589 m/sec, 306188 t fired, .

Time elapsed: 491 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 14/1559 6/32 RERS17pb113-PT-3-LTLFireability-05 427885 m, 30421 m/sec, 478225 t fired, .

Time elapsed: 496 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 19/1559 8/32 RERS17pb113-PT-3-LTLFireability-05 580299 m, 30482 m/sec, 648482 t fired, .

Time elapsed: 501 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 24/1559 10/32 RERS17pb113-PT-3-LTLFireability-05 731054 m, 30151 m/sec, 817789 t fired, .

Time elapsed: 506 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 29/1559 12/32 RERS17pb113-PT-3-LTLFireability-05 882273 m, 30243 m/sec, 990124 t fired, .

Time elapsed: 511 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 34/1559 14/32 RERS17pb113-PT-3-LTLFireability-05 1031735 m, 29892 m/sec, 1165003 t fired, .

Time elapsed: 516 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 39/1559 16/32 RERS17pb113-PT-3-LTLFireability-05 1181443 m, 29941 m/sec, 1337521 t fired, .

Time elapsed: 521 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 44/1559 18/32 RERS17pb113-PT-3-LTLFireability-05 1331168 m, 29945 m/sec, 1510475 t fired, .

Time elapsed: 526 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 49/1559 20/32 RERS17pb113-PT-3-LTLFireability-05 1480825 m, 29931 m/sec, 1684703 t fired, .

Time elapsed: 531 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 54/1559 22/32 RERS17pb113-PT-3-LTLFireability-05 1630399 m, 29914 m/sec, 1857301 t fired, .

Time elapsed: 536 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 59/1559 23/32 RERS17pb113-PT-3-LTLFireability-05 1778716 m, 29663 m/sec, 2026398 t fired, .

Time elapsed: 541 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 64/1559 25/32 RERS17pb113-PT-3-LTLFireability-05 1927364 m, 29729 m/sec, 2197797 t fired, .

Time elapsed: 546 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 69/1559 27/32 RERS17pb113-PT-3-LTLFireability-05 2074915 m, 29510 m/sec, 2373052 t fired, .

Time elapsed: 551 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 74/1559 29/32 RERS17pb113-PT-3-LTLFireability-05 2222832 m, 29583 m/sec, 2548800 t fired, .

Time elapsed: 556 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 79/1559 31/32 RERS17pb113-PT-3-LTLFireability-05 2371186 m, 29670 m/sec, 2722091 t fired, .

Time elapsed: 561 secs. Pages in use: 31
# running tasks: 1 of 4 Visible: 6
lola: CANCELED task # 7 (type EXCL) for RERS17pb113-PT-3-LTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 566 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
lola: LAUNCH task # 18 (type EXCL) for 15 RERS17pb113-PT-3-LTLFireability-15
lola: time limit : 3034 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 5/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 372 m, 74 m/sec, 371 t fired, .

Time elapsed: 571 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 10/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 703 m, 66 m/sec, 702 t fired, .

Time elapsed: 576 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 15/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 916 m, 42 m/sec, 915 t fired, .

Time elapsed: 581 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 20/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 1320 m, 80 m/sec, 1319 t fired, .

Time elapsed: 586 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 25/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 1729 m, 81 m/sec, 1728 t fired, .

Time elapsed: 591 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 30/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 2147 m, 83 m/sec, 2146 t fired, .

Time elapsed: 596 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 35/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 2572 m, 85 m/sec, 2571 t fired, .

Time elapsed: 601 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 40/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 2989 m, 83 m/sec, 2988 t fired, .

Time elapsed: 606 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 45/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 3415 m, 85 m/sec, 3414 t fired, .

Time elapsed: 611 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 50/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 3718 m, 60 m/sec, 3717 t fired, .

Time elapsed: 616 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 55/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 4127 m, 81 m/sec, 4126 t fired, .

Time elapsed: 621 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 60/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 4533 m, 81 m/sec, 4532 t fired, .

Time elapsed: 626 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 65/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 4958 m, 85 m/sec, 4957 t fired, .

Time elapsed: 631 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 70/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 5391 m, 86 m/sec, 5390 t fired, .

Time elapsed: 636 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 75/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 5816 m, 85 m/sec, 5815 t fired, .

Time elapsed: 641 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 80/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 6235 m, 83 m/sec, 6234 t fired, .

Time elapsed: 646 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 85/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 6653 m, 83 m/sec, 6652 t fired, .

Time elapsed: 651 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 90/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 7098 m, 89 m/sec, 7097 t fired, .

Time elapsed: 656 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 95/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 7522 m, 84 m/sec, 7521 t fired, .

Time elapsed: 661 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 100/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 7928 m, 81 m/sec, 7927 t fired, .

Time elapsed: 666 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 105/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 8310 m, 76 m/sec, 8309 t fired, .

Time elapsed: 671 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 110/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 8725 m, 83 m/sec, 8724 t fired, .

Time elapsed: 676 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 115/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 9145 m, 84 m/sec, 9144 t fired, .

Time elapsed: 681 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 120/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 9570 m, 85 m/sec, 9569 t fired, .

Time elapsed: 686 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 125/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 9991 m, 84 m/sec, 9990 t fired, .

Time elapsed: 691 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 130/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 10417 m, 85 m/sec, 10416 t fired, .

Time elapsed: 696 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 135/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 10838 m, 84 m/sec, 10837 t fired, .

Time elapsed: 701 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 140/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 11251 m, 82 m/sec, 11250 t fired, .

Time elapsed: 706 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 145/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 11662 m, 82 m/sec, 11661 t fired, .

Time elapsed: 711 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 150/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 12078 m, 83 m/sec, 12077 t fired, .

Time elapsed: 716 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 155/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 12413 m, 67 m/sec, 12412 t fired, .

Time elapsed: 721 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-3-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-3-LTLFireability-15: F 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 EG EXCL 160/3034 1/32 RERS17pb113-PT-3-LTLFireability-15 12853 m, 88 m/sec, 12852 t fired, .

Time elapsed: 726 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 6
lola: FINISHED task # 18 (type EXCL) for RERS17pb113-PT-3-LTLFireability-15
lola: result : true
lola: markings : 13218
lola: fired transitions : 13218
lola: time used : 165.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 6

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-3-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-02: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-05: LTL unknown AGGR
RERS17pb113-PT-3-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-07: LTL false LTL model checker
RERS17pb113-PT-3-LTLFireability-15: F false state space / EG


Time elapsed: 731 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RERS17pb113-PT-3"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is RERS17pb113-PT-3, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r327-tall-167889199100020"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RERS17pb113-PT-3.tgz
mv RERS17pb113-PT-3 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;