fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r327-tall-167889199100010
Last Updated
May 14, 2023

About the Execution of LoLa+red for RERS17pb113-PT-2

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
0.000 633662.00 0.00 0.00 [undef] Cannot compute

Execution Chart

Sorry, for this execution, no execution chart could be reported.

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r327-tall-167889199100010.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is RERS17pb113-PT-2, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r327-tall-167889199100010
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 15M
-rw-r--r-- 1 mcc users 6.4K Feb 26 18:12 CTLCardinality.txt
-rw-r--r-- 1 mcc users 66K Feb 26 18:12 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K Feb 26 18:11 CTLFireability.txt
-rw-r--r-- 1 mcc users 40K Feb 26 18:11 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 16:37 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:37 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Feb 25 16:37 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:37 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.7K Feb 26 18:18 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 73K Feb 26 18:18 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.6K Feb 26 18:15 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 51K Feb 26 18:15 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:37 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:37 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 15M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RERS17pb113-PT-2-CTLFireability-00
FORMULA_NAME RERS17pb113-PT-2-CTLFireability-01
FORMULA_NAME RERS17pb113-PT-2-CTLFireability-02
FORMULA_NAME RERS17pb113-PT-2-CTLFireability-03
FORMULA_NAME RERS17pb113-PT-2-CTLFireability-04
FORMULA_NAME RERS17pb113-PT-2-CTLFireability-05
FORMULA_NAME RERS17pb113-PT-2-CTLFireability-06
FORMULA_NAME RERS17pb113-PT-2-CTLFireability-07
FORMULA_NAME RERS17pb113-PT-2-CTLFireability-08
FORMULA_NAME RERS17pb113-PT-2-CTLFireability-09
FORMULA_NAME RERS17pb113-PT-2-CTLFireability-10
FORMULA_NAME RERS17pb113-PT-2-CTLFireability-11
FORMULA_NAME RERS17pb113-PT-2-CTLFireability-12
FORMULA_NAME RERS17pb113-PT-2-CTLFireability-13
FORMULA_NAME RERS17pb113-PT-2-CTLFireability-14
FORMULA_NAME RERS17pb113-PT-2-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678930136970

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RERS17pb113-PT-2
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-16 01:28:58] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-16 01:28:58] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-16 01:28:59] [INFO ] Load time of PNML (sax parser for PT used): 603 ms
[2023-03-16 01:28:59] [INFO ] Transformed 639 places.
[2023-03-16 01:28:59] [INFO ] Transformed 31353 transitions.
[2023-03-16 01:28:59] [INFO ] Parsed PT model containing 639 places and 31353 transitions and 125418 arcs in 806 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 16 ms.
Support contains 154 out of 639 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 639/639 places, 31353/31353 transitions.
Ensure Unique test removed 12 places
Iterating post reduction 0 with 12 rules applied. Total rules applied 12 place count 627 transition count 31353
Applied a total of 12 rules in 184 ms. Remains 627 /639 variables (removed 12) and now considering 31353/31353 (removed 0) transitions.
[2023-03-16 01:28:59] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
// Phase 1: matrix 18326 rows 627 cols
[2023-03-16 01:28:59] [INFO ] Computed 13 place invariants in 113 ms
[2023-03-16 01:29:01] [INFO ] Implicit Places using invariants in 1766 ms returned []
Implicit Place search using SMT only with invariants took 1791 ms to find 0 implicit places.
[2023-03-16 01:29:01] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 01:29:01] [INFO ] Invariant cache hit.
[2023-03-16 01:29:10] [INFO ] Dead Transitions using invariants and state equation in 8637 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 627/639 places, 31353/31353 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10626 ms. Remains : 627/639 places, 31353/31353 transitions.
Support contains 154 out of 627 places after structural reductions.
[2023-03-16 01:29:11] [INFO ] Flatten gal took : 913 ms
[2023-03-16 01:29:12] [INFO ] Flatten gal took : 735 ms
[2023-03-16 01:29:13] [INFO ] Input system was already deterministic with 31353 transitions.
Support contains 139 out of 627 places (down from 154) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 737 ms. (steps per millisecond=13 ) properties (out of 67) seen :22
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=76 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=76 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 56 ms. (steps per millisecond=17 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 45) seen :0
Running SMT prover for 45 properties.
[2023-03-16 01:29:15] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 01:29:15] [INFO ] Invariant cache hit.
[2023-03-16 01:29:16] [INFO ] [Real]Absence check using 13 positive place invariants in 8 ms returned sat
[2023-03-16 01:29:40] [INFO ] After 24683ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0 real:44
[2023-03-16 01:29:41] [INFO ] [Nat]Absence check using 13 positive place invariants in 7 ms returned sat
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Broken pipe ...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.checkResults(DeadlockTester.java:797)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:631)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 01:30:05] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 01:30:05] [INFO ] After 25052ms SMT Verify possible using all constraints in natural domain returned unsat :1 sat :0 real:44
Fused 45 Parikh solutions to 27 different solutions.
Parikh walk visited 0 properties in 172 ms.
Support contains 86 out of 627 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 352 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 354 ms. Remains : 627/627 places, 31353/31353 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 889 ms. (steps per millisecond=11 ) properties (out of 43) seen :6
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 66 ms. (steps per millisecond=15 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 36 ms. (steps per millisecond=27 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 37) seen :0
Running SMT prover for 37 properties.
[2023-03-16 01:30:07] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 01:30:07] [INFO ] Invariant cache hit.
[2023-03-16 01:30:08] [INFO ] [Real]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 01:30:33] [INFO ] After 24132ms SMT Verify possible using state equation in real domain returned unsat :0 sat :17 real:19
[2023-03-16 01:30:33] [INFO ] State equation strengthened by 829 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 01:30:33] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 01:30:33] [INFO ] After 25312ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Fused 37 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 76 out of 627 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 345 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 345 ms. Remains : 627/627 places, 31353/31353 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 736 ms. (steps per millisecond=13 ) properties (out of 37) seen :4
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 33) seen :0
Running SMT prover for 33 properties.
[2023-03-16 01:30:34] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 01:30:34] [INFO ] Invariant cache hit.
[2023-03-16 01:30:35] [INFO ] [Real]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 01:31:00] [INFO ] After 24359ms SMT Verify possible using state equation in real domain returned unsat :0 sat :9 real:24
[2023-03-16 01:31:00] [INFO ] State equation strengthened by 829 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 01:31:00] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 01:31:00] [INFO ] After 25441ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Fused 33 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 71 out of 627 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 196 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 196 ms. Remains : 627/627 places, 31353/31353 transitions.
Successfully simplified 2 atomic propositions for a total of 16 simplifications.
[2023-03-16 01:31:01] [INFO ] Flatten gal took : 603 ms
[2023-03-16 01:31:02] [INFO ] Flatten gal took : 702 ms
[2023-03-16 01:31:03] [INFO ] Input system was already deterministic with 31353 transitions.
Support contains 116 out of 627 places (down from 120) after GAL structural reductions.
Computed a total of 1 stabilizing places and 1 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 74 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 77 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 01:31:04] [INFO ] Flatten gal took : 557 ms
[2023-03-16 01:31:05] [INFO ] Flatten gal took : 674 ms
[2023-03-16 01:31:06] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 249 ms. Remains 626 /627 variables (removed 1) and now considering 31352/31353 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 250 ms. Remains : 626/627 places, 31352/31353 transitions.
[2023-03-16 01:31:07] [INFO ] Flatten gal took : 598 ms
[2023-03-16 01:31:08] [INFO ] Flatten gal took : 693 ms
[2023-03-16 01:31:10] [INFO ] Input system was already deterministic with 31352 transitions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 75 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 76 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 01:31:10] [INFO ] Flatten gal took : 590 ms
[2023-03-16 01:31:11] [INFO ] Flatten gal took : 690 ms
[2023-03-16 01:31:13] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 176 ms. Remains 626 /627 variables (removed 1) and now considering 31352/31353 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 178 ms. Remains : 626/627 places, 31352/31353 transitions.
[2023-03-16 01:31:13] [INFO ] Flatten gal took : 529 ms
[2023-03-16 01:31:14] [INFO ] Flatten gal took : 622 ms
[2023-03-16 01:31:16] [INFO ] Input system was already deterministic with 31352 transitions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 111 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 112 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 01:31:16] [INFO ] Flatten gal took : 597 ms
[2023-03-16 01:31:17] [INFO ] Flatten gal took : 665 ms
[2023-03-16 01:31:18] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 69 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 70 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 01:31:19] [INFO ] Flatten gal took : 536 ms
[2023-03-16 01:31:20] [INFO ] Flatten gal took : 639 ms
[2023-03-16 01:31:21] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 170 ms. Remains 626 /627 variables (removed 1) and now considering 31352/31353 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 170 ms. Remains : 626/627 places, 31352/31353 transitions.
[2023-03-16 01:31:22] [INFO ] Flatten gal took : 535 ms
[2023-03-16 01:31:23] [INFO ] Flatten gal took : 623 ms
[2023-03-16 01:31:24] [INFO ] Input system was already deterministic with 31352 transitions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 70 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 70 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 01:31:25] [INFO ] Flatten gal took : 535 ms
[2023-03-16 01:31:25] [INFO ] Flatten gal took : 623 ms
[2023-03-16 01:31:27] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 70 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 70 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 01:31:28] [INFO ] Flatten gal took : 538 ms
[2023-03-16 01:31:28] [INFO ] Flatten gal took : 652 ms
[2023-03-16 01:31:29] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 70 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 70 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 01:31:30] [INFO ] Flatten gal took : 533 ms
[2023-03-16 01:31:31] [INFO ] Flatten gal took : 626 ms
[2023-03-16 01:31:32] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 68 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 69 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 01:31:33] [INFO ] Flatten gal took : 533 ms
[2023-03-16 01:31:33] [INFO ] Flatten gal took : 626 ms
[2023-03-16 01:31:35] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 171 ms. Remains 626 /627 variables (removed 1) and now considering 31352/31353 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 171 ms. Remains : 626/627 places, 31352/31353 transitions.
[2023-03-16 01:31:36] [INFO ] Flatten gal took : 534 ms
[2023-03-16 01:31:36] [INFO ] Flatten gal took : 614 ms
[2023-03-16 01:31:37] [INFO ] Input system was already deterministic with 31352 transitions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 68 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 69 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 01:31:38] [INFO ] Flatten gal took : 528 ms
[2023-03-16 01:31:39] [INFO ] Flatten gal took : 617 ms
[2023-03-16 01:31:40] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 69 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 70 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 01:31:41] [INFO ] Flatten gal took : 565 ms
[2023-03-16 01:31:41] [INFO ] Flatten gal took : 589 ms
[2023-03-16 01:31:43] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 69 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 69 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 01:31:43] [INFO ] Flatten gal took : 536 ms
[2023-03-16 01:31:44] [INFO ] Flatten gal took : 615 ms
[2023-03-16 01:31:45] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 68 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 69 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 01:31:46] [INFO ] Flatten gal took : 589 ms
[2023-03-16 01:31:47] [INFO ] Flatten gal took : 718 ms
[2023-03-16 01:31:49] [INFO ] Input system was already deterministic with 31353 transitions.
[2023-03-16 01:31:49] [INFO ] Flatten gal took : 664 ms
[2023-03-16 01:31:50] [INFO ] Flatten gal took : 698 ms
[2023-03-16 01:31:50] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-16 01:31:50] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 627 places, 31353 transitions and 125406 arcs took 115 ms.
Total runtime 172282 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT RERS17pb113-PT-2
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/376
CTLFireability

BK_STOP 1678930770632

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/376/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/376/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/376/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-2-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-CTLFireability-01: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-CTLFireability-02: DISJ 0 0 0 0 0 0 0 0
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RERS17pb113-PT-2-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-2-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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/home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin//../BenchKit_head.sh: line 63: 499 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RERS17pb113-PT-2"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is RERS17pb113-PT-2, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r327-tall-167889199100010"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RERS17pb113-PT-2.tgz
mv RERS17pb113-PT-2 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;