fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r326-tall-167889198800762
Last Updated
May 14, 2023

About the Execution of LoLA for ResAllocation-PT-R050C002

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
2988.436 280471.00 253240.00 891.60 F??????TTTTF?T?? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r326-tall-167889198800762.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is ResAllocation-PT-R050C002, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r326-tall-167889198800762
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 704K
-rw-r--r-- 1 mcc users 6.6K Feb 25 15:30 CTLCardinality.txt
-rw-r--r-- 1 mcc users 65K Feb 25 15:30 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K Feb 25 15:29 CTLFireability.txt
-rw-r--r-- 1 mcc users 54K Feb 25 15:29 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:45 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:45 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 16:45 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:45 LTLFireability.xml
-rw-r--r-- 1 mcc users 16K Feb 25 15:32 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 167K Feb 25 15:32 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.1K Feb 25 15:31 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 64K Feb 25 15:31 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 16:45 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:45 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 9 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 212K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ResAllocation-PT-R050C002-CTLFireability-00
FORMULA_NAME ResAllocation-PT-R050C002-CTLFireability-01
FORMULA_NAME ResAllocation-PT-R050C002-CTLFireability-02
FORMULA_NAME ResAllocation-PT-R050C002-CTLFireability-03
FORMULA_NAME ResAllocation-PT-R050C002-CTLFireability-04
FORMULA_NAME ResAllocation-PT-R050C002-CTLFireability-05
FORMULA_NAME ResAllocation-PT-R050C002-CTLFireability-06
FORMULA_NAME ResAllocation-PT-R050C002-CTLFireability-07
FORMULA_NAME ResAllocation-PT-R050C002-CTLFireability-08
FORMULA_NAME ResAllocation-PT-R050C002-CTLFireability-09
FORMULA_NAME ResAllocation-PT-R050C002-CTLFireability-10
FORMULA_NAME ResAllocation-PT-R050C002-CTLFireability-11
FORMULA_NAME ResAllocation-PT-R050C002-CTLFireability-12
FORMULA_NAME ResAllocation-PT-R050C002-CTLFireability-13
FORMULA_NAME ResAllocation-PT-R050C002-CTLFireability-14
FORMULA_NAME ResAllocation-PT-R050C002-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679077993913

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ResAllocation-PT-R050C002
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT ResAllocation-PT-R050C002
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA ResAllocation-PT-R050C002-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R050C002-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R050C002-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R050C002-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R050C002-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R050C002-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R050C002-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679078274384

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 48 (type EXCL) for 0 ResAllocation-PT-R050C002-CTLFireability-00
lola: time limit : 179 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: FINISHED task # 48 (type EXCL) for ResAllocation-PT-R050C002-CTLFireability-00
lola: result : true
lola: markings : 795
lola: fired transitions : 794
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 24 ResAllocation-PT-R050C002-CTLFireability-08
lola: time limit : 199 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 25 (type EXCL) for ResAllocation-PT-R050C002-CTLFireability-08
lola: result : true
lola: markings : 106
lola: fired transitions : 215
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 ResAllocation-PT-R050C002-CTLFireability-05
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 5/257 7/32 ResAllocation-PT-R050C002-CTLFireability-05 1590635 m, 318127 m/sec, 8788131 t fired, .

Time elapsed: 6 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 10/257 13/32 ResAllocation-PT-R050C002-CTLFireability-05 3021676 m, 286208 m/sec, 17470145 t fired, .

Time elapsed: 11 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 15/257 19/32 ResAllocation-PT-R050C002-CTLFireability-05 4318921 m, 259449 m/sec, 25805002 t fired, .

Time elapsed: 16 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 20/257 24/32 ResAllocation-PT-R050C002-CTLFireability-05 5681282 m, 272472 m/sec, 34065339 t fired, .

Time elapsed: 21 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 25/257 30/32 ResAllocation-PT-R050C002-CTLFireability-05 7026575 m, 269058 m/sec, 42399772 t fired, .

Time elapsed: 26 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 16 (type EXCL) for ResAllocation-PT-R050C002-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 31 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 43 (type EXCL) for 42 ResAllocation-PT-R050C002-CTLFireability-14
lola: time limit : 274 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 5/274 7/32 ResAllocation-PT-R050C002-CTLFireability-14 1452772 m, 290554 m/sec, 9418476 t fired, .

Time elapsed: 36 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 10/274 12/32 ResAllocation-PT-R050C002-CTLFireability-14 2725555 m, 254556 m/sec, 18424038 t fired, .

Time elapsed: 41 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 15/274 17/32 ResAllocation-PT-R050C002-CTLFireability-14 3939909 m, 242870 m/sec, 27194853 t fired, .

Time elapsed: 46 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 20/274 22/32 ResAllocation-PT-R050C002-CTLFireability-14 5084488 m, 228915 m/sec, 35707948 t fired, .

Time elapsed: 51 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 25/274 27/32 ResAllocation-PT-R050C002-CTLFireability-14 6290130 m, 241128 m/sec, 44285707 t fired, .

Time elapsed: 56 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 30/274 32/32 ResAllocation-PT-R050C002-CTLFireability-14 7462321 m, 234438 m/sec, 52715631 t fired, .

Time elapsed: 61 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 43 (type EXCL) for ResAllocation-PT-R050C002-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 66 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 40 (type EXCL) for 39 ResAllocation-PT-R050C002-CTLFireability-13
lola: time limit : 294 sec
lola: memory limit: 32 pages
lola: FINISHED task # 40 (type EXCL) for ResAllocation-PT-R050C002-CTLFireability-13
lola: result : true
lola: markings : 106
lola: fired transitions : 106
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 37 (type EXCL) for 36 ResAllocation-PT-R050C002-CTLFireability-12
lola: time limit : 321 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 5/321 7/32 ResAllocation-PT-R050C002-CTLFireability-12 1640611 m, 328122 m/sec, 9118396 t fired, .

Time elapsed: 71 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 10/321 14/32 ResAllocation-PT-R050C002-CTLFireability-12 3089671 m, 289812 m/sec, 17845318 t fired, .

Time elapsed: 76 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 15/321 19/32 ResAllocation-PT-R050C002-CTLFireability-12 4385767 m, 259219 m/sec, 26255777 t fired, .

Time elapsed: 81 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 20/321 25/32 ResAllocation-PT-R050C002-CTLFireability-12 5755142 m, 273875 m/sec, 34533014 t fired, .

Time elapsed: 86 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 25/321 30/32 ResAllocation-PT-R050C002-CTLFireability-12 7084957 m, 265963 m/sec, 42790301 t fired, .

Time elapsed: 91 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 37 (type EXCL) for ResAllocation-PT-R050C002-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 96 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 34 (type EXCL) for 33 ResAllocation-PT-R050C002-CTLFireability-11
lola: time limit : 350 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for ResAllocation-PT-R050C002-CTLFireability-11
lola: result : false
lola: markings : 106
lola: fired transitions : 603
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 ResAllocation-PT-R050C002-CTLFireability-10
lola: time limit : 389 sec
lola: memory limit: 32 pages
lola: FINISHED task # 31 (type EXCL) for ResAllocation-PT-R050C002-CTLFireability-10
lola: result : true
lola: markings : 106
lola: fired transitions : 108
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 28 (type EXCL) for 27 ResAllocation-PT-R050C002-CTLFireability-09
lola: time limit : 438 sec
lola: memory limit: 32 pages
lola: FINISHED task # 28 (type EXCL) for ResAllocation-PT-R050C002-CTLFireability-09
lola: result : true
lola: markings : 106
lola: fired transitions : 213
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 ResAllocation-PT-R050C002-CTLFireability-07
lola: time limit : 500 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for ResAllocation-PT-R050C002-CTLFireability-07
lola: result : true
lola: markings : 87
lola: fired transitions : 89
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 ResAllocation-PT-R050C002-CTLFireability-06
lola: time limit : 584 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 5/584 8/32 ResAllocation-PT-R050C002-CTLFireability-06 1665003 m, 333000 m/sec, 9252321 t fired, .

Time elapsed: 101 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 10/584 14/32 ResAllocation-PT-R050C002-CTLFireability-06 3146537 m, 296306 m/sec, 18128768 t fired, .

Time elapsed: 106 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 15/584 19/32 ResAllocation-PT-R050C002-CTLFireability-06 4449708 m, 260634 m/sec, 26674009 t fired, .

Time elapsed: 111 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 20/584 25/32 ResAllocation-PT-R050C002-CTLFireability-06 5850397 m, 280137 m/sec, 35128359 t fired, .

Time elapsed: 116 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 25/584 31/32 ResAllocation-PT-R050C002-CTLFireability-06 7193070 m, 268534 m/sec, 43479095 t fired, .

Time elapsed: 121 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 19 (type EXCL) for ResAllocation-PT-R050C002-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 126 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 13 (type EXCL) for 12 ResAllocation-PT-R050C002-CTLFireability-04
lola: time limit : 694 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/694 8/32 ResAllocation-PT-R050C002-CTLFireability-04 1669477 m, 333895 m/sec, 9275162 t fired, .

Time elapsed: 131 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 10/694 14/32 ResAllocation-PT-R050C002-CTLFireability-04 3151448 m, 296394 m/sec, 18158937 t fired, .

Time elapsed: 136 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 15/694 19/32 ResAllocation-PT-R050C002-CTLFireability-04 4464444 m, 262599 m/sec, 26774838 t fired, .

Time elapsed: 141 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 20/694 25/32 ResAllocation-PT-R050C002-CTLFireability-04 5864411 m, 279993 m/sec, 35219987 t fired, .

Time elapsed: 146 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 25/694 31/32 ResAllocation-PT-R050C002-CTLFireability-04 7209139 m, 268945 m/sec, 43592793 t fired, .

Time elapsed: 151 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 13 (type EXCL) for ResAllocation-PT-R050C002-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 156 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 7 (type EXCL) for 6 ResAllocation-PT-R050C002-CTLFireability-02
lola: time limit : 861 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/861 6/32 ResAllocation-PT-R050C002-CTLFireability-02 1361248 m, 272249 m/sec, 9196217 t fired, .

Time elapsed: 161 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/861 11/32 ResAllocation-PT-R050C002-CTLFireability-02 2583494 m, 244449 m/sec, 18015542 t fired, .

Time elapsed: 166 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/861 16/32 ResAllocation-PT-R050C002-CTLFireability-02 3760022 m, 235305 m/sec, 26685904 t fired, .

Time elapsed: 171 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/861 21/32 ResAllocation-PT-R050C002-CTLFireability-02 4838791 m, 215753 m/sec, 35083250 t fired, .

Time elapsed: 176 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 25/861 26/32 ResAllocation-PT-R050C002-CTLFireability-02 5966349 m, 225511 m/sec, 43410409 t fired, .

Time elapsed: 181 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 30/861 30/32 ResAllocation-PT-R050C002-CTLFireability-02 7098398 m, 226409 m/sec, 51771009 t fired, .

Time elapsed: 186 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 7 (type EXCL) for ResAllocation-PT-R050C002-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 191 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 4 (type EXCL) for 3 ResAllocation-PT-R050C002-CTLFireability-01
lola: time limit : 1136 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/1136 6/32 ResAllocation-PT-R050C002-CTLFireability-01 1222074 m, 244414 m/sec, 9458166 t fired, .

Time elapsed: 196 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/1136 10/32 ResAllocation-PT-R050C002-CTLFireability-01 2328408 m, 221266 m/sec, 18572690 t fired, .

Time elapsed: 201 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/1136 15/32 ResAllocation-PT-R050C002-CTLFireability-01 3428539 m, 220026 m/sec, 27582054 t fired, .

Time elapsed: 206 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 20/1136 19/32 ResAllocation-PT-R050C002-CTLFireability-01 4402896 m, 194871 m/sec, 36290699 t fired, .

Time elapsed: 211 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 25/1136 23/32 ResAllocation-PT-R050C002-CTLFireability-01 5427885 m, 204997 m/sec, 44853308 t fired, .

Time elapsed: 216 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 30/1136 28/32 ResAllocation-PT-R050C002-CTLFireability-01 6455755 m, 205574 m/sec, 53605987 t fired, .

Time elapsed: 221 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 35/1136 32/32 ResAllocation-PT-R050C002-CTLFireability-01 7469625 m, 202774 m/sec, 62135408 t fired, .

Time elapsed: 226 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 4 (type EXCL) for ResAllocation-PT-R050C002-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 231 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 46 (type EXCL) for 45 ResAllocation-PT-R050C002-CTLFireability-15
lola: time limit : 1684 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 5/1684 8/32 ResAllocation-PT-R050C002-CTLFireability-15 1678622 m, 335724 m/sec, 9330460 t fired, .

Time elapsed: 236 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 10/1684 14/32 ResAllocation-PT-R050C002-CTLFireability-15 3174521 m, 299179 m/sec, 18291431 t fired, .

Time elapsed: 241 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 15/1684 19/32 ResAllocation-PT-R050C002-CTLFireability-15 4395610 m, 244217 m/sec, 26319126 t fired, .

Time elapsed: 246 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 20/1684 24/32 ResAllocation-PT-R050C002-CTLFireability-15 5677767 m, 256431 m/sec, 34043974 t fired, .

Time elapsed: 251 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 25/1684 30/32 ResAllocation-PT-R050C002-CTLFireability-15 7041809 m, 272808 m/sec, 42508117 t fired, .

Time elapsed: 256 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 46 (type EXCL) for ResAllocation-PT-R050C002-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 261 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 10 (type EXCL) for 9 ResAllocation-PT-R050C002-CTLFireability-03
lola: time limit : 3339 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/3339 13/32 ResAllocation-PT-R050C002-CTLFireability-03 2858426 m, 571685 m/sec, 8263433 t fired, .

Time elapsed: 266 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 10/3339 23/32 ResAllocation-PT-R050C002-CTLFireability-03 5328257 m, 493966 m/sec, 15784640 t fired, .

Time elapsed: 271 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 15/3339 32/32 ResAllocation-PT-R050C002-CTLFireability-03 7583376 m, 451023 m/sec, 22765738 t fired, .

Time elapsed: 276 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 10 (type EXCL) for ResAllocation-PT-R050C002-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R050C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 281 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-CTLFireability-00: F false state space / EG
ResAllocation-PT-R050C002-CTLFireability-01: CTL unknown AGGR
ResAllocation-PT-R050C002-CTLFireability-02: CTL unknown AGGR
ResAllocation-PT-R050C002-CTLFireability-03: CTL unknown AGGR
ResAllocation-PT-R050C002-CTLFireability-04: CTL unknown AGGR
ResAllocation-PT-R050C002-CTLFireability-05: CTL unknown AGGR
ResAllocation-PT-R050C002-CTLFireability-06: CTL unknown AGGR
ResAllocation-PT-R050C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-08: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-10: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R050C002-CTLFireability-12: CTL unknown AGGR
ResAllocation-PT-R050C002-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R050C002-CTLFireability-14: CTL unknown AGGR
ResAllocation-PT-R050C002-CTLFireability-15: CTL unknown AGGR


Time elapsed: 281 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ResAllocation-PT-R050C002"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is ResAllocation-PT-R050C002, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r326-tall-167889198800762"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ResAllocation-PT-R050C002.tgz
mv ResAllocation-PT-R050C002 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;