About the Execution of LoLA for ResAllocation-PT-R003C100
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
3365.688 | 596059.00 | 581973.00 | 1340.80 | ?F??FF?F??T?TTFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r326-tall-167889198800722.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is ResAllocation-PT-R003C100, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r326-tall-167889198800722
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.2M
-rw-r--r-- 1 mcc users 7.4K Feb 25 15:23 CTLCardinality.txt
-rw-r--r-- 1 mcc users 76K Feb 25 15:23 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K Feb 25 15:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 53K Feb 25 15:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 16:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Feb 25 16:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 16:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 10K Feb 25 15:24 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 97K Feb 25 15:24 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 10K Feb 25 15:24 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 84K Feb 25 15:24 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 16:44 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:44 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 9 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 721K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-00
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-01
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-02
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-03
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-04
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-05
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-06
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-07
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-08
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-09
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-10
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-11
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-12
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-13
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-14
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679074729988
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ResAllocation-PT-R003C100
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT ResAllocation-PT-R003C100
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability
FORMULA ResAllocation-PT-R003C100-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R003C100-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R003C100-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R003C100-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R003C100-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R003C100-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R003C100-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R003C100-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R003C100-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679075326047
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 6 (type EXCL) for 3 ResAllocation-PT-R003C100-CTLFireability-01
lola: time limit : 150 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
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ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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lola: result : true
lola: markings : 9855
lola: fired transitions : 12818
lola: time used : 0.000000
lola: memory pages used : 1
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lola: markings : 95
lola: fired transitions : 145
lola: time used : 0.000000
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lola: markings : 4
lola: fired transitions : 11
lola: time used : 0.000000
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lola: time used : 0.000000
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ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 60/321 32/32 ResAllocation-PT-R003C100-CTLFireability-09 6132995 m, 98392 m/sec, 47419032 t fired, .
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ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
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lola: fired transitions : 504
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ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
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ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
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ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
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ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
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ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
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ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
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ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
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ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
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ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
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lola: result : false
lola: markings : 159
lola: fired transitions : 197
lola: time used : 0.000000
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ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
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ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
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ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
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ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
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ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
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ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
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ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
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ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 65/3075 31/32 ResAllocation-PT-R003C100-CTLFireability-11 6877017 m, 93434 m/sec, 62607669 t fired, .
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lola: CANCELED task # 42 (type EXCL) for ResAllocation-PT-R003C100-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-00: CTL unknown AGGR
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-02: CTL unknown AGGR
ResAllocation-PT-R003C100-CTLFireability-03: AGEF unknown AGGR
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-06: CTL unknown AGGR
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-08: CTL unknown AGGR
ResAllocation-PT-R003C100-CTLFireability-09: CTL unknown AGGR
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-11: CTL unknown AGGR
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ResAllocation-PT-R003C100"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is ResAllocation-PT-R003C100, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r326-tall-167889198800722"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ResAllocation-PT-R003C100.tgz
mv ResAllocation-PT-R003C100 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;