fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r326-tall-167889198800722
Last Updated
May 14, 2023

About the Execution of LoLA for ResAllocation-PT-R003C100

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
3365.688 596059.00 581973.00 1340.80 ?F??FF?F??T?TTFT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r326-tall-167889198800722.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is ResAllocation-PT-R003C100, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r326-tall-167889198800722
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.2M
-rw-r--r-- 1 mcc users 7.4K Feb 25 15:23 CTLCardinality.txt
-rw-r--r-- 1 mcc users 76K Feb 25 15:23 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K Feb 25 15:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 53K Feb 25 15:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 16:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Feb 25 16:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 16:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 10K Feb 25 15:24 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 97K Feb 25 15:24 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 10K Feb 25 15:24 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 84K Feb 25 15:24 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 16:44 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:44 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 9 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 721K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-00
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-01
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-02
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-03
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-04
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-05
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-06
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-07
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-08
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-09
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-10
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-11
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-12
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-13
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-14
FORMULA_NAME ResAllocation-PT-R003C100-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679074729988

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ResAllocation-PT-R003C100
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT ResAllocation-PT-R003C100
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA ResAllocation-PT-R003C100-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C100-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C100-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C100-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C100-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C100-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C100-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C100-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C100-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679075326047

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 6 (type EXCL) for 3 ResAllocation-PT-R003C100-CTLFireability-01
lola: time limit : 150 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 1 0 2 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 5/200 4/32 ResAllocation-PT-R003C100-CTLFireability-01 581803 m, 116360 m/sec, 4228914 t fired, .

Time elapsed: 5 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 1 0 2 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 10/200 7/32 ResAllocation-PT-R003C100-CTLFireability-01 1127157 m, 109070 m/sec, 8633702 t fired, .

Time elapsed: 10 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 1 0 2 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 15/200 9/32 ResAllocation-PT-R003C100-CTLFireability-01 1656388 m, 105846 m/sec, 12890149 t fired, .

Time elapsed: 15 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 1 0 2 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 20/200 12/32 ResAllocation-PT-R003C100-CTLFireability-01 2181516 m, 105025 m/sec, 17073660 t fired, .

Time elapsed: 20 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 1 0 2 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 25/200 15/32 ResAllocation-PT-R003C100-CTLFireability-01 2678479 m, 99392 m/sec, 21208616 t fired, .

Time elapsed: 25 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 1 0 2 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 30/200 18/32 ResAllocation-PT-R003C100-CTLFireability-01 3223466 m, 108997 m/sec, 25155949 t fired, .

Time elapsed: 30 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 1 0 2 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 35/200 20/32 ResAllocation-PT-R003C100-CTLFireability-01 3765273 m, 108361 m/sec, 29015914 t fired, .

Time elapsed: 35 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 1 0 2 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 40/200 23/32 ResAllocation-PT-R003C100-CTLFireability-01 4258870 m, 98719 m/sec, 32920692 t fired, .

Time elapsed: 40 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 1 0 2 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 45/200 25/32 ResAllocation-PT-R003C100-CTLFireability-01 4777102 m, 103646 m/sec, 36953578 t fired, .

Time elapsed: 45 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 1 0 2 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 50/200 28/32 ResAllocation-PT-R003C100-CTLFireability-01 5301637 m, 104907 m/sec, 40949169 t fired, .

Time elapsed: 50 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 1 0 2 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 55/200 31/32 ResAllocation-PT-R003C100-CTLFireability-01 5814580 m, 102588 m/sec, 45030028 t fired, .

Time elapsed: 55 secs. Pages in use: 31
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 6 (type EXCL) for ResAllocation-PT-R003C100-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 60 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 54 (type EXCL) for 53 ResAllocation-PT-R003C100-CTLFireability-15
lola: time limit : 208 sec
lola: memory limit: 32 pages
lola: FINISHED task # 54 (type EXCL) for ResAllocation-PT-R003C100-CTLFireability-15
lola: result : true
lola: markings : 9855
lola: fired transitions : 12818
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 51 (type EXCL) for 50 ResAllocation-PT-R003C100-CTLFireability-14
lola: time limit : 221 sec
lola: memory limit: 32 pages
lola: FINISHED task # 51 (type EXCL) for ResAllocation-PT-R003C100-CTLFireability-14
lola: result : false
lola: markings : 95
lola: fired transitions : 145
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 48 (type EXCL) for 47 ResAllocation-PT-R003C100-CTLFireability-13
lola: time limit : 236 sec
lola: memory limit: 32 pages
lola: FINISHED task # 48 (type EXCL) for ResAllocation-PT-R003C100-CTLFireability-13
lola: result : true
lola: markings : 4
lola: fired transitions : 11
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 45 (type EXCL) for 44 ResAllocation-PT-R003C100-CTLFireability-12
lola: time limit : 252 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for ResAllocation-PT-R003C100-CTLFireability-12
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 39 (type EXCL) for 34 ResAllocation-PT-R003C100-CTLFireability-10
lola: time limit : 272 sec
lola: memory limit: 32 pages
lola: FINISHED task # 39 (type EXCL) for ResAllocation-PT-R003C100-CTLFireability-10
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 37 (type EXCL) for 34 ResAllocation-PT-R003C100-CTLFireability-10
lola: time limit : 295 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for ResAllocation-PT-R003C100-CTLFireability-10
lola: result : true
lola: markings : 401
lola: fired transitions : 499
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 32 (type EXCL) for 31 ResAllocation-PT-R003C100-CTLFireability-09
lola: time limit : 321 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 5/321 4/32 ResAllocation-PT-R003C100-CTLFireability-09 613519 m, 122703 m/sec, 4451165 t fired, .

Time elapsed: 65 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 10/321 7/32 ResAllocation-PT-R003C100-CTLFireability-09 1121810 m, 101658 m/sec, 8593437 t fired, .

Time elapsed: 70 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 15/321 9/32 ResAllocation-PT-R003C100-CTLFireability-09 1634791 m, 102596 m/sec, 12691403 t fired, .

Time elapsed: 75 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 20/321 12/32 ResAllocation-PT-R003C100-CTLFireability-09 2137887 m, 100619 m/sec, 16747240 t fired, .

Time elapsed: 80 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 25/321 15/32 ResAllocation-PT-R003C100-CTLFireability-09 2619801 m, 96382 m/sec, 20742599 t fired, .

Time elapsed: 85 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 30/321 17/32 ResAllocation-PT-R003C100-CTLFireability-09 3143891 m, 104818 m/sec, 24574877 t fired, .

Time elapsed: 90 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 35/321 20/32 ResAllocation-PT-R003C100-CTLFireability-09 3675774 m, 106376 m/sec, 28327277 t fired, .

Time elapsed: 95 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 40/321 22/32 ResAllocation-PT-R003C100-CTLFireability-09 4168301 m, 98505 m/sec, 32238647 t fired, .

Time elapsed: 100 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 45/321 25/32 ResAllocation-PT-R003C100-CTLFireability-09 4667314 m, 99802 m/sec, 36054178 t fired, .

Time elapsed: 105 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 50/321 27/32 ResAllocation-PT-R003C100-CTLFireability-09 5148774 m, 96292 m/sec, 39840692 t fired, .

Time elapsed: 110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 55/321 30/32 ResAllocation-PT-R003C100-CTLFireability-09 5641035 m, 98452 m/sec, 43657188 t fired, .

Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 60/321 32/32 ResAllocation-PT-R003C100-CTLFireability-09 6132995 m, 98392 m/sec, 47419032 t fired, .

Time elapsed: 120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 32 (type EXCL) for ResAllocation-PT-R003C100-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 26 (type EXCL) for 25 ResAllocation-PT-R003C100-CTLFireability-07
lola: time limit : 347 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for ResAllocation-PT-R003C100-CTLFireability-07
lola: result : false
lola: markings : 404
lola: fired transitions : 504
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 23 (type EXCL) for 22 ResAllocation-PT-R003C100-CTLFireability-06
lola: time limit : 386 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 5/386 4/32 ResAllocation-PT-R003C100-CTLFireability-06 596396 m, 119279 m/sec, 4342415 t fired, .

Time elapsed: 130 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 10/386 6/32 ResAllocation-PT-R003C100-CTLFireability-06 1106493 m, 102019 m/sec, 8461416 t fired, .

Time elapsed: 135 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 15/386 9/32 ResAllocation-PT-R003C100-CTLFireability-06 1615338 m, 101769 m/sec, 12524698 t fired, .

Time elapsed: 140 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 20/386 12/32 ResAllocation-PT-R003C100-CTLFireability-06 2115661 m, 100064 m/sec, 16559445 t fired, .

Time elapsed: 145 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 25/386 14/32 ResAllocation-PT-R003C100-CTLFireability-06 2591589 m, 95185 m/sec, 20525172 t fired, .

Time elapsed: 150 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 30/386 17/32 ResAllocation-PT-R003C100-CTLFireability-06 3111273 m, 103936 m/sec, 24338056 t fired, .

Time elapsed: 155 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 35/386 20/32 ResAllocation-PT-R003C100-CTLFireability-06 3640936 m, 105932 m/sec, 28057549 t fired, .

Time elapsed: 160 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 40/386 22/32 ResAllocation-PT-R003C100-CTLFireability-06 4112994 m, 94411 m/sec, 31829964 t fired, .

Time elapsed: 165 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 45/386 25/32 ResAllocation-PT-R003C100-CTLFireability-06 4608880 m, 99177 m/sec, 35572962 t fired, .

Time elapsed: 170 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 50/386 27/32 ResAllocation-PT-R003C100-CTLFireability-06 5082037 m, 94631 m/sec, 39317685 t fired, .

Time elapsed: 175 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 55/386 29/32 ResAllocation-PT-R003C100-CTLFireability-06 5569520 m, 97496 m/sec, 43069561 t fired, .

Time elapsed: 180 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 60/386 32/32 ResAllocation-PT-R003C100-CTLFireability-06 6064220 m, 98940 m/sec, 46889821 t fired, .

Time elapsed: 185 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 23 (type EXCL) for ResAllocation-PT-R003C100-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 190 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 20 (type EXCL) for 19 ResAllocation-PT-R003C100-CTLFireability-05
lola: time limit : 426 sec
lola: memory limit: 32 pages
lola: FINISHED task # 20 (type EXCL) for ResAllocation-PT-R003C100-CTLFireability-05
lola: result : false
lola: markings : 406
lola: fired transitions : 505
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 11 (type EXCL) for 10 ResAllocation-PT-R003C100-CTLFireability-02
lola: time limit : 487 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 5/487 3/32 ResAllocation-PT-R003C100-CTLFireability-02 532034 m, 106406 m/sec, 4402387 t fired, .

Time elapsed: 195 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 10/487 6/32 ResAllocation-PT-R003C100-CTLFireability-02 999195 m, 93432 m/sec, 8556164 t fired, .

Time elapsed: 200 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 15/487 8/32 ResAllocation-PT-R003C100-CTLFireability-02 1452987 m, 90758 m/sec, 12622505 t fired, .

Time elapsed: 205 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 20/487 11/32 ResAllocation-PT-R003C100-CTLFireability-02 1890426 m, 87487 m/sec, 16714323 t fired, .

Time elapsed: 210 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 25/487 13/32 ResAllocation-PT-R003C100-CTLFireability-02 2334774 m, 88869 m/sec, 20735085 t fired, .

Time elapsed: 215 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 30/487 15/32 ResAllocation-PT-R003C100-CTLFireability-02 2773035 m, 87652 m/sec, 24672830 t fired, .

Time elapsed: 220 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 35/487 18/32 ResAllocation-PT-R003C100-CTLFireability-02 3238926 m, 93178 m/sec, 28507243 t fired, .

Time elapsed: 225 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 40/487 20/32 ResAllocation-PT-R003C100-CTLFireability-02 3710727 m, 94360 m/sec, 32286559 t fired, .

Time elapsed: 230 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 45/487 22/32 ResAllocation-PT-R003C100-CTLFireability-02 4129900 m, 83834 m/sec, 36089492 t fired, .

Time elapsed: 235 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 50/487 24/32 ResAllocation-PT-R003C100-CTLFireability-02 4576579 m, 89335 m/sec, 39872619 t fired, .

Time elapsed: 240 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 55/487 27/32 ResAllocation-PT-R003C100-CTLFireability-02 4996174 m, 83919 m/sec, 43662738 t fired, .

Time elapsed: 245 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 60/487 29/32 ResAllocation-PT-R003C100-CTLFireability-02 5437768 m, 88318 m/sec, 47441750 t fired, .

Time elapsed: 250 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 65/487 31/32 ResAllocation-PT-R003C100-CTLFireability-02 5861162 m, 84678 m/sec, 51237024 t fired, .

Time elapsed: 255 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 11 (type EXCL) for ResAllocation-PT-R003C100-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 260 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 8 (type EXCL) for 3 ResAllocation-PT-R003C100-CTLFireability-01
lola: time limit : 556 sec
lola: memory limit: 32 pages
lola: FINISHED task # 8 (type EXCL) for ResAllocation-PT-R003C100-CTLFireability-01
lola: result : false
lola: markings : 159
lola: fired transitions : 197
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 ResAllocation-PT-R003C100-CTLFireability-00
lola: time limit : 668 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/668 2/32 ResAllocation-PT-R003C100-CTLFireability-00 298967 m, 59793 m/sec, 2113541 t fired, .

Time elapsed: 265 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/668 4/32 ResAllocation-PT-R003C100-CTLFireability-00 639780 m, 68162 m/sec, 5794644 t fired, .

Time elapsed: 270 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/668 6/32 ResAllocation-PT-R003C100-CTLFireability-00 918808 m, 55805 m/sec, 9300364 t fired, .

Time elapsed: 275 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 20/668 8/32 ResAllocation-PT-R003C100-CTLFireability-00 1284811 m, 73200 m/sec, 13039565 t fired, .

Time elapsed: 280 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 25/668 9/32 ResAllocation-PT-R003C100-CTLFireability-00 1556303 m, 54298 m/sec, 16543732 t fired, .

Time elapsed: 285 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 30/668 11/32 ResAllocation-PT-R003C100-CTLFireability-00 1854565 m, 59652 m/sec, 20112671 t fired, .

Time elapsed: 290 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 35/668 12/32 ResAllocation-PT-R003C100-CTLFireability-00 2190541 m, 67195 m/sec, 23752294 t fired, .

Time elapsed: 295 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 40/668 14/32 ResAllocation-PT-R003C100-CTLFireability-00 2455938 m, 53079 m/sec, 27217266 t fired, .

Time elapsed: 300 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 45/668 15/32 ResAllocation-PT-R003C100-CTLFireability-00 2771088 m, 63030 m/sec, 30783536 t fired, .

Time elapsed: 305 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 50/668 17/32 ResAllocation-PT-R003C100-CTLFireability-00 3078482 m, 61478 m/sec, 34296425 t fired, .

Time elapsed: 310 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 55/668 18/32 ResAllocation-PT-R003C100-CTLFireability-00 3341194 m, 52542 m/sec, 37730597 t fired, .

Time elapsed: 315 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 60/668 20/32 ResAllocation-PT-R003C100-CTLFireability-00 3623049 m, 56371 m/sec, 41165042 t fired, .

Time elapsed: 320 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 65/668 21/32 ResAllocation-PT-R003C100-CTLFireability-00 3897573 m, 54904 m/sec, 44589243 t fired, .

Time elapsed: 325 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 70/668 23/32 ResAllocation-PT-R003C100-CTLFireability-00 4175120 m, 55509 m/sec, 48035251 t fired, .

Time elapsed: 330 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 75/668 24/32 ResAllocation-PT-R003C100-CTLFireability-00 4449151 m, 54806 m/sec, 51504635 t fired, .

Time elapsed: 335 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 80/668 25/32 ResAllocation-PT-R003C100-CTLFireability-00 4707020 m, 51573 m/sec, 54957667 t fired, .

Time elapsed: 340 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 85/668 27/32 ResAllocation-PT-R003C100-CTLFireability-00 4948138 m, 48223 m/sec, 58355001 t fired, .

Time elapsed: 345 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 90/668 28/32 ResAllocation-PT-R003C100-CTLFireability-00 5208099 m, 51992 m/sec, 61914126 t fired, .

Time elapsed: 350 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 95/668 29/32 ResAllocation-PT-R003C100-CTLFireability-00 5469027 m, 52185 m/sec, 65429251 t fired, .

Time elapsed: 355 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 100/668 31/32 ResAllocation-PT-R003C100-CTLFireability-00 5723170 m, 50828 m/sec, 68946287 t fired, .

Time elapsed: 360 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 105/668 32/32 ResAllocation-PT-R003C100-CTLFireability-00 5974235 m, 50213 m/sec, 72434441 t fired, .

Time elapsed: 365 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 1 (type EXCL) for ResAllocation-PT-R003C100-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 370 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 14 (type EXCL) for 13 ResAllocation-PT-R003C100-CTLFireability-03
lola: time limit : 807 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 AGEF EXCL 5/807 3/32 ResAllocation-PT-R003C100-CTLFireability-03 703569 m, 140713 m/sec, 5784538 t fired, .

Time elapsed: 375 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 AGEF EXCL 10/807 6/32 ResAllocation-PT-R003C100-CTLFireability-03 1344054 m, 128097 m/sec, 11417333 t fired, .

Time elapsed: 380 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 AGEF EXCL 15/807 8/32 ResAllocation-PT-R003C100-CTLFireability-03 1895992 m, 110387 m/sec, 16809689 t fired, .

Time elapsed: 385 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 AGEF EXCL 20/807 10/32 ResAllocation-PT-R003C100-CTLFireability-03 2446693 m, 110140 m/sec, 22222487 t fired, .

Time elapsed: 390 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 AGEF EXCL 25/807 12/32 ResAllocation-PT-R003C100-CTLFireability-03 3022758 m, 115213 m/sec, 27626775 t fired, .

Time elapsed: 395 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 AGEF EXCL 30/807 14/32 ResAllocation-PT-R003C100-CTLFireability-03 3551017 m, 105651 m/sec, 32815816 t fired, .

Time elapsed: 400 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 AGEF EXCL 35/807 16/32 ResAllocation-PT-R003C100-CTLFireability-03 4047669 m, 99330 m/sec, 37946043 t fired, .

Time elapsed: 405 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 AGEF EXCL 40/807 18/32 ResAllocation-PT-R003C100-CTLFireability-03 4507376 m, 91941 m/sec, 43015898 t fired, .

Time elapsed: 410 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 AGEF EXCL 45/807 20/32 ResAllocation-PT-R003C100-CTLFireability-03 5077001 m, 113925 m/sec, 48294429 t fired, .

Time elapsed: 415 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 AGEF EXCL 50/807 23/32 ResAllocation-PT-R003C100-CTLFireability-03 5651460 m, 114891 m/sec, 53521802 t fired, .

Time elapsed: 420 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 AGEF EXCL 55/807 25/32 ResAllocation-PT-R003C100-CTLFireability-03 6199278 m, 109563 m/sec, 58722157 t fired, .

Time elapsed: 425 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 AGEF EXCL 60/807 27/32 ResAllocation-PT-R003C100-CTLFireability-03 6762403 m, 112625 m/sec, 64089067 t fired, .

Time elapsed: 430 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 AGEF EXCL 65/807 29/32 ResAllocation-PT-R003C100-CTLFireability-03 7317189 m, 110957 m/sec, 69425626 t fired, .

Time elapsed: 435 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 AGEF EXCL 70/807 31/32 ResAllocation-PT-R003C100-CTLFireability-03 7839421 m, 104446 m/sec, 74706884 t fired, .

Time elapsed: 440 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 14 (type EXCL) for ResAllocation-PT-R003C100-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 445 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 56 (type EXCL) for 16 ResAllocation-PT-R003C100-CTLFireability-04
lola: time limit : 1051 sec
lola: memory limit: 32 pages
lola: FINISHED task # 56 (type EXCL) for ResAllocation-PT-R003C100-CTLFireability-04
lola: result : false
lola: markings : 4
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 29 (type EXCL) for 28 ResAllocation-PT-R003C100-CTLFireability-08
lola: time limit : 1577 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 5/1577 4/32 ResAllocation-PT-R003C100-CTLFireability-08 654607 m, 130921 m/sec, 6033850 t fired, .

Time elapsed: 450 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 10/1577 6/32 ResAllocation-PT-R003C100-CTLFireability-08 1191817 m, 107442 m/sec, 11651703 t fired, .

Time elapsed: 455 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 15/1577 8/32 ResAllocation-PT-R003C100-CTLFireability-08 1726161 m, 106868 m/sec, 17110014 t fired, .

Time elapsed: 460 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 20/1577 11/32 ResAllocation-PT-R003C100-CTLFireability-08 2246229 m, 104013 m/sec, 22445059 t fired, .

Time elapsed: 465 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 25/1577 13/32 ResAllocation-PT-R003C100-CTLFireability-08 2735020 m, 97758 m/sec, 27552570 t fired, .

Time elapsed: 470 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 30/1577 15/32 ResAllocation-PT-R003C100-CTLFireability-08 3188033 m, 90602 m/sec, 32604435 t fired, .

Time elapsed: 475 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 35/1577 17/32 ResAllocation-PT-R003C100-CTLFireability-08 3620528 m, 86499 m/sec, 37645279 t fired, .

Time elapsed: 480 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 40/1577 18/32 ResAllocation-PT-R003C100-CTLFireability-08 4055896 m, 87073 m/sec, 42677731 t fired, .

Time elapsed: 485 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 45/1577 20/32 ResAllocation-PT-R003C100-CTLFireability-08 4496460 m, 88112 m/sec, 47735397 t fired, .

Time elapsed: 490 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 50/1577 22/32 ResAllocation-PT-R003C100-CTLFireability-08 4951690 m, 91046 m/sec, 52757206 t fired, .

Time elapsed: 495 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 55/1577 24/32 ResAllocation-PT-R003C100-CTLFireability-08 5419616 m, 93585 m/sec, 57713984 t fired, .

Time elapsed: 500 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 60/1577 26/32 ResAllocation-PT-R003C100-CTLFireability-08 5852279 m, 86532 m/sec, 62639101 t fired, .

Time elapsed: 505 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 65/1577 28/32 ResAllocation-PT-R003C100-CTLFireability-08 6291076 m, 87759 m/sec, 67563523 t fired, .

Time elapsed: 510 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 70/1577 30/32 ResAllocation-PT-R003C100-CTLFireability-08 6724965 m, 86777 m/sec, 72487995 t fired, .

Time elapsed: 515 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 75/1577 31/32 ResAllocation-PT-R003C100-CTLFireability-08 7151963 m, 85399 m/sec, 77380748 t fired, .

Time elapsed: 520 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 29 (type EXCL) for ResAllocation-PT-R003C100-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 525 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 42 (type EXCL) for 41 ResAllocation-PT-R003C100-CTLFireability-11
lola: time limit : 3075 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 5/3075 4/32 ResAllocation-PT-R003C100-CTLFireability-11 702763 m, 140552 m/sec, 5434819 t fired, .

Time elapsed: 530 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 10/3075 6/32 ResAllocation-PT-R003C100-CTLFireability-11 1282649 m, 115977 m/sec, 10514024 t fired, .

Time elapsed: 535 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 15/3075 9/32 ResAllocation-PT-R003C100-CTLFireability-11 1868968 m, 117263 m/sec, 15601225 t fired, .

Time elapsed: 540 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 20/3075 12/32 ResAllocation-PT-R003C100-CTLFireability-11 2438000 m, 113806 m/sec, 20577588 t fired, .

Time elapsed: 545 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 25/3075 14/32 ResAllocation-PT-R003C100-CTLFireability-11 2965332 m, 105466 m/sec, 25358209 t fired, .

Time elapsed: 550 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 30/3075 16/32 ResAllocation-PT-R003C100-CTLFireability-11 3474153 m, 101764 m/sec, 30089065 t fired, .

Time elapsed: 555 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 35/3075 19/32 ResAllocation-PT-R003C100-CTLFireability-11 3961646 m, 97498 m/sec, 34809515 t fired, .

Time elapsed: 560 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 40/3075 21/32 ResAllocation-PT-R003C100-CTLFireability-11 4438240 m, 95318 m/sec, 39512747 t fired, .

Time elapsed: 565 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 45/3075 23/32 ResAllocation-PT-R003C100-CTLFireability-11 4909436 m, 94239 m/sec, 44275264 t fired, .

Time elapsed: 570 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 50/3075 25/32 ResAllocation-PT-R003C100-CTLFireability-11 5426251 m, 103363 m/sec, 48937137 t fired, .

Time elapsed: 575 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 55/3075 27/32 ResAllocation-PT-R003C100-CTLFireability-11 5934840 m, 101717 m/sec, 53502298 t fired, .

Time elapsed: 580 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 60/3075 29/32 ResAllocation-PT-R003C100-CTLFireability-11 6409847 m, 95001 m/sec, 58027156 t fired, .

Time elapsed: 585 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 65/3075 31/32 ResAllocation-PT-R003C100-CTLFireability-11 6877017 m, 93434 m/sec, 62607669 t fired, .

Time elapsed: 590 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 42 (type EXCL) for ResAllocation-PT-R003C100-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C100-CTLFireability-11: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 595 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C100-CTLFireability-00: CTL unknown AGGR
ResAllocation-PT-R003C100-CTLFireability-01: CONJ false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-02: CTL unknown AGGR
ResAllocation-PT-R003C100-CTLFireability-03: AGEF unknown AGGR
ResAllocation-PT-R003C100-CTLFireability-04: SP ACTL false LTL model checker
ResAllocation-PT-R003C100-CTLFireability-05: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-06: CTL unknown AGGR
ResAllocation-PT-R003C100-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-08: CTL unknown AGGR
ResAllocation-PT-R003C100-CTLFireability-09: CTL unknown AGGR
ResAllocation-PT-R003C100-CTLFireability-10: DISJ true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-11: CTL unknown AGGR
ResAllocation-PT-R003C100-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C100-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C100-CTLFireability-15: CTL true CTL model checker


Time elapsed: 595 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ResAllocation-PT-R003C100"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is ResAllocation-PT-R003C100, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r326-tall-167889198800722"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ResAllocation-PT-R003C100.tgz
mv ResAllocation-PT-R003C100 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;