Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r326-tall-167889198800714.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.............................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is ResAllocation-PT-R003C050, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r326-tall-167889198800714
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 816K
-rw-r--r-- 1 mcc users 8.3K Feb 25 15:20 CTLCardinality.txt
-rw-r--r-- 1 mcc users 91K Feb 25 15:20 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.8K Feb 25 15:20 CTLFireability.txt
-rw-r--r-- 1 mcc users 51K Feb 25 15:20 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 16:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.3K Feb 25 15:22 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 89K Feb 25 15:22 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.7K Feb 25 15:21 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 81K Feb 25 15:21 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 16:44 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:44 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 9 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 360K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-00
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-01
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-02
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-03
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-04
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-05
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-06
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-07
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-08
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-09
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-10
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-11
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-12
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-13
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-14
FORMULA_NAME ResAllocation-PT-R003C050-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679074260884

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ResAllocation-PT-R003C050
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT ResAllocation-PT-R003C050
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA ResAllocation-PT-R003C050-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C050-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C050-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C050-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C050-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C050-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C050-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C050-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679074621512

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:183
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 25 (type EXCL) for 24 ResAllocation-PT-R003C050-CTLFireability-08
lola: time limit : 149 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 5/224 7/32 ResAllocation-PT-R003C050-CTLFireability-08 1566860 m, 313372 m/sec, 5599719 t fired, .

Time elapsed: 6 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 10/224 13/32 ResAllocation-PT-R003C050-CTLFireability-08 2997743 m, 286176 m/sec, 10988590 t fired, .

Time elapsed: 11 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 15/224 19/32 ResAllocation-PT-R003C050-CTLFireability-08 4326412 m, 265733 m/sec, 16267536 t fired, .

Time elapsed: 16 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 20/224 24/32 ResAllocation-PT-R003C050-CTLFireability-08 5554351 m, 245587 m/sec, 21352016 t fired, .

Time elapsed: 21 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 25/224 29/32 ResAllocation-PT-R003C050-CTLFireability-08 6845396 m, 258209 m/sec, 26545408 t fired, .

Time elapsed: 26 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 25 (type EXCL) for ResAllocation-PT-R003C050-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 31 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 46 (type EXCL) for 45 ResAllocation-PT-R003C050-CTLFireability-15
lola: time limit : 237 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 5/237 5/32 ResAllocation-PT-R003C050-CTLFireability-15 1124281 m, 224856 m/sec, 6293370 t fired, .

Time elapsed: 36 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 10/237 10/32 ResAllocation-PT-R003C050-CTLFireability-15 2155002 m, 206144 m/sec, 12289710 t fired, .

Time elapsed: 41 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 15/237 14/32 ResAllocation-PT-R003C050-CTLFireability-15 3149554 m, 198910 m/sec, 18032404 t fired, .

Time elapsed: 46 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 20/237 18/32 ResAllocation-PT-R003C050-CTLFireability-15 4118054 m, 193700 m/sec, 23636851 t fired, .

Time elapsed: 51 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 25/237 21/32 ResAllocation-PT-R003C050-CTLFireability-15 4963318 m, 169052 m/sec, 29059574 t fired, .

Time elapsed: 56 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 30/237 25/32 ResAllocation-PT-R003C050-CTLFireability-15 5837142 m, 174764 m/sec, 34634220 t fired, .

Time elapsed: 61 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 35/237 29/32 ResAllocation-PT-R003C050-CTLFireability-15 6733383 m, 179248 m/sec, 40294692 t fired, .

Time elapsed: 66 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 46 (type EXCL) for ResAllocation-PT-R003C050-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 71 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 40 (type EXCL) for 39 ResAllocation-PT-R003C050-CTLFireability-13
lola: time limit : 252 sec
lola: memory limit: 32 pages
lola: FINISHED task # 40 (type EXCL) for ResAllocation-PT-R003C050-CTLFireability-13
lola: result : true
lola: markings : 187
lola: fired transitions : 439
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 37 (type EXCL) for 36 ResAllocation-PT-R003C050-CTLFireability-12
lola: time limit : 271 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for ResAllocation-PT-R003C050-CTLFireability-12
lola: result : true
lola: markings : 4
lola: fired transitions : 7
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 33 ResAllocation-PT-R003C050-CTLFireability-11
lola: time limit : 294 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for ResAllocation-PT-R003C050-CTLFireability-11
lola: result : true
lola: markings : 587
lola: fired transitions : 1380
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 28 (type EXCL) for 27 ResAllocation-PT-R003C050-CTLFireability-09
lola: time limit : 320 sec
lola: memory limit: 32 pages
lola: FINISHED task # 28 (type EXCL) for ResAllocation-PT-R003C050-CTLFireability-09
lola: result : true
lola: markings : 13
lola: fired transitions : 24
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 ResAllocation-PT-R003C050-CTLFireability-07
lola: time limit : 352 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for ResAllocation-PT-R003C050-CTLFireability-07
lola: result : true
lola: markings : 4
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 ResAllocation-PT-R003C050-CTLFireability-06
lola: time limit : 392 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 5/392 5/32 ResAllocation-PT-R003C050-CTLFireability-06 1170654 m, 234130 m/sec, 6562860 t fired, .

Time elapsed: 76 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 10/392 10/32 ResAllocation-PT-R003C050-CTLFireability-06 2222172 m, 210303 m/sec, 12706275 t fired, .

Time elapsed: 81 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 15/392 14/32 ResAllocation-PT-R003C050-CTLFireability-06 3235981 m, 202761 m/sec, 18581657 t fired, .

Time elapsed: 86 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 20/392 18/32 ResAllocation-PT-R003C050-CTLFireability-06 4220081 m, 196820 m/sec, 24263307 t fired, .

Time elapsed: 91 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 25/392 22/32 ResAllocation-PT-R003C050-CTLFireability-06 5097100 m, 175403 m/sec, 29831456 t fired, .

Time elapsed: 96 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 30/392 26/32 ResAllocation-PT-R003C050-CTLFireability-06 5959196 m, 172419 m/sec, 35452309 t fired, .

Time elapsed: 101 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 35/392 29/32 ResAllocation-PT-R003C050-CTLFireability-06 6855846 m, 179330 m/sec, 41094436 t fired, .

Time elapsed: 106 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 19 (type EXCL) for ResAllocation-PT-R003C050-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 111 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 16 (type EXCL) for 15 ResAllocation-PT-R003C050-CTLFireability-05
lola: time limit : 436 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 5/436 5/32 ResAllocation-PT-R003C050-CTLFireability-05 1010492 m, 202098 m/sec, 6631991 t fired, .

Time elapsed: 116 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 10/436 9/32 ResAllocation-PT-R003C050-CTLFireability-05 1937874 m, 185476 m/sec, 12950298 t fired, .

Time elapsed: 121 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 15/436 13/32 ResAllocation-PT-R003C050-CTLFireability-05 2837973 m, 180019 m/sec, 19079761 t fired, .

Time elapsed: 126 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 20/436 16/32 ResAllocation-PT-R003C050-CTLFireability-05 3748849 m, 182175 m/sec, 25177584 t fired, .

Time elapsed: 131 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 25/436 20/32 ResAllocation-PT-R003C050-CTLFireability-05 4562253 m, 162680 m/sec, 30994139 t fired, .

Time elapsed: 136 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 30/436 23/32 ResAllocation-PT-R003C050-CTLFireability-05 5339560 m, 155461 m/sec, 36779885 t fired, .

Time elapsed: 141 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 35/436 26/32 ResAllocation-PT-R003C050-CTLFireability-05 6098429 m, 151773 m/sec, 42454311 t fired, .

Time elapsed: 146 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 40/436 30/32 ResAllocation-PT-R003C050-CTLFireability-05 6899128 m, 160139 m/sec, 48308862 t fired, .

Time elapsed: 151 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 16 (type EXCL) for ResAllocation-PT-R003C050-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 156 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 13 (type EXCL) for 12 ResAllocation-PT-R003C050-CTLFireability-04
lola: time limit : 492 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for ResAllocation-PT-R003C050-CTLFireability-04
lola: result : true
lola: markings : 587
lola: fired transitions : 794
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 ResAllocation-PT-R003C050-CTLFireability-03
lola: time limit : 574 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/574 7/32 ResAllocation-PT-R003C050-CTLFireability-03 1487831 m, 297566 m/sec, 5674488 t fired, .

Time elapsed: 161 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 10/574 12/32 ResAllocation-PT-R003C050-CTLFireability-03 2807879 m, 264009 m/sec, 11010646 t fired, .

Time elapsed: 166 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 15/574 18/32 ResAllocation-PT-R003C050-CTLFireability-03 4067042 m, 251832 m/sec, 16137557 t fired, .

Time elapsed: 171 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 20/574 23/32 ResAllocation-PT-R003C050-CTLFireability-03 5315900 m, 249771 m/sec, 21216641 t fired, .

Time elapsed: 176 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 25/574 28/32 ResAllocation-PT-R003C050-CTLFireability-03 6506201 m, 238060 m/sec, 26055273 t fired, .

Time elapsed: 181 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 10 (type EXCL) for ResAllocation-PT-R003C050-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 186 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 7 (type EXCL) for 6 ResAllocation-PT-R003C050-CTLFireability-02
lola: time limit : 682 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/682 5/32 ResAllocation-PT-R003C050-CTLFireability-02 971892 m, 194378 m/sec, 6359181 t fired, .

Time elapsed: 191 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/682 8/32 ResAllocation-PT-R003C050-CTLFireability-02 1833715 m, 172364 m/sec, 12294253 t fired, .

Time elapsed: 196 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/682 12/32 ResAllocation-PT-R003C050-CTLFireability-02 2689949 m, 171246 m/sec, 18091458 t fired, .

Time elapsed: 201 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/682 15/32 ResAllocation-PT-R003C050-CTLFireability-02 3525614 m, 167133 m/sec, 23746754 t fired, .

Time elapsed: 206 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 25/682 19/32 ResAllocation-PT-R003C050-CTLFireability-02 4323372 m, 159551 m/sec, 29182759 t fired, .

Time elapsed: 211 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 30/682 22/32 ResAllocation-PT-R003C050-CTLFireability-02 5043667 m, 144059 m/sec, 34571519 t fired, .

Time elapsed: 216 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 35/682 25/32 ResAllocation-PT-R003C050-CTLFireability-02 5783990 m, 148064 m/sec, 40054170 t fired, .

Time elapsed: 221 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 40/682 28/32 ResAllocation-PT-R003C050-CTLFireability-02 6518721 m, 146946 m/sec, 45469651 t fired, .

Time elapsed: 226 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 45/682 31/32 ResAllocation-PT-R003C050-CTLFireability-02 7262803 m, 148816 m/sec, 50859822 t fired, .

Time elapsed: 231 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 7 (type EXCL) for ResAllocation-PT-R003C050-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 236 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 4 (type EXCL) for 3 ResAllocation-PT-R003C050-CTLFireability-01
lola: time limit : 841 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for ResAllocation-PT-R003C050-CTLFireability-01
lola: result : true
lola: markings : 4
lola: fired transitions : 21
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 48 (type EXCL) for 42 ResAllocation-PT-R003C050-CTLFireability-14
lola: time limit : 1121 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 AGEF EXCL 5/1121 4/32 ResAllocation-PT-R003C050-CTLFireability-14 893335 m, 178667 m/sec, 7785317 t fired, .

Time elapsed: 241 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 AGEF EXCL 10/1121 7/32 ResAllocation-PT-R003C050-CTLFireability-14 1696182 m, 160569 m/sec, 15293811 t fired, .

Time elapsed: 246 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 AGEF EXCL 15/1121 10/32 ResAllocation-PT-R003C050-CTLFireability-14 2473947 m, 155553 m/sec, 22884485 t fired, .

Time elapsed: 251 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 AGEF EXCL 20/1121 12/32 ResAllocation-PT-R003C050-CTLFireability-14 3225689 m, 150348 m/sec, 30428236 t fired, .

Time elapsed: 256 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 AGEF EXCL 25/1121 15/32 ResAllocation-PT-R003C050-CTLFireability-14 3916856 m, 138233 m/sec, 37662155 t fired, .

Time elapsed: 261 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 AGEF EXCL 30/1121 18/32 ResAllocation-PT-R003C050-CTLFireability-14 4670082 m, 150645 m/sec, 45053028 t fired, .

Time elapsed: 266 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 AGEF EXCL 35/1121 20/32 ResAllocation-PT-R003C050-CTLFireability-14 5387841 m, 143551 m/sec, 52317136 t fired, .

Time elapsed: 271 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 AGEF EXCL 40/1121 23/32 ResAllocation-PT-R003C050-CTLFireability-14 6155681 m, 153568 m/sec, 59625211 t fired, .

Time elapsed: 276 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 AGEF EXCL 45/1121 26/32 ResAllocation-PT-R003C050-CTLFireability-14 6860841 m, 141032 m/sec, 66728622 t fired, .

Time elapsed: 281 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 AGEF EXCL 50/1121 28/32 ResAllocation-PT-R003C050-CTLFireability-14 7527226 m, 133277 m/sec, 73802189 t fired, .

Time elapsed: 286 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 AGEF EXCL 55/1121 31/32 ResAllocation-PT-R003C050-CTLFireability-14 8251871 m, 144929 m/sec, 81103379 t fired, .

Time elapsed: 291 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 48 (type EXCL) for ResAllocation-PT-R003C050-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 296 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 1 (type EXCL) for 0 ResAllocation-PT-R003C050-CTLFireability-00
lola: time limit : 1652 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for ResAllocation-PT-R003C050-CTLFireability-00
lola: result : true
lola: markings : 4
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 ResAllocation-PT-R003C050-CTLFireability-10
lola: time limit : 3304 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-00: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 5/3304 4/32 ResAllocation-PT-R003C050-CTLFireability-10 785189 m, 157037 m/sec, 7114453 t fired, .

Time elapsed: 301 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-00: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 10/3304 7/32 ResAllocation-PT-R003C050-CTLFireability-10 1504203 m, 143802 m/sec, 14078135 t fired, .

Time elapsed: 306 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-00: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 15/3304 9/32 ResAllocation-PT-R003C050-CTLFireability-10 2189346 m, 137028 m/sec, 20925970 t fired, .

Time elapsed: 311 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-00: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 20/3304 12/32 ResAllocation-PT-R003C050-CTLFireability-10 2830485 m, 128227 m/sec, 27596300 t fired, .

Time elapsed: 316 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-00: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 25/3304 15/32 ResAllocation-PT-R003C050-CTLFireability-10 3469815 m, 127866 m/sec, 34190468 t fired, .

Time elapsed: 321 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-00: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 30/3304 17/32 ResAllocation-PT-R003C050-CTLFireability-10 4072782 m, 120593 m/sec, 40675913 t fired, .

Time elapsed: 326 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-00: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 35/3304 20/32 ResAllocation-PT-R003C050-CTLFireability-10 4696548 m, 124753 m/sec, 47316375 t fired, .

Time elapsed: 331 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-00: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 40/3304 22/32 ResAllocation-PT-R003C050-CTLFireability-10 5285528 m, 117796 m/sec, 53854241 t fired, .

Time elapsed: 336 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-00: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 45/3304 24/32 ResAllocation-PT-R003C050-CTLFireability-10 5852217 m, 113337 m/sec, 60292457 t fired, .

Time elapsed: 341 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-00: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 50/3304 27/32 ResAllocation-PT-R003C050-CTLFireability-10 6544720 m, 138500 m/sec, 67089282 t fired, .

Time elapsed: 346 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-00: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 55/3304 30/32 ResAllocation-PT-R003C050-CTLFireability-10 7173537 m, 125763 m/sec, 73617390 t fired, .

Time elapsed: 351 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-00: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 60/3304 32/32 ResAllocation-PT-R003C050-CTLFireability-10 7815419 m, 128376 m/sec, 80150265 t fired, .

Time elapsed: 356 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 31 (type EXCL) for ResAllocation-PT-R003C050-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-00: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-14: EFAG 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 361 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C050-CTLFireability-00: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-01: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-02: CTL unknown AGGR
ResAllocation-PT-R003C050-CTLFireability-03: CTL unknown AGGR
ResAllocation-PT-R003C050-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-05: CTL unknown AGGR
ResAllocation-PT-R003C050-CTLFireability-06: CTL unknown AGGR
ResAllocation-PT-R003C050-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-08: CTL unknown AGGR
ResAllocation-PT-R003C050-CTLFireability-09: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-10: CTL unknown AGGR
ResAllocation-PT-R003C050-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C050-CTLFireability-14: EFAG unknown AGGR
ResAllocation-PT-R003C050-CTLFireability-15: CTL unknown AGGR


Time elapsed: 361 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ResAllocation-PT-R003C050"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is ResAllocation-PT-R003C050, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r326-tall-167889198800714"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ResAllocation-PT-R003C050.tgz
mv ResAllocation-PT-R003C050 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;