Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r326-tall-167889198700700.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is ResAllocation-PT-R003C015, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r326-tall-167889198700700
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 548K
-rw-r--r-- 1 mcc users 6.8K Feb 25 15:20 CTLCardinality.txt
-rw-r--r-- 1 mcc users 68K Feb 25 15:20 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.4K Feb 25 15:19 CTLFireability.txt
-rw-r--r-- 1 mcc users 59K Feb 25 15:19 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 16:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.1K Feb 25 15:21 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 86K Feb 25 15:21 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 15:21 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 92K Feb 25 15:21 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 16:44 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:44 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 9 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 107K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ResAllocation-PT-R003C015-LTLFireability-00
FORMULA_NAME ResAllocation-PT-R003C015-LTLFireability-01
FORMULA_NAME ResAllocation-PT-R003C015-LTLFireability-02
FORMULA_NAME ResAllocation-PT-R003C015-LTLFireability-03
FORMULA_NAME ResAllocation-PT-R003C015-LTLFireability-04
FORMULA_NAME ResAllocation-PT-R003C015-LTLFireability-05
FORMULA_NAME ResAllocation-PT-R003C015-LTLFireability-06
FORMULA_NAME ResAllocation-PT-R003C015-LTLFireability-07
FORMULA_NAME ResAllocation-PT-R003C015-LTLFireability-08
FORMULA_NAME ResAllocation-PT-R003C015-LTLFireability-09
FORMULA_NAME ResAllocation-PT-R003C015-LTLFireability-10
FORMULA_NAME ResAllocation-PT-R003C015-LTLFireability-11
FORMULA_NAME ResAllocation-PT-R003C015-LTLFireability-12
FORMULA_NAME ResAllocation-PT-R003C015-LTLFireability-13
FORMULA_NAME ResAllocation-PT-R003C015-LTLFireability-14
FORMULA_NAME ResAllocation-PT-R003C015-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1679073546776

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=LTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ResAllocation-PT-R003C015
Not applying reductions.
Model is PT
LTLFireability PT
starting LoLA
BK_INPUT ResAllocation-PT-R003C015
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
LTLFireability

FORMULA ResAllocation-PT-R003C015-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C015-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C015-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C015-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C015-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C015-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C015-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C015-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C015-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C015-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C015-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C015-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C015-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C015-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679073586934

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/LTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:518
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:409
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:373
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 4 (type EXCL) for 3 ResAllocation-PT-R003C015-LTLFireability-01
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 61 (type FNDP) for 30 ResAllocation-PT-R003C015-LTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 62 (type EQUN) for 30 ResAllocation-PT-R003C015-LTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 64 (type SRCH) for 30 ResAllocation-PT-R003C015-LTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 64 (type SRCH) for ResAllocation-PT-R003C015-LTLFireability-10
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 61 (type FNDP) for ResAllocation-PT-R003C015-LTLFireability-10
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 62 (type EQUN) for ResAllocation-PT-R003C015-LTLFireability-10 (obsolete)
sara: try reading problem file /home/mcc/execution/LTLFireability-62.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 62 (type EQUN) for ResAllocation-PT-R003C015-LTLFireability-10
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C015-LTLFireability-10: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C015-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
ResAllocation-PT-R003C015-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 LTL EXCL 5/211 9/32 ResAllocation-PT-R003C015-LTLFireability-01 1284297 m, 256859 m/sec, 10124046 t fired, .

Time elapsed: 5 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 4 (type EXCL) for ResAllocation-PT-R003C015-LTLFireability-01
lola: result : false
lola: markings : 1690652
lola: fired transitions : 13708848
lola: time used : 7.000000
lola: memory pages used : 11
lola: LAUNCH task # 58 (type EXCL) for 57 ResAllocation-PT-R003C015-LTLFireability-15
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: FINISHED task # 58 (type EXCL) for ResAllocation-PT-R003C015-LTLFireability-15
lola: result : false
lola: markings : 145
lola: fired transitions : 175
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 55 (type EXCL) for 46 ResAllocation-PT-R003C015-LTLFireability-14
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: FINISHED task # 55 (type EXCL) for ResAllocation-PT-R003C015-LTLFireability-14
lola: result : false
lola: markings : 81310
lola: fired transitions : 532667
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 44 (type EXCL) for 43 ResAllocation-PT-R003C015-LTLFireability-13
lola: time limit : 299 sec
lola: memory limit: 32 pages
lola: FINISHED task # 44 (type EXCL) for ResAllocation-PT-R003C015-LTLFireability-13
lola: result : false
lola: markings : 22
lola: fired transitions : 22
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 41 (type EXCL) for 40 ResAllocation-PT-R003C015-LTLFireability-12
lola: time limit : 326 sec
lola: memory limit: 32 pages
lola: FINISHED task # 41 (type EXCL) for ResAllocation-PT-R003C015-LTLFireability-12
lola: result : false
lola: markings : 11
lola: fired transitions : 11
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 38 (type EXCL) for 37 ResAllocation-PT-R003C015-LTLFireability-11
lola: time limit : 359 sec
lola: memory limit: 32 pages
lola: FINISHED task # 38 (type EXCL) for ResAllocation-PT-R003C015-LTLFireability-11
lola: result : false
lola: markings : 5
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 28 (type EXCL) for 27 ResAllocation-PT-R003C015-LTLFireability-09
lola: time limit : 399 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C015-LTLFireability-01: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-10: CONJ false findpath
ResAllocation-PT-R003C015-LTLFireability-11: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-12: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-13: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-14: CONJ false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-15: LTL false LTL model checker

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ResAllocation-PT-R003C015-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-09: LTL 0 0 1 0 1 0 0 0

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28 LTL EXCL 2/399 5/32 ResAllocation-PT-R003C015-LTLFireability-09 768527 m, 153705 m/sec, 5902780 t fired, .

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lola: fired transitions : 8533569
lola: time used : 4.000000
lola: memory pages used : 7
lola: LAUNCH task # 19 (type EXCL) for 18 ResAllocation-PT-R003C015-LTLFireability-06
lola: time limit : 448 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for ResAllocation-PT-R003C015-LTLFireability-06
lola: result : false
lola: markings : 6
lola: fired transitions : 6
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 ResAllocation-PT-R003C015-LTLFireability-03
lola: time limit : 512 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C015-LTLFireability-01: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-06: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-09: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-10: CONJ false findpath
ResAllocation-PT-R003C015-LTLFireability-11: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-12: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-13: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-14: CONJ false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-15: LTL false LTL model checker

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ResAllocation-PT-R003C015-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-08: LTL 0 1 0 0 1 0 0 0

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10 LTL EXCL 3/512 12/32 ResAllocation-PT-R003C015-LTLFireability-03 1763896 m, 352779 m/sec, 6792102 t fired, .

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ResAllocation-PT-R003C015-LTLFireability-06: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-09: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-10: CONJ false findpath
ResAllocation-PT-R003C015-LTLFireability-11: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-12: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-13: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-14: CONJ false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-15: LTL false LTL model checker

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ResAllocation-PT-R003C015-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
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10 LTL EXCL 8/512 25/32 ResAllocation-PT-R003C015-LTLFireability-03 3743779 m, 395976 m/sec, 15442976 t fired, .

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ResAllocation-PT-R003C015-LTLFireability-01: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-06: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-09: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-10: CONJ false findpath
ResAllocation-PT-R003C015-LTLFireability-11: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-12: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-13: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-14: CONJ false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-15: LTL false LTL model checker

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ResAllocation-PT-R003C015-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C015-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-LTLFireability-08: LTL 0 1 0 0 1 0 0 0

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lola: LAUNCH task # 1 (type EXCL) for 0 ResAllocation-PT-R003C015-LTLFireability-00
lola: time limit : 595 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for ResAllocation-PT-R003C015-LTLFireability-00
lola: result : false
lola: markings : 357126
lola: fired transitions : 2486975
lola: time used : 2.000000
lola: memory pages used : 3
lola: LAUNCH task # 16 (type EXCL) for 15 ResAllocation-PT-R003C015-LTLFireability-05
lola: time limit : 714 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for ResAllocation-PT-R003C015-LTLFireability-05
lola: result : false
lola: markings : 16949
lola: fired transitions : 47049
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 ResAllocation-PT-R003C015-LTLFireability-02
lola: time limit : 893 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for ResAllocation-PT-R003C015-LTLFireability-02
lola: result : false
lola: markings : 30
lola: fired transitions : 30
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 24 ResAllocation-PT-R003C015-LTLFireability-08
lola: time limit : 1191 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for ResAllocation-PT-R003C015-LTLFireability-08
lola: result : false
lola: markings : 50
lola: fired transitions : 56
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 ResAllocation-PT-R003C015-LTLFireability-04
lola: time limit : 1786 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C015-LTLFireability-00: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-01: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-02: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-05: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-06: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-08: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-09: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-10: CONJ false findpath
ResAllocation-PT-R003C015-LTLFireability-11: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-12: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-13: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-14: CONJ false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-15: LTL false LTL model checker

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ResAllocation-PT-R003C015-LTLFireability-07: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 LTL EXCL 3/1786 11/32 ResAllocation-PT-R003C015-LTLFireability-04 1686896 m, 337379 m/sec, 6065086 t fired, .

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ResAllocation-PT-R003C015-LTLFireability-00: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-01: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-02: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-05: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-06: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-08: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-09: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-10: CONJ false findpath
ResAllocation-PT-R003C015-LTLFireability-11: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-12: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-13: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-14: CONJ false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-15: LTL false LTL model checker

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13 LTL EXCL 8/1786 25/32 ResAllocation-PT-R003C015-LTLFireability-04 3796465 m, 421913 m/sec, 14195961 t fired, .

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ResAllocation-PT-R003C015-LTLFireability-00: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-01: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-02: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-05: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-06: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-08: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-09: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-10: CONJ false findpath
ResAllocation-PT-R003C015-LTLFireability-11: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-12: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-13: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-14: CONJ false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-15: LTL false LTL model checker

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lola: FINISHED task # 22 (type EXCL) for ResAllocation-PT-R003C015-LTLFireability-07
lola: result : false
lola: markings : 6
lola: fired transitions : 7
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C015-LTLFireability-00: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-01: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-02: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-03: LTL unknown AGGR
ResAllocation-PT-R003C015-LTLFireability-04: LTL unknown AGGR
ResAllocation-PT-R003C015-LTLFireability-05: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-06: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-07: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-08: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-09: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-10: CONJ false findpath
ResAllocation-PT-R003C015-LTLFireability-11: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-12: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-13: LTL false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-14: CONJ false LTL model checker
ResAllocation-PT-R003C015-LTLFireability-15: LTL false LTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ResAllocation-PT-R003C015"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is ResAllocation-PT-R003C015, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r326-tall-167889198700700"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ResAllocation-PT-R003C015.tgz
mv ResAllocation-PT-R003C015 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;