About the Execution of LoLA for ResAllocation-PT-R003C015
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 2713.731 | 205341.00 | 192470.00 | 820.60 | ??FT?TTF?FT?FTFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r326-tall-167889198700698.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is ResAllocation-PT-R003C015, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r326-tall-167889198700698
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 548K
-rw-r--r-- 1 mcc users 6.8K Feb 25 15:20 CTLCardinality.txt
-rw-r--r-- 1 mcc users 68K Feb 25 15:20 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.4K Feb 25 15:19 CTLFireability.txt
-rw-r--r-- 1 mcc users 59K Feb 25 15:19 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 16:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.1K Feb 25 15:21 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 86K Feb 25 15:21 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 15:21 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 92K Feb 25 15:21 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 16:44 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:44 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 9 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 107K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-00
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-01
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-02
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-03
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-04
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-05
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-06
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-07
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-08
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-09
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-10
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-11
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-12
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-13
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-14
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679073332035
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ResAllocation-PT-R003C015
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT ResAllocation-PT-R003C015
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability
FORMULA ResAllocation-PT-R003C015-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R003C015-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R003C015-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R003C015-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R003C015-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R003C015-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R003C015-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R003C015-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R003C015-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R003C015-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R003C015-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679073537376
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:460
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:463
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: LAUNCH task # 1 (type EXCL) for 0 ResAllocation-PT-R003C015-CTLFireability-00
lola: time limit : 120 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C015-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
ResAllocation-PT-R003C015-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-10: DISJ 0 3 0 0 3 0 0 0
ResAllocation-PT-R003C015-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/189 8/32 ResAllocation-PT-R003C015-CTLFireability-00 1679231 m, 335846 m/sec, 9982622 t fired, .
Time elapsed: 5 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C015-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
ResAllocation-PT-R003C015-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-10: DISJ 0 3 0 0 3 0 0 0
ResAllocation-PT-R003C015-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/189 14/32 ResAllocation-PT-R003C015-CTLFireability-00 3271070 m, 318367 m/sec, 20166344 t fired, .
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ResAllocation-PT-R003C015-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
ResAllocation-PT-R003C015-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-10: DISJ 0 3 0 0 3 0 0 0
ResAllocation-PT-R003C015-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/189 21/32 ResAllocation-PT-R003C015-CTLFireability-00 4819527 m, 309691 m/sec, 30079654 t fired, .
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ResAllocation-PT-R003C015-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
ResAllocation-PT-R003C015-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-10: DISJ 0 3 0 0 3 0 0 0
ResAllocation-PT-R003C015-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 20/189 27/32 ResAllocation-PT-R003C015-CTLFireability-00 6269984 m, 290091 m/sec, 39530597 t fired, .
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ResAllocation-PT-R003C015-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C015-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
ResAllocation-PT-R003C015-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-10: DISJ 0 3 0 0 3 0 0 0
ResAllocation-PT-R003C015-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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lola: LAUNCH task # 58 (type EXCL) for 57 ResAllocation-PT-R003C015-CTLFireability-15
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lola: FINISHED task # 58 (type EXCL) for ResAllocation-PT-R003C015-CTLFireability-15
lola: result : false
lola: markings : 241
lola: fired transitions : 284
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 55 (type EXCL) for 54 ResAllocation-PT-R003C015-CTLFireability-14
lola: time limit : 210 sec
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lola: FINISHED task # 55 (type EXCL) for ResAllocation-PT-R003C015-CTLFireability-14
lola: result : false
lola: markings : 21
lola: fired transitions : 21
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 52 (type EXCL) for 51 ResAllocation-PT-R003C015-CTLFireability-13
lola: time limit : 223 sec
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lola: FINISHED task # 52 (type EXCL) for ResAllocation-PT-R003C015-CTLFireability-13
lola: result : true
lola: markings : 569
lola: fired transitions : 616
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 49 (type EXCL) for 48 ResAllocation-PT-R003C015-CTLFireability-12
lola: time limit : 238 sec
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lola: FINISHED task # 49 (type EXCL) for ResAllocation-PT-R003C015-CTLFireability-12
lola: result : false
lola: markings : 618
lola: fired transitions : 3272
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 46 (type EXCL) for 45 ResAllocation-PT-R003C015-CTLFireability-11
lola: time limit : 255 sec
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ResAllocation-PT-R003C015-CTLFireability-12: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-13: CTL true CTL model checker
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ResAllocation-PT-R003C015-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C015-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
ResAllocation-PT-R003C015-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-10: DISJ 0 3 0 0 3 0 0 0
ResAllocation-PT-R003C015-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 5/255 6/32 ResAllocation-PT-R003C015-CTLFireability-11 1356988 m, 271397 m/sec, 10703338 t fired, .
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ResAllocation-PT-R003C015-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C015-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
ResAllocation-PT-R003C015-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-10: DISJ 0 3 0 0 3 0 0 0
ResAllocation-PT-R003C015-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 10/255 11/32 ResAllocation-PT-R003C015-CTLFireability-11 2591086 m, 246819 m/sec, 21223527 t fired, .
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ResAllocation-PT-R003C015-CTLFireability-14: CTL false CTL model checker
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ResAllocation-PT-R003C015-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C015-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
ResAllocation-PT-R003C015-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-10: DISJ 0 3 0 0 3 0 0 0
ResAllocation-PT-R003C015-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
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46 CTL EXCL 15/255 16/32 ResAllocation-PT-R003C015-CTLFireability-11 3645745 m, 210931 m/sec, 30732808 t fired, .
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ResAllocation-PT-R003C015-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
ResAllocation-PT-R003C015-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-10: DISJ 0 3 0 0 3 0 0 0
ResAllocation-PT-R003C015-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
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46 CTL EXCL 20/255 19/32 ResAllocation-PT-R003C015-CTLFireability-11 4494779 m, 169806 m/sec, 39209092 t fired, .
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ResAllocation-PT-R003C015-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C015-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
ResAllocation-PT-R003C015-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-10: DISJ 0 3 0 0 3 0 0 0
ResAllocation-PT-R003C015-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 25/255 24/32 ResAllocation-PT-R003C015-CTLFireability-11 5637551 m, 228554 m/sec, 49508242 t fired, .
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ResAllocation-PT-R003C015-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-14: CTL false CTL model checker
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ResAllocation-PT-R003C015-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C015-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
ResAllocation-PT-R003C015-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-10: DISJ 0 3 0 0 3 0 0 0
ResAllocation-PT-R003C015-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 30/255 28/32 ResAllocation-PT-R003C015-CTLFireability-11 6658673 m, 204224 m/sec, 59391490 t fired, .
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ResAllocation-PT-R003C015-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C015-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
ResAllocation-PT-R003C015-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-10: DISJ 0 3 0 0 3 0 0 0
ResAllocation-PT-R003C015-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 35/255 32/32 ResAllocation-PT-R003C015-CTLFireability-11 7584194 m, 185104 m/sec, 68166338 t fired, .
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ResAllocation-PT-R003C015-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
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ResAllocation-PT-R003C015-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
ResAllocation-PT-R003C015-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-10: DISJ 0 3 0 0 3 0 0 0
ResAllocation-PT-R003C015-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: result : false
lola: markings : 211
lola: fired transitions : 309
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 32 (type EXCL) for 31 ResAllocation-PT-R003C015-CTLFireability-09
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lola: result : false
lola: markings : 193
lola: fired transitions : 254
lola: time used : 0.000000
lola: memory pages used : 1
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C015-CTLFireability-09: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-12: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-13: CTL true CTL model checker
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ResAllocation-PT-R003C015-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C015-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-08: DISJ 0 1 1 0 2 0 0 0
ResAllocation-PT-R003C015-CTLFireability-10: DISJ 0 1 0 0 4 0 0 1
ResAllocation-PT-R003C015-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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ResAllocation-PT-R003C015-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-08: DISJ 0 1 1 0 2 0 0 0
ResAllocation-PT-R003C015-CTLFireability-10: DISJ 0 1 0 0 4 0 0 1
ResAllocation-PT-R003C015-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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ResAllocation-PT-R003C015-CTLFireability-12: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-13: CTL true CTL model checker
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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ResAllocation-PT-R003C015-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-08: DISJ 0 1 1 0 2 0 0 0
ResAllocation-PT-R003C015-CTLFireability-10: DISJ 0 1 0 0 4 0 0 1
ResAllocation-PT-R003C015-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
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ResAllocation-PT-R003C015-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-08: DISJ 0 1 1 0 2 0 0 0
ResAllocation-PT-R003C015-CTLFireability-10: DISJ 0 1 0 0 4 0 0 1
ResAllocation-PT-R003C015-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
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ResAllocation-PT-R003C015-CTLFireability-12: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-13: CTL true CTL model checker
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ResAllocation-PT-R003C015-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-08: DISJ 0 1 0 0 2 0 1 0
ResAllocation-PT-R003C015-CTLFireability-10: DISJ 0 1 0 0 4 0 0 1
ResAllocation-PT-R003C015-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
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lola: result : false
lola: markings : 15
lola: fired transitions : 14
lola: time used : 0.000000
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lola: result : false
lola: markings : 20024
lola: fired transitions : 82557
lola: time used : 0.000000
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lola: result : true
lola: markings : 60
lola: fired transitions : 243
lola: time used : 0.000000
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ResAllocation-PT-R003C015-CTLFireability-06: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-09: CTL false CTL model checker
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ResAllocation-PT-R003C015-CTLFireability-14: CTL false CTL model checker
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ResAllocation-PT-R003C015-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-08: DISJ 0 0 0 0 3 0 1 0
ResAllocation-PT-R003C015-CTLFireability-10: DISJ 0 1 0 0 4 0 0 1
ResAllocation-PT-R003C015-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/585 4/32 ResAllocation-PT-R003C015-CTLFireability-01 724759 m, 144951 m/sec, 9332217 t fired, .
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ResAllocation-PT-R003C015-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-08: DISJ 0 0 0 0 3 0 1 0
ResAllocation-PT-R003C015-CTLFireability-10: DISJ 0 1 0 0 4 0 0 1
ResAllocation-PT-R003C015-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/585 6/32 ResAllocation-PT-R003C015-CTLFireability-01 1407396 m, 136527 m/sec, 18530512 t fired, .
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ResAllocation-PT-R003C015-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C015-CTLFireability-08: DISJ 0 0 0 0 3 0 1 0
ResAllocation-PT-R003C015-CTLFireability-10: DISJ 0 1 0 0 4 0 0 1
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ResAllocation-PT-R003C015-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C015-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C015-CTLFireability-08: DISJ 0 0 0 0 3 0 1 0
ResAllocation-PT-R003C015-CTLFireability-10: DISJ 0 1 0 0 4 0 0 1
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ResAllocation-PT-R003C015-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C015-CTLFireability-08: DISJ 0 0 0 0 3 0 1 0
ResAllocation-PT-R003C015-CTLFireability-10: DISJ 0 1 0 0 4 0 0 1
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ResAllocation-PT-R003C015-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C015-CTLFireability-08: DISJ 0 0 0 0 3 0 1 0
ResAllocation-PT-R003C015-CTLFireability-10: DISJ 0 1 0 0 4 0 0 1
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ResAllocation-PT-R003C015-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-08: DISJ 0 0 0 0 3 0 1 0
ResAllocation-PT-R003C015-CTLFireability-10: DISJ 0 1 0 0 4 0 0 1
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ResAllocation-PT-R003C015-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C015-CTLFireability-08: DISJ 0 0 0 0 3 0 1 0
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ResAllocation-PT-R003C015-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C015-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C015-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C015-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-08: DISJ 0 0 0 0 3 0 1 0
ResAllocation-PT-R003C015-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 40/3445 29/32 ResAllocation-PT-R003C015-CTLFireability-04 6738706 m, 157882 m/sec, 96924544 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C015-CTLFireability-02: AGEF false tscc_search
ResAllocation-PT-R003C015-CTLFireability-03: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-05: EFAG true tscc_search
ResAllocation-PT-R003C015-CTLFireability-06: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-09: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-10: DISJ true tscc_search
ResAllocation-PT-R003C015-CTLFireability-12: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C015-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C015-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C015-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-08: DISJ 0 0 0 0 3 0 1 0
ResAllocation-PT-R003C015-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 45/3445 32/32 ResAllocation-PT-R003C015-CTLFireability-04 7599389 m, 172136 m/sec, 108871375 t fired, .
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lola: CANCELED task # 13 (type EXCL) for ResAllocation-PT-R003C015-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C015-CTLFireability-02: AGEF false tscc_search
ResAllocation-PT-R003C015-CTLFireability-03: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-05: EFAG true tscc_search
ResAllocation-PT-R003C015-CTLFireability-06: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-09: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-10: DISJ true tscc_search
ResAllocation-PT-R003C015-CTLFireability-12: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C015-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C015-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C015-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C015-CTLFireability-08: DISJ 0 0 0 0 3 0 1 0
ResAllocation-PT-R003C015-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C015-CTLFireability-00: CTL unknown AGGR
ResAllocation-PT-R003C015-CTLFireability-01: CTL unknown AGGR
ResAllocation-PT-R003C015-CTLFireability-02: AGEF false tscc_search
ResAllocation-PT-R003C015-CTLFireability-03: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-04: CTL unknown AGGR
ResAllocation-PT-R003C015-CTLFireability-05: EFAG true tscc_search
ResAllocation-PT-R003C015-CTLFireability-06: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-08: DISJ unknown DISJ
ResAllocation-PT-R003C015-CTLFireability-09: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-10: DISJ true tscc_search
ResAllocation-PT-R003C015-CTLFireability-11: CTL unknown AGGR
ResAllocation-PT-R003C015-CTLFireability-12: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-13: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-15: CTL false CTL model checker
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ResAllocation-PT-R003C015"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is ResAllocation-PT-R003C015, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r326-tall-167889198700698"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ResAllocation-PT-R003C015.tgz
mv ResAllocation-PT-R003C015 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;