Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r326-tall-167889198300372.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is Railroad-PT-010, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r326-tall-167889198300372
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 604K
-rw-r--r-- 1 mcc users 9.0K Feb 25 22:26 CTLCardinality.txt
-rw-r--r-- 1 mcc users 98K Feb 25 22:26 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.9K Feb 25 22:25 CTLFireability.txt
-rw-r--r-- 1 mcc users 47K Feb 25 22:25 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.2K Feb 25 16:41 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:41 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 16:41 LTLFireability.txt
-rw-r--r-- 1 mcc users 14K Feb 25 16:41 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Feb 25 22:27 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 148K Feb 25 22:27 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 22:27 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 81K Feb 25 22:27 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:41 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:41 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 82K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Railroad-PT-010-LTLFireability-00
FORMULA_NAME Railroad-PT-010-LTLFireability-01
FORMULA_NAME Railroad-PT-010-LTLFireability-02
FORMULA_NAME Railroad-PT-010-LTLFireability-03
FORMULA_NAME Railroad-PT-010-LTLFireability-04
FORMULA_NAME Railroad-PT-010-LTLFireability-05
FORMULA_NAME Railroad-PT-010-LTLFireability-06
FORMULA_NAME Railroad-PT-010-LTLFireability-07
FORMULA_NAME Railroad-PT-010-LTLFireability-08
FORMULA_NAME Railroad-PT-010-LTLFireability-09
FORMULA_NAME Railroad-PT-010-LTLFireability-10
FORMULA_NAME Railroad-PT-010-LTLFireability-11
FORMULA_NAME Railroad-PT-010-LTLFireability-12
FORMULA_NAME Railroad-PT-010-LTLFireability-13
FORMULA_NAME Railroad-PT-010-LTLFireability-14
FORMULA_NAME Railroad-PT-010-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1679040156016

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=LTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Railroad-PT-010
Not applying reductions.
Model is PT
LTLFireability PT
starting LoLA
BK_INPUT Railroad-PT-010
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
LTLFireability

FORMULA Railroad-PT-010-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-010-LTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-010-LTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-010-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-010-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-010-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-010-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-010-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-010-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-010-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-010-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-010-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-010-LTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-010-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-010-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-010-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679040191548

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/LTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:144
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:373
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:518
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 10 transitions removed,31 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 10 (type CNST) for 9 Railroad-PT-010-LTLFireability-03
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 10 (type CNST) for Railroad-PT-010-LTLFireability-03
lola: result : false
lola: LAUNCH task # 4 (type EXCL) for 3 Railroad-PT-010-LTLFireability-01
lola: time limit : 144 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 40 (type CNST) for 37 Railroad-PT-010-LTLFireability-11
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 40 (type CNST) for Railroad-PT-010-LTLFireability-11
lola: result : true
lola: FINISHED task # 4 (type EXCL) for Railroad-PT-010-LTLFireability-01
lola: result : true
lola: markings : 11
lola: fired transitions : 10
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 16 (type EXCL) for 15 Railroad-PT-010-LTLFireability-05
lola: time limit : 180 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for Railroad-PT-010-LTLFireability-05
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 Railroad-PT-010-LTLFireability-00
lola: time limit : 200 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for Railroad-PT-010-LTLFireability-00
lola: result : false
lola: markings : 19
lola: fired transitions : 19
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 54 (type EXCL) for 53 Railroad-PT-010-LTLFireability-15
lola: time limit : 225 sec
lola: memory limit: 32 pages
lola: FINISHED task # 54 (type EXCL) for Railroad-PT-010-LTLFireability-15
lola: result : false
lola: markings : 17
lola: fired transitions : 20
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 59 (type EXCL) for 6 Railroad-PT-010-LTLFireability-02
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 59 (type EXCL) for Railroad-PT-010-LTLFireability-02
lola: result : true
lola: markings : 19
lola: fired transitions : 19
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 37 Railroad-PT-010-LTLFireability-11
lola: time limit : 300 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 62 (type SKEL/FNDP) for 50 Railroad-PT-010-LTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 63 (type SKEL/EQUN) for 50 Railroad-PT-010-LTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 64 (type SKEL/SRCH) for 50 Railroad-PT-010-LTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: FINISHED task # 62 (type SKEL/FNDP) for Railroad-PT-010-LTLFireability-14
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 63 (type EQUN) for Railroad-PT-010-LTLFireability-14 (obsolete)
lola: CANCELED task # 64 (type SRCH) for Railroad-PT-010-LTLFireability-14 (obsolete)
lola: LAUNCH task # 69 (type FNDP) for 21 Railroad-PT-010-LTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 70 (type EQUN) for 21 Railroad-PT-010-LTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 72 (type SRCH) for 21 Railroad-PT-010-LTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 64 (type SKEL/SRCH) for Railroad-PT-010-LTLFireability-14
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 69 (type FNDP) for Railroad-PT-010-LTLFireability-07
lola: result : true
lola: fired transitions : 24
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 70 (type EQUN) for Railroad-PT-010-LTLFireability-07 (obsolete)
lola: CANCELED task # 72 (type SRCH) for Railroad-PT-010-LTLFireability-07 (obsolete)
lola: LAUNCH task # 57 (type FNDP) for 44 Railroad-PT-010-LTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 58 (type EQUN) for 44 Railroad-PT-010-LTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: LAUNCH task # 67 (type SRCH) for 44 Railroad-PT-010-LTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 57 (type FNDP) for Railroad-PT-010-LTLFireability-12
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 58 (type EQUN) for Railroad-PT-010-LTLFireability-12 (obsolete)
lola: CANCELED task # 67 (type SRCH) for Railroad-PT-010-LTLFireability-12 (obsolete)
lola: LAUNCH task # 74 (type FNDP) for 50 Railroad-PT-010-LTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 75 (type EQUN) for 50 Railroad-PT-010-LTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 77 (type SRCH) for 50 Railroad-PT-010-LTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 72 (type SRCH) for Railroad-PT-010-LTLFireability-07
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
sara: try reading problem file /home/mcc/execution/LTLFireability-63.sara.
sara: try reading problem file /home/mcc/execution/LTLFireability-70.sara.
lola: FINISHED task # 77 (type SRCH) for Railroad-PT-010-LTLFireability-14
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1

lola: FINISHED task # 63 (type SKEL/EQUN) for Railroad-PT-010-LTLFireability-14
lola: result : true
lola: FINISHED task # 42 (type EXCL) for Railroad-PT-010-LTLFireability-11
lola: result : false
lola: markings : 5673
lola: fired transitions : 15570
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 48 (type EXCL) for 47 Railroad-PT-010-LTLFireability-13
lola: time limit : 514 sec
lola: memory limit: 32 pages
lola: FINISHED task # 48 (type EXCL) for Railroad-PT-010-LTLFireability-13
lola: result : false
lola: markings : 12
lola: fired transitions : 12
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 35 (type EXCL) for 34 Railroad-PT-010-LTLFireability-10
lola: time limit : 600 sec
lola: memory limit: 32 pages
sara: try reading problem file /home/mcc/execution/LTLFireability-75.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 74 (type FNDP) for Railroad-PT-010-LTLFireability-14
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 75 (type EQUN) for Railroad-PT-010-LTLFireability-14 (obsolete)
lola: FINISHED task # 67 (type SRCH) for Railroad-PT-010-LTLFireability-12
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 75 (type EQUN) for Railroad-PT-010-LTLFireability-14
lola: result : unknown
sara: try reading problem file /home/mcc/execution/LTLFireability-58.sara.
lola: FINISHED task # 35 (type EXCL) for Railroad-PT-010-LTLFireability-10
lola: result : false

lola: markings : 1700
lola: fired transitions : 4525
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 32 (type EXCL) for 31 Railroad-PT-010-LTLFireability-09
lola: time limit : 900 sec
lola: memory limit: 32 pages
lola: FINISHED task # 70 (type EQUN) for Railroad-PT-010-LTLFireability-07
lola: result : true
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 58 (type EQUN) for Railroad-PT-010-LTLFireability-12
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Railroad-PT-010-LTLFireability-00: LTL false LTL model checker
Railroad-PT-010-LTLFireability-01: LTL true LTL model checker
Railroad-PT-010-LTLFireability-02: F false state space / EG
Railroad-PT-010-LTLFireability-03: INITIAL false preprocessing
Railroad-PT-010-LTLFireability-05: LTL true LTL model checker
Railroad-PT-010-LTLFireability-07: CONJ false findpath
Railroad-PT-010-LTLFireability-10: LTL false LTL model checker
Railroad-PT-010-LTLFireability-11: CONJ false LTL model checker
Railroad-PT-010-LTLFireability-12: AG false findpath
Railroad-PT-010-LTLFireability-13: LTL false LTL model checker
Railroad-PT-010-LTLFireability-14: AG false findpath
Railroad-PT-010-LTLFireability-15: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Railroad-PT-010-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
Railroad-PT-010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
Railroad-PT-010-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
Railroad-PT-010-LTLFireability-09: LTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 LTL EXCL 5/900 9/32 Railroad-PT-010-LTLFireability-09 1335953 m, 267190 m/sec, 7963041 t fired, .

Time elapsed: 5 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Railroad-PT-010-LTLFireability-00: LTL false LTL model checker
Railroad-PT-010-LTLFireability-01: LTL true LTL model checker
Railroad-PT-010-LTLFireability-02: F false state space / EG
Railroad-PT-010-LTLFireability-03: INITIAL false preprocessing
Railroad-PT-010-LTLFireability-05: LTL true LTL model checker
Railroad-PT-010-LTLFireability-07: CONJ false findpath
Railroad-PT-010-LTLFireability-10: LTL false LTL model checker
Railroad-PT-010-LTLFireability-11: CONJ false LTL model checker
Railroad-PT-010-LTLFireability-12: AG false findpath
Railroad-PT-010-LTLFireability-13: LTL false LTL model checker
Railroad-PT-010-LTLFireability-14: AG false findpath
Railroad-PT-010-LTLFireability-15: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Railroad-PT-010-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
Railroad-PT-010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
Railroad-PT-010-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
Railroad-PT-010-LTLFireability-09: LTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 LTL EXCL 10/900 15/32 Railroad-PT-010-LTLFireability-09 2341639 m, 201137 m/sec, 14697789 t fired, .

Time elapsed: 10 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Railroad-PT-010-LTLFireability-00: LTL false LTL model checker
Railroad-PT-010-LTLFireability-01: LTL true LTL model checker
Railroad-PT-010-LTLFireability-02: F false state space / EG
Railroad-PT-010-LTLFireability-03: INITIAL false preprocessing
Railroad-PT-010-LTLFireability-05: LTL true LTL model checker
Railroad-PT-010-LTLFireability-07: CONJ false findpath
Railroad-PT-010-LTLFireability-10: LTL false LTL model checker
Railroad-PT-010-LTLFireability-11: CONJ false LTL model checker
Railroad-PT-010-LTLFireability-12: AG false findpath
Railroad-PT-010-LTLFireability-13: LTL false LTL model checker
Railroad-PT-010-LTLFireability-14: AG false findpath
Railroad-PT-010-LTLFireability-15: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Railroad-PT-010-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
Railroad-PT-010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
Railroad-PT-010-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
Railroad-PT-010-LTLFireability-09: LTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 LTL EXCL 15/900 22/32 Railroad-PT-010-LTLFireability-09 3303211 m, 192314 m/sec, 20321537 t fired, .

Time elapsed: 15 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Railroad-PT-010-LTLFireability-00: LTL false LTL model checker
Railroad-PT-010-LTLFireability-01: LTL true LTL model checker
Railroad-PT-010-LTLFireability-02: F false state space / EG
Railroad-PT-010-LTLFireability-03: INITIAL false preprocessing
Railroad-PT-010-LTLFireability-05: LTL true LTL model checker
Railroad-PT-010-LTLFireability-07: CONJ false findpath
Railroad-PT-010-LTLFireability-10: LTL false LTL model checker
Railroad-PT-010-LTLFireability-11: CONJ false LTL model checker
Railroad-PT-010-LTLFireability-12: AG false findpath
Railroad-PT-010-LTLFireability-13: LTL false LTL model checker
Railroad-PT-010-LTLFireability-14: AG false findpath
Railroad-PT-010-LTLFireability-15: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Railroad-PT-010-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
Railroad-PT-010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
Railroad-PT-010-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
Railroad-PT-010-LTLFireability-09: LTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 LTL EXCL 20/900 27/32 Railroad-PT-010-LTLFireability-09 4173538 m, 174065 m/sec, 25737139 t fired, .

Time elapsed: 20 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Railroad-PT-010-LTLFireability-00: LTL false LTL model checker
Railroad-PT-010-LTLFireability-01: LTL true LTL model checker
Railroad-PT-010-LTLFireability-02: F false state space / EG
Railroad-PT-010-LTLFireability-03: INITIAL false preprocessing
Railroad-PT-010-LTLFireability-05: LTL true LTL model checker
Railroad-PT-010-LTLFireability-07: CONJ false findpath
Railroad-PT-010-LTLFireability-10: LTL false LTL model checker
Railroad-PT-010-LTLFireability-11: CONJ false LTL model checker
Railroad-PT-010-LTLFireability-12: AG false findpath
Railroad-PT-010-LTLFireability-13: LTL false LTL model checker
Railroad-PT-010-LTLFireability-14: AG false findpath
Railroad-PT-010-LTLFireability-15: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Railroad-PT-010-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
Railroad-PT-010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
Railroad-PT-010-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
Railroad-PT-010-LTLFireability-09: LTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 LTL EXCL 25/900 32/32 Railroad-PT-010-LTLFireability-09 4838932 m, 133078 m/sec, 31360258 t fired, .

Time elapsed: 25 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Railroad-PT-010-LTLFireability-00: LTL false LTL model checker
Railroad-PT-010-LTLFireability-01: LTL true LTL model checker
Railroad-PT-010-LTLFireability-02: F false state space / EG
Railroad-PT-010-LTLFireability-03: INITIAL false preprocessing
Railroad-PT-010-LTLFireability-05: LTL true LTL model checker
Railroad-PT-010-LTLFireability-07: CONJ false findpath
Railroad-PT-010-LTLFireability-10: LTL false LTL model checker
Railroad-PT-010-LTLFireability-11: CONJ false LTL model checker
Railroad-PT-010-LTLFireability-12: AG false findpath
Railroad-PT-010-LTLFireability-13: LTL false LTL model checker
Railroad-PT-010-LTLFireability-14: AG false findpath
Railroad-PT-010-LTLFireability-15: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Railroad-PT-010-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
Railroad-PT-010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
Railroad-PT-010-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
Railroad-PT-010-LTLFireability-09: LTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 LTL EXCL 30/900 32/32 Railroad-PT-010-LTLFireability-09 4842991 m, 811 m/sec, 36618170 t fired, .

Time elapsed: 30 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Railroad-PT-010-LTLFireability-00: LTL false LTL model checker
Railroad-PT-010-LTLFireability-01: LTL true LTL model checker
Railroad-PT-010-LTLFireability-02: F false state space / EG
Railroad-PT-010-LTLFireability-03: INITIAL false preprocessing
Railroad-PT-010-LTLFireability-05: LTL true LTL model checker
Railroad-PT-010-LTLFireability-07: CONJ false findpath
Railroad-PT-010-LTLFireability-10: LTL false LTL model checker
Railroad-PT-010-LTLFireability-11: CONJ false LTL model checker
Railroad-PT-010-LTLFireability-12: AG false findpath
Railroad-PT-010-LTLFireability-13: LTL false LTL model checker
Railroad-PT-010-LTLFireability-14: AG false findpath
Railroad-PT-010-LTLFireability-15: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Railroad-PT-010-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
Railroad-PT-010-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
Railroad-PT-010-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
Railroad-PT-010-LTLFireability-09: LTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 LTL EXCL 35/900 32/32 Railroad-PT-010-LTLFireability-09 4843114 m, 24 m/sec, 42348385 t fired, .

Time elapsed: 35 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 32 (type EXCL) for Railroad-PT-010-LTLFireability-09
lola: result : true
lola: markings : 4843114
lola: fired transitions : 42862932
lola: time used : 35.000000
lola: memory pages used : 32
lola: LAUNCH task # 19 (type EXCL) for 18 Railroad-PT-010-LTLFireability-06
lola: time limit : 1188 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for Railroad-PT-010-LTLFireability-06
lola: result : false
lola: markings : 82
lola: fired transitions : 150
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 29 (type EXCL) for 28 Railroad-PT-010-LTLFireability-08
lola: time limit : 1782 sec
lola: memory limit: 32 pages
lola: FINISHED task # 29 (type EXCL) for Railroad-PT-010-LTLFireability-08
lola: result : false
lola: markings : 67
lola: fired transitions : 104
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 Railroad-PT-010-LTLFireability-04
lola: time limit : 3565 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for Railroad-PT-010-LTLFireability-04
lola: result : false
lola: markings : 11
lola: fired transitions : 11
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Railroad-PT-010-LTLFireability-00: LTL false LTL model checker
Railroad-PT-010-LTLFireability-01: LTL true LTL model checker
Railroad-PT-010-LTLFireability-02: F false state space / EG
Railroad-PT-010-LTLFireability-03: INITIAL false preprocessing
Railroad-PT-010-LTLFireability-04: LTL false LTL model checker
Railroad-PT-010-LTLFireability-05: LTL true LTL model checker
Railroad-PT-010-LTLFireability-06: LTL false LTL model checker
Railroad-PT-010-LTLFireability-07: CONJ false findpath
Railroad-PT-010-LTLFireability-08: LTL false LTL model checker
Railroad-PT-010-LTLFireability-09: LTL true LTL model checker
Railroad-PT-010-LTLFireability-10: LTL false LTL model checker
Railroad-PT-010-LTLFireability-11: CONJ false LTL model checker
Railroad-PT-010-LTLFireability-12: AG false findpath
Railroad-PT-010-LTLFireability-13: LTL false LTL model checker
Railroad-PT-010-LTLFireability-14: AG false findpath
Railroad-PT-010-LTLFireability-15: LTL false LTL model checker


Time elapsed: 35 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Railroad-PT-010"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is Railroad-PT-010, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r326-tall-167889198300372"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/Railroad-PT-010.tgz
mv Railroad-PT-010 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;