MCC'2023- Execution of r326-tall-167889198100234

About the Execution of LoLA for RERS2020-PT-pb103

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
16212.279	547334.00	4831605.00	17825.40	?????T??????????	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r3
Waiting for the VM to be ready
....................................
==============
Generated by BenchKit 2-5348
Executing tool lola
Input is RERS2020-PT-pb103,
Time confinement is 3600 seconds
Memory confinement is 16384
Number of cores is 4
Run identifier is r326-tall-1678
====================================

--------------------
preparation of the directory
/home/mcc/execution
total 18M
-rw-r--r-- 1 mcc users 7.2K
-rw-r--r-- 1 mcc users 75K
-rw-r--r-- 1 mcc users 6.0K
-rw-r--r-- 1 mcc users 51K
-rw-r--r-- 1 mcc users 3.8K
-rw-r--r-- 1 mcc users 27K
-rw-r--r-- 1 mcc users 2.5K
-rw-r--r-- 1 mcc users 17K
-rw-r--r-- 1 mcc users 13K
-rw-r--r-- 1 mcc users 130K
-rw-r--r-- 1 mcc users 8.8K
-rw-r--r-- 1 mcc users 64K
-rw-r--r-- 1 mcc users 1.6K
-rw-r--r-- 1 mcc users 3.7K
-rw-r--r-- 1 mcc users 6 Mar
-rw-r--r-- 1 mcc users 6 Mar
-rw-r--r-- 1 mcc users 6 Mar
-rw-r--r-- 1 mcc users 18M Mar

--------------------
content from stdout:

=== Data for post analysis

The expected result is a vector
BOOL_VECTOR

here is the order used to build
FORMULA_NAME RERS2020-PT-pb103-CTLFi
FORMULA_NAME RERS2020-PT-pb103-CTLFi
FORMULA_NAME RERS2020-PT-pb103-CTLFi
FORMULA_NAME RERS2020-PT-pb103-CTLFi
FORMULA_NAME RERS2020-PT-pb103-CTLFi
FORMULA_NAME RERS2020-PT-pb103-CTLFi
FORMULA_NAME RERS2020-PT-pb103-CTLFi
FORMULA_NAME RERS2020-PT-pb103-CTLFi
FORMULA_NAME RERS2020-PT-pb103-CTLFi
FORMULA_NAME RERS2020-PT-pb103-CTLFi
FORMULA_NAME RERS2020-PT-pb103-CTLFi
FORMULA_NAME RERS2020-PT-pb103-CTLFi
FORMULA_NAME RERS2020-PT-pb103-CTLFi
FORMULA_NAME RERS2020-PT-pb103-CTLFi
FORMULA_NAME RERS2020-PT-pb103-CTLFi
FORMULA_NAME RERS2020-PT-pb103-CTLFi

=== Now, execution of the tool

BK_START 1679014513061

bash -c /home/mcc/BenchKit/BenchKit_head.sh
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RERS2020-PT-pb103
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT RERS2020-PT-pb103
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bi
current directory: /home/mcc/executi
CTLFireability

FORMULA RERS2020-PT-pb103-CTLFireability-05

BK_STOP 1679015060395
TIME LIMIT: Killed by timeout
MemTotal: 16393232 kB
MemFree: 6420724 kB
After kill :
MemTotal: 16393232 kB
MemFree: 6419960 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/e
lola: reading pnml
lola: PNML file contains
lola: finished parsing
lola: closed net file /home/mcc/ex
lola: Reading formula.
lola: Using XML format (--xmlformu
lola: reading XML formula
lola: reading formula from
lola: rewrite Frontend/Parser/form
lola: rewrite Frontend/Parser/form
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lola: RELEASE
lola: RELEASE
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======================================================= examination is CTLFireability MBytes 89198100234 ================================= to be used: Feb 26 08:33 CTLCardinality.txt Feb 26 08:33 CTLCardinality.xml Feb 26 08:31 CTLFireability.txt Feb 26 08:31 CTLFireability.xml Feb 25 16:40 LTLCardinality.txt Feb 25 16:40 LTLCardinality.xml Feb 25 16:40 LTLFireability.txt Feb 25 16:40 LTLFireability.xml Feb 26 08:36 ReachabilityCardinality.txt Feb 26 08:36 ReachabilityCardinality.xml Feb 26 08:35 ReachabilityFireability.txt Feb 26 08:35 ReachabilityFireability.xml Feb 25 16:40 UpperBounds.txt Feb 25 16:40 UpperBounds.xml 5 18:23 equiv_col 5 18:23 instance 5 18:23 iscolored 5 18:23 model.pnml generated by BenchKit (invocation template) of booleans the result vector(from text file) reability-00 reability-01 reability-02 reability-03 reability-04 reability-05 reability-06 reability-07 reability-08 reability-09 reability-10 reability-11 reability-12 reability-13 reability-14 reability-15 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VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 AG 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 EG 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 0 4.000000 secs. VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 AG 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 EG 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 0 5.000000 secs. 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VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 EG 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 0 7.000000 secs. ula_rewrite.k:807 ula_rewrite.k:807 ula_rewrite.k:807 ula_rewrite.k:807 ula_rewrite.k:807 ula_rewrite.k:806 ula_rewrite.k:814 ula_rewrite.k:813 ula_rewrite.k:811 ula_rewrite.k:809 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 EG 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 1 0 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 0 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 EG 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 1 0 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 0 ula_rewrite.k:813 ula_rewrite.k:809 ula_rewrite.k:811 EXCL) for 45 RERS2020-PT-pb103-CTLFireability-15 ula_rewrite.k:812 ula_rewrite.k:810 ula_rewrite.k:809 ula_rewrite.k:815 ula_rewrite.k:811 ula_rewrite.k:806 ula_rewrite.k:808 ula_rewrite.k:813 ula_rewrite.k:811 ula_rewrite.k:807 ula_rewrite.k:814 ula_rewrite.k:813 ula_rewrite.k:814 ula_rewrite.k:808 ula_rewrite.k:811 ula_rewrite.k:809 ula_rewrite.k:721 ula_rewrite.k:788 ula_rewrite.k:813 ula_rewrite.k:815 ula_rewrite.k:810 ula_rewrite.k:807 ula_rewrite.k:808 ula_rewrite.k:814 ula_rewrite.k:809 ula_rewrite.k:811 ula_rewrite.k:809 ula_rewrite.k:721 ula_rewrite.k:788 ula_rewrite.k:721 ula_rewrite.k:788 FNDP) for 21 RERS2020-PT-pb103-CTLFireability-07 EQUN) for 21 RERS2020-PT-pb103-CTLFireability-07 SRCH) for 21 RERS2020-PT-pb103-CTLFireability-07 ula_rewrite.k:807 ula_rewrite.k:813 ula_rewrite.k:812 ula_rewrite.k:808 (type SRCH) for RERS2020-PT-pb103-CTLFireability-07 : unknown 0.000000 1 ula_rewrite.k:721 ula_rewrite.k:788 ula_rewrite.k:808 ula_rewrite.k:814 ula_rewrite.k:814 ula_rewrite.k:813 ula_rewrite.k:813 ula_rewrite.k:812 ula_rewrite.k:811 ula_rewrite.k:814 ula_rewrite.k:812 ula_rewrite.k:815 ula_rewrite.k:812 ula_rewrite.k:806 ula_rewrite.k:807 ula_rewrite.k:812 ula_rewrite.k:807 ula_rewrite.k:810 ula_rewrite.k:809 ula_rewrite.k:808 ula_rewrite.k:808 /home/mcc/execution/CTLFireability-50.sara. VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 RERS2020-PT-pb103-CTLFireability-15 19866 m, 3973 m/sec, 138686 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 516 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 2 ula_rewrite.k:809 ula_rewrite.k:813 ula_rewrite.k:808 ula_rewrite.k:806 ula_rewrite.k:812 ula_rewrite.k:814 ula_rewrite.k:809 ula_rewrite.k:814 ula_rewrite.k:812 ula_rewrite.k:811 ula_rewrite.k:811 ula_rewrite.k:811 ula_rewrite.k:815 ula_rewrite.k:811 ula_rewrite.k:812 ula_rewrite.k:814 ula_rewrite.k:814 ula_rewrite.k:813 ula_rewrite.k:812 ula_rewrite.k:811 ula_rewrite.k:809 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 RERS2020-PT-pb103-CTLFireability-15 43933 m, 4813 m/sec, 312116 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 1494 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 2 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 RERS2020-PT-pb103-CTLFireability-15 84553 m, 8124 m/sec, 611399 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 2078 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 2 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 RERS2020-PT-pb103-CTLFireability-15 125133 m, 8116 m/sec, 917485 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 3172 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 2 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 RERS2020-PT-pb103-CTLFireability-15 164334 m, 7840 m/sec, 1214459 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 4821 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 2 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 RERS2020-PT-pb103-CTLFireability-15 202938 m, 7720 m/sec, 1511522 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 6528 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 2 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 RERS2020-PT-pb103-CTLFireability-15 242778 m, 7968 m/sec, 1820665 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 8296 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 2 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 RERS2020-PT-pb103-CTLFireability-15 264673 m, 4379 m/sec, 1991639 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 9963 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 2 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 RERS2020-PT-pb103-CTLFireability-15 284166 m, 3898 m/sec, 2144957 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 11531 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 2 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 RERS2020-PT-pb103-CTLFireability-15 303646 m, 3896 m/sec, 2297729 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 13252 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 2 is non-deterministic VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 RERS2020-PT-pb103-CTLFireability-15 333235 m, 5917 m/sec, 2531396 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 14949 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 2 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 RERS2020-PT-pb103-CTLFireability-15 367843 m, 6921 m/sec, 2806849 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 16520 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 2 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 RERS2020-PT-pb103-CTLFireability-15 405469 m, 7525 m/sec, 3106711 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 18220 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 2 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 RERS2020-PT-pb103-CTLFireability-15 443830 m, 7672 m/sec, 3414906 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 19949 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 2 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 RERS2020-PT-pb103-CTLFireability-15 482381 m, 7710 m/sec, 3726799 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 21614 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 3 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 RERS2020-PT-pb103-CTLFireability-15 512312 m, 5986 m/sec, 3969705 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 22337 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 3 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 RERS2020-PT-pb103-CTLFireability-15 546343 m, 6806 m/sec, 4246807 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 23805 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 3 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 RERS2020-PT-pb103-CTLFireability-15 584575 m, 7646 m/sec, 4558606 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 25403 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 3 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 RERS2020-PT-pb103-CTLFireability-15 622702 m, 7625 m/sec, 4873045 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 26998 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 3 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 RERS2020-PT-pb103-CTLFireability-15 660901 m, 7639 m/sec, 5187781 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 28573 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 3 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 RERS2020-PT-pb103-CTLFireability-15 698266 m, 7473 m/sec, 5497267 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 29841 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 4 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 RERS2020-PT-pb103-CTLFireability-15 736919 m, 7730 m/sec, 5819510 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 31531 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 4 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 RERS2020-PT-pb103-CTLFireability-15 768838 m, 6383 m/sec, 6087283 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 33268 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 4 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 RERS2020-PT-pb103-CTLFireability-15 807679 m, 7768 m/sec, 6412093 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 35040 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 4 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 RERS2020-PT-pb103-CTLFireability-15 845634 m, 7591 m/sec, 6732988 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 36622 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 4 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 RERS2020-PT-pb103-CTLFireability-15 883311 m, 7535 m/sec, 7052292 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 38226 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 4 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 RERS2020-PT-pb103-CTLFireability-15 921254 m, 7588 m/sec, 7375880 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 39957 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 5 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 RERS2020-PT-pb103-CTLFireability-15 958723 m, 7493 m/sec, 7696523 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 41711 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 5 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 RERS2020-PT-pb103-CTLFireability-15 996162 m, 7487 m/sec, 8018998 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 43426 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 5 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 RERS2020-PT-pb103-CTLFireability-15 1024869 m, 5741 m/sec, 8267441 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 44716 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 5 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 RERS2020-PT-pb103-CTLFireability-15 1053674 m, 5761 m/sec, 8517690 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 45965 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 5 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 RERS2020-PT-pb103-CTLFireability-15 1091412 m, 7547 m/sec, 8846408 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 47495 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 5 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 RERS2020-PT-pb103-CTLFireability-15 1129091 m, 7535 m/sec, 9175915 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 49221 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 5 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 RERS2020-PT-pb103-CTLFireability-15 1166535 m, 7488 m/sec, 9504313 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 50596 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 6 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 RERS2020-PT-pb103-CTLFireability-15 1184723 m, 3637 m/sec, 9664649 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 52251 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 6 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 RERS2020-PT-pb103-CTLFireability-15 1205511 m, 4157 m/sec, 9848790 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 54018 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 6 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 RERS2020-PT-pb103-CTLFireability-15 1239878 m, 6873 m/sec, 10154806 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 55728 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 6 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 RERS2020-PT-pb103-CTLFireability-15 1274786 m, 6981 m/sec, 10467048 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 57436 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 6 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 RERS2020-PT-pb103-CTLFireability-15 1304074 m, 5857 m/sec, 10729216 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 59075 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 6 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 RERS2020-PT-pb103-CTLFireability-15 1341122 m, 7409 m/sec, 11064367 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 60793 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 6 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 RERS2020-PT-pb103-CTLFireability-15 1376517 m, 7079 m/sec, 11386617 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 62517 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 7 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 RERS2020-PT-pb103-CTLFireability-15 1412862 m, 7269 m/sec, 11721567 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 64284 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 7 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 RERS2020-PT-pb103-CTLFireability-15 1449540 m, 7335 m/sec, 12060822 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 65765 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 7 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 RERS2020-PT-pb103-CTLFireability-15 1484693 m, 7030 m/sec, 12388658 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 67401 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 7 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 RERS2020-PT-pb103-CTLFireability-15 1521160 m, 7293 m/sec, 12731063 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 69011 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 7 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 RERS2020-PT-pb103-CTLFireability-15 1553474 m, 6462 m/sec, 13036809 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 70658 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 7 (type EXCL) for RERS2020-PT-pb103-CTLFireability-15 (local timeout) VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 1 0 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 RERS2020-PT-pb103-CTLFireability-07 72431 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 8 EXCL) for 39 RERS2020-PT-pb103-CTLFireability-13 EXCL) for 45 RERS2020-PT-pb103-CTLFireability-15 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 RERS2020-PT-pb103-CTLFireability-13 -- 0/5 RERS2020-PT-pb103-CTLFireability-15 -- 0/5 RERS2020-PT-pb103-CTLFireability-07 75231 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 9 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 RERS2020-PT-pb103-CTLFireability-13 2957 m, 591 m/sec, 20044 t fired, . 1/5 RERS2020-PT-pb103-CTLFireability-15 36169 m, -303461 m/sec, 255958 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 76826 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 10 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 RERS2020-PT-pb103-CTLFireability-13 25663 m, 4541 m/sec, 179898 t fired, . 1/5 RERS2020-PT-pb103-CTLFireability-15 58960 m, 4558 m/sec, 421788 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 78430 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 10 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 RERS2020-PT-pb103-CTLFireability-13 46253 m, 4118 m/sec, 329020 t fired, . 1/5 RERS2020-PT-pb103-CTLFireability-15 86649 m, 5537 m/sec, 627077 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 79534 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 10 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 RERS2020-PT-pb103-CTLFireability-13 62767 m, 3302 m/sec, 450114 t fired, . 1/5 RERS2020-PT-pb103-CTLFireability-15 104566 m, 3583 m/sec, 761794 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 80489 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 10 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 RERS2020-PT-pb103-CTLFireability-13 77038 m, 2854 m/sec, 555405 t fired, . 1/5 RERS2020-PT-pb103-CTLFireability-15 129416 m, 4970 m/sec, 949394 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 82141 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 10 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 RERS2020-PT-pb103-CTLFireability-13 94756 m, 3543 m/sec, 687824 t fired, . 1/5 RERS2020-PT-pb103-CTLFireability-15 158113 m, 5739 m/sec, 1167232 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 83265 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 10 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 RERS2020-PT-pb103-CTLFireability-13 118000 m, 4648 m/sec, 863310 t fired, . 1/5 RERS2020-PT-pb103-CTLFireability-15 184637 m, 5304 m/sec, 1370118 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 84825 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 10 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 RERS2020-PT-pb103-CTLFireability-13 142072 m, 4814 m/sec, 1045443 t fired, . 2/5 RERS2020-PT-pb103-CTLFireability-15 222391 m, 7550 m/sec, 1662115 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 86278 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 11 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 RERS2020-PT-pb103-CTLFireability-13 162682 m, 4122 m/sec, 1201936 t fired, . 2/5 RERS2020-PT-pb103-CTLFireability-15 247780 m, 5077 m/sec, 1859468 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 87848 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 11 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 RERS2020-PT-pb103-CTLFireability-13 188253 m, 5114 m/sec, 1398033 t fired, . 2/5 RERS2020-PT-pb103-CTLFireability-15 275452 m, 5534 m/sec, 2076841 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 89142 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 11 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 RERS2020-PT-pb103-CTLFireability-13 216766 m, 5702 m/sec, 1618394 t fired, . 2/5 RERS2020-PT-pb103-CTLFireability-15 305865 m, 6082 m/sec, 2315393 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 90216 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 11 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 RERS2020-PT-pb103-CTLFireability-13 239259 m, 4498 m/sec, 1793470 t fired, . 2/5 RERS2020-PT-pb103-CTLFireability-15 344348 m, 7696 m/sec, 2620113 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 91400 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 12 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 RERS2020-PT-pb103-CTLFireability-13 264888 m, 5125 m/sec, 1993350 t fired, . 2/5 RERS2020-PT-pb103-CTLFireability-15 383646 m, 7859 m/sec, 2932638 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 93055 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 12 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 RERS2020-PT-pb103-CTLFireability-13 287241 m, 4470 m/sec, 2169145 t fired, . 2/5 RERS2020-PT-pb103-CTLFireability-15 422394 m, 7749 m/sec, 3242576 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 94122 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 12 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 RERS2020-PT-pb103-CTLFireability-13 309282 m, 4408 m/sec, 2342588 t fired, . 3/5 RERS2020-PT-pb103-CTLFireability-15 450852 m, 5691 m/sec, 3471595 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 95499 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 13 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 RERS2020-PT-pb103-CTLFireability-13 330648 m, 4273 m/sec, 2511088 t fired, . 3/5 RERS2020-PT-pb103-CTLFireability-15 468361 m, 3501 m/sec, 3613187 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 97119 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 13 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 RERS2020-PT-pb103-CTLFireability-13 356813 m, 5233 m/sec, 2719215 t fired, . 3/5 RERS2020-PT-pb103-CTLFireability-15 487840 m, 3895 m/sec, 3770634 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 98398 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 13 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 RERS2020-PT-pb103-CTLFireability-13 386053 m, 5848 m/sec, 2952063 t fired, . 3/5 RERS2020-PT-pb103-CTLFireability-15 507679 m, 3967 m/sec, 3931705 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 99885 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 13 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 RERS2020-PT-pb103-CTLFireability-13 403118 m, 3413 m/sec, 3088044 t fired, . 3/5 RERS2020-PT-pb103-CTLFireability-15 529660 m, 4396 m/sec, 4110355 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 101308 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 13 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 RERS2020-PT-pb103-CTLFireability-13 424865 m, 4349 m/sec, 3262430 t fired, . 3/5 RERS2020-PT-pb103-CTLFireability-15 556239 m, 5315 m/sec, 4327843 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 102515 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 13 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 RERS2020-PT-pb103-CTLFireability-13 442599 m, 3546 m/sec, 3405185 t fired, . 3/5 RERS2020-PT-pb103-CTLFireability-15 588255 m, 6403 m/sec, 4588640 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 103396 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 13 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 RERS2020-PT-pb103-CTLFireability-13 462811 m, 4042 m/sec, 3568267 t fired, . 3/5 RERS2020-PT-pb103-CTLFireability-15 627352 m, 7819 m/sec, 4911032 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 104761 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 14 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 RERS2020-PT-pb103-CTLFireability-13 489536 m, 5345 m/sec, 3784329 t fired, . 3/5 RERS2020-PT-pb103-CTLFireability-15 659339 m, 6397 m/sec, 5175043 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 105700 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 14 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 RERS2020-PT-pb103-CTLFireability-13 504637 m, 3020 m/sec, 3907001 t fired, . 4/5 RERS2020-PT-pb103-CTLFireability-15 698705 m, 7873 m/sec, 5500877 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 107458 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 15 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 RERS2020-PT-pb103-CTLFireability-13 518465 m, 2765 m/sec, 4020099 t fired, . 4/5 RERS2020-PT-pb103-CTLFireability-15 732830 m, 6825 m/sec, 5785225 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 108693 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 15 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 RERS2020-PT-pb103-CTLFireability-13 533409 m, 2988 m/sec, 4140923 t fired, . 4/5 RERS2020-PT-pb103-CTLFireability-15 771963 m, 7826 m/sec, 6113772 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 110470 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 15 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 RERS2020-PT-pb103-CTLFireability-13 552297 m, 3777 m/sec, 4295629 t fired, . 4/5 RERS2020-PT-pb103-CTLFireability-15 809552 m, 7517 m/sec, 6427674 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 111457 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 15 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 RERS2020-PT-pb103-CTLFireability-13 579377 m, 5416 m/sec, 4516366 t fired, . 4/5 RERS2020-PT-pb103-CTLFireability-15 843861 m, 6861 m/sec, 6717928 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 112537 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 15 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 RERS2020-PT-pb103-CTLFireability-13 608731 m, 5870 m/sec, 4757478 t fired, . 4/5 RERS2020-PT-pb103-CTLFireability-15 868753 m, 4978 m/sec, 6928785 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 114106 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 15 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 RERS2020-PT-pb103-CTLFireability-13 637759 m, 5805 m/sec, 4996908 t fired, . 4/5 RERS2020-PT-pb103-CTLFireability-15 893335 m, 4916 m/sec, 7138561 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 115840 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 15 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 RERS2020-PT-pb103-CTLFireability-13 666414 m, 5731 m/sec, 5233423 t fired, . 5/5 RERS2020-PT-pb103-CTLFireability-15 928724 m, 7077 m/sec, 7440230 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 117497 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 16 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 RERS2020-PT-pb103-CTLFireability-13 696338 m, 5984 m/sec, 5481363 t fired, . 5/5 RERS2020-PT-pb103-CTLFireability-15 963351 m, 6925 m/sec, 7737068 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 119257 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 17 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 RERS2020-PT-pb103-CTLFireability-13 726503 m, 6033 m/sec, 5732997 t fired, . 5/5 RERS2020-PT-pb103-CTLFireability-15 998498 m, 7029 m/sec, 8039251 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 120942 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 17 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 RERS2020-PT-pb103-CTLFireability-13 755971 m, 5893 m/sec, 5978723 t fired, . 5/5 RERS2020-PT-pb103-CTLFireability-15 1034794 m, 7259 m/sec, 8353883 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 122491 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 17 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 RERS2020-PT-pb103-CTLFireability-13 781701 m, 5146 m/sec, 6195598 t fired, . 5/5 RERS2020-PT-pb103-CTLFireability-15 1066228 m, 6286 m/sec, 8626268 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 124079 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 17 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 RERS2020-PT-pb103-CTLFireability-13 801266 m, 3913 m/sec, 6358614 t fired, . 5/5 RERS2020-PT-pb103-CTLFireability-15 1103570 m, 7468 m/sec, 8952034 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 125219 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 17 VALUE PRODUCED BY true preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AG 0 1 2 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 RERS2020-PT-pb103-CTLFireability-13 819880 m, 3722 m/sec, 6514768 t fired, . 5/5 RERS2020-PT-pb103-CTLFireability-15 1122651 m, 3816 m/sec, 9119403 t fired, . 0/5 RERS2020-PT-pb103-CTLFireability-07 126293 t fired, 1 attempts, . 0/5 RERS2020-PT-pb103-CTLFireability-07 sara is running. Pages in use: 17 (type EXCL) for RERS2020-PT-pb103-CTLFireability-15 (memory limit exceeded) /../BenchKit_head.sh: line 63: 375 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RERS2020-PT-pb103"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is RERS2020-PT-pb103, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r326-tall-167889198100234"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RERS2020-PT-pb103.tgz
mv RERS2020-PT-pb103 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;