Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r326-tall-167889198100174.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is RERS17pb115-PT-4, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r326-tall-167889198100174
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 70M
-rw-r--r-- 1 mcc users 6.4K Feb 25 13:57 CTLCardinality.txt
-rw-r--r-- 1 mcc users 70K Feb 25 13:57 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.4K Feb 25 13:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 35K Feb 25 13:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:39 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:39 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Feb 25 16:39 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:39 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 14:07 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 120K Feb 25 14:07 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 13K Feb 25 14:01 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 81K Feb 25 14:01 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:39 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:39 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 69M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RERS17pb115-PT-4-ReachabilityCardinality-00
FORMULA_NAME RERS17pb115-PT-4-ReachabilityCardinality-01
FORMULA_NAME RERS17pb115-PT-4-ReachabilityCardinality-02
FORMULA_NAME RERS17pb115-PT-4-ReachabilityCardinality-03
FORMULA_NAME RERS17pb115-PT-4-ReachabilityCardinality-04
FORMULA_NAME RERS17pb115-PT-4-ReachabilityCardinality-05
FORMULA_NAME RERS17pb115-PT-4-ReachabilityCardinality-06
FORMULA_NAME RERS17pb115-PT-4-ReachabilityCardinality-07
FORMULA_NAME RERS17pb115-PT-4-ReachabilityCardinality-08
FORMULA_NAME RERS17pb115-PT-4-ReachabilityCardinality-09
FORMULA_NAME RERS17pb115-PT-4-ReachabilityCardinality-10
FORMULA_NAME RERS17pb115-PT-4-ReachabilityCardinality-11
FORMULA_NAME RERS17pb115-PT-4-ReachabilityCardinality-12
FORMULA_NAME RERS17pb115-PT-4-ReachabilityCardinality-13
FORMULA_NAME RERS17pb115-PT-4-ReachabilityCardinality-14
FORMULA_NAME RERS17pb115-PT-4-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1678991293354

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=ReachabilityCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RERS17pb115-PT-4
Not applying reductions.
Model is PT
ReachabilityCardinality PT
starting LoLA
BK_INPUT RERS17pb115-PT-4
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
ReachabilityCardinality
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 4124108 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16090708 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
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RERS17pb115-PT-4-ReachabilityCardinality-00: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-01: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-02: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-03: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-04: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-05: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-06: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-07: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-08: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-09: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-15: AG 0 0 0 0 0 0 0 0

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RERS17pb115-PT-4-ReachabilityCardinality-01: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-02: EF 0 0 0 0 0 0 0 0
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RERS17pb115-PT-4-ReachabilityCardinality-04: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-05: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-06: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-07: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-08: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-09: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-15: AG 0 0 0 0 0 0 0 0

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RERS17pb115-PT-4-ReachabilityCardinality-06: EF 0 0 0 0 0 0 0 0
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RERS17pb115-PT-4-ReachabilityCardinality-09: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
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RERS17pb115-PT-4-ReachabilityCardinality-09: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
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RERS17pb115-PT-4-ReachabilityCardinality-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-15: AG 0 0 0 0 0 0 0 0

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RERS17pb115-PT-4-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
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RERS17pb115-PT-4-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-4-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
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