About the Execution of LoLA for RERS17pb114-PT-4
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 3379.747 | 3600000.00 | 4253162.00 | 10642.60 | [undef] | Time out reached |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r326-tall-167889198000100.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is RERS17pb114-PT-4, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r326-tall-167889198000100
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 73M
-rw-r--r-- 1 mcc users 5.7K Feb 26 04:51 CTLCardinality.txt
-rw-r--r-- 1 mcc users 58K Feb 26 04:51 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.8K Feb 26 04:47 CTLFireability.txt
-rw-r--r-- 1 mcc users 49K Feb 26 04:47 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:38 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:38 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.1K Feb 25 16:38 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:38 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 26 04:57 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 128K Feb 26 04:57 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.3K Feb 26 04:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 41K Feb 26 04:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:38 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:38 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 73M Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME RERS17pb114-PT-4-LTLFireability-00
FORMULA_NAME RERS17pb114-PT-4-LTLFireability-01
FORMULA_NAME RERS17pb114-PT-4-LTLFireability-02
FORMULA_NAME RERS17pb114-PT-4-LTLFireability-03
FORMULA_NAME RERS17pb114-PT-4-LTLFireability-04
FORMULA_NAME RERS17pb114-PT-4-LTLFireability-05
FORMULA_NAME RERS17pb114-PT-4-LTLFireability-06
FORMULA_NAME RERS17pb114-PT-4-LTLFireability-07
FORMULA_NAME RERS17pb114-PT-4-LTLFireability-08
FORMULA_NAME RERS17pb114-PT-4-LTLFireability-09
FORMULA_NAME RERS17pb114-PT-4-LTLFireability-10
FORMULA_NAME RERS17pb114-PT-4-LTLFireability-11
FORMULA_NAME RERS17pb114-PT-4-LTLFireability-12
FORMULA_NAME RERS17pb114-PT-4-LTLFireability-13
FORMULA_NAME RERS17pb114-PT-4-LTLFireability-14
FORMULA_NAME RERS17pb114-PT-4-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1678959011349
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=LTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RERS17pb114-PT-4
Not applying reductions.
Model is PT
LTLFireability PT
starting LoLA
BK_INPUT RERS17pb114-PT-4
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
LTLFireability
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393232 kB
MemFree: 12752344 kB
After kill :
MemTotal: 16393232 kB
MemFree: 16086784 kB
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/LTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:524
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:373
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:379
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 42 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 47 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 52 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 57 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 62 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 67 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 72 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 77 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 82 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 87 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 92 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 97 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 102 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 107 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 112 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 117 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 122 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 127 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 132 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 137 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 142 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 147 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 152 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 157 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 162 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 167 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 172 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 177 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 182 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 187 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 192 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 197 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 202 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 207 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 212 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 217 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 222 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 227 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 232 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 237 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 242 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 247 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 252 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 257 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 262 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 267 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 272 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 277 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 282 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 287 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 292 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 297 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 302 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 307 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 312 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 317 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 322 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 327 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 332 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 337 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 342 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 347 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 352 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 357 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 362 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 367 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 372 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 377 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 382 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 387 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 392 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 397 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 402 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 407 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 412 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 417 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 422 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 427 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 432 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 437 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 442 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 447 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 452 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 457 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 462 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 467 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 472 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 477 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 482 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 487 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 492 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 497 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 502 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 507 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 512 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 517 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 522 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 527 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 532 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 537 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 542 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 547 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 552 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 557 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 562 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 567 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 572 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 577 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 582 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 587 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 592 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 597 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 602 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 607 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 612 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 617 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 622 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 627 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 632 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 637 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 642 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 647 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 652 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 657 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 662 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 629.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 667 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 672 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 677 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 682 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 687 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 692 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 697 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 702 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 707 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 712 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 717 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 722 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 727 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 732 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 737 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 742 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 747 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 752 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 757 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 762 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 767 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 772 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 777 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 782 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 787 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 792 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 797 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 802 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 807 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 812 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 817 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 822 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 827 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 832 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 837 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 842 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 847 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 852 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 857 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 862 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 867 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 872 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 877 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 882 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 887 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 892 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 897 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 902 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 907 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 912 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 917 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 922 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 927 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 932 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 937 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 942 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 947 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 952 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 957 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 962 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 967 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 972 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 977 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 982 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 987 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 992 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 997 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1002 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1007 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1012 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1017 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1022 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1027 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1032 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1037 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1042 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1047 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1053 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1058 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1063 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1068 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1073 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1078 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1083 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1088 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1093 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1098 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1103 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 438.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1108 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1113 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1118 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1123 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1128 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1133 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1138 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1143 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1148 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1153 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1158 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1163 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1168 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1173 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1178 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1183 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1188 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1193 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1198 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1203 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1208 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1213 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1218 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1223 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1228 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1233 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1238 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1243 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1248 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1253 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1258 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1263 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1268 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1273 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1278 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1283 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1288 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1293 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1298 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1303 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1308 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1313 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1318 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1323 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1328 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1333 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1338 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1343 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1348 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1353 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1358 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1363 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1368 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1373 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1378 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1383 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1388 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1393 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1398 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1403 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1408 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1413 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1418 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1423 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1428 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1433 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1438 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1443 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1448 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1453 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1458 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1463 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1468 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1473 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1478 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1483 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1488 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1493 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1498 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1503 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1508 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1513 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1518 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1523 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1528 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1533 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1538 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1543 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1548 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1553 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1558 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1563 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1568 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1573 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1578 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1583 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1588 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1593 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1598 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1603 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1608 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1613 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1618 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1623 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1628 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1633 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1638 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1643 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1648 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1653 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1658 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1663 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1668 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 568.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1673 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1678 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1683 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1688 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1693 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1698 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1703 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1708 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1713 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1718 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1723 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1728 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1733 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1738 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1743 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1748 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1753 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1758 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1763 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1768 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1773 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1778 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1783 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1788 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1793 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1798 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1803 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1808 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1813 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1818 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1823 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1828 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1833 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1838 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1843 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1848 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1853 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1858 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1863 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1868 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1873 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1878 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1883 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1888 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1893 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1898 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1903 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1908 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1913 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1918 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1923 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1928 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1933 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1938 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1943 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1948 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1953 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1958 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1963 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1968 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1973 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1978 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1983 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1988 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1993 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1998 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2003 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2008 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2013 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2018 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2023 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2028 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2033 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2038 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2043 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2048 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2053 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2058 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2063 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2068 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2073 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2078 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2083 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2088 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2093 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2098 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2103 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2108 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2113 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2118 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2123 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2128 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2133 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2138 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2143 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2148 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2153 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2158 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2163 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2168 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2173 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2178 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2183 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2188 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2193 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2198 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2203 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2208 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2213 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2218 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2223 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2228 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2233 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2238 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2243 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2248 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2253 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2258 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2263 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2268 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2273 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2278 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 610.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2283 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2288 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2293 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2298 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2303 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2308 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2313 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2318 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2323 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2328 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2333 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2338 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2343 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2348 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2353 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2358 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2363 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2368 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2373 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2378 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2383 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2388 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2393 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2398 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2403 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2408 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2413 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2419 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2424 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2429 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2434 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2439 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2444 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2449 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2454 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2459 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2464 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2469 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2474 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2479 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2484 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2489 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2494 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2499 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2504 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2509 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2514 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2519 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2524 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2529 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2534 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2539 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2544 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2549 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2554 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2559 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2564 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2569 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2574 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2579 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2584 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2589 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2594 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2599 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2604 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2609 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2614 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2619 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2624 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2629 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2634 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2639 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2644 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2649 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2654 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2659 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2664 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2669 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2674 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2679 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2684 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2689 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2694 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2699 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2704 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2709 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2714 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2719 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2724 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2729 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2734 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2739 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2744 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2749 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2754 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2759 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2764 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2769 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2774 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2779 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2784 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2789 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2794 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2799 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2804 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2809 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2814 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2819 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2824 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2829 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2834 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2839 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2844 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2849 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2854 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2859 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2864 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2869 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2874 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2879 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2884 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2889 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2894 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2899 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2904 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2909 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2914 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2919 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2924 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 615.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2929 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2934 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2939 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2944 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2949 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2954 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2959 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2964 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2969 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2974 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2979 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2984 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2989 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2994 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2999 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3004 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3009 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3014 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3019 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3024 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3029 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3034 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3039 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3044 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3049 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3054 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3059 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3064 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3069 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3074 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3079 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 3084 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-4-LTLFireability-00: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-04: AG 0 0 0 0 1 0 0 0
RERS17pb114-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RERS17pb114-PT-4"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is RERS17pb114-PT-4, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r326-tall-167889198000100"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/RERS17pb114-PT-4.tgz
mv RERS17pb114-PT-4 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;