fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r326-tall-167889197900026
Last Updated
May 14, 2023

About the Execution of LoLA for RERS17pb113-PT-4

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
0.000 493210.00 0.00 0.00 [undef] Cannot compute

Execution Chart

Sorry, for this execution, no execution chart could be reported.

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r326-tall-167889197900026.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is RERS17pb113-PT-4, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r326-tall-167889197900026
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 15M
-rw-r--r-- 1 mcc users 7.3K Feb 26 18:11 CTLCardinality.txt
-rw-r--r-- 1 mcc users 80K Feb 26 18:11 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.5K Feb 26 18:10 CTLFireability.txt
-rw-r--r-- 1 mcc users 53K Feb 26 18:10 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 16:37 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:37 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Feb 25 16:37 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:37 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 26 18:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 110K Feb 26 18:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 14K Feb 26 18:14 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 89K Feb 26 18:14 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:37 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:37 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 15M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-00
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-01
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-02
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-03
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-04
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-05
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-06
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-07
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-08
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-09
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-10
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-11
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-12
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-13
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-14
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678936114030

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RERS17pb113-PT-4
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT RERS17pb113-PT-4
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

BK_STOP 1678936607240

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 145 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 150 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 13.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 155 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 160 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 165 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 170 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 175 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 13.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 180 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 185 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 12.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 190 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 195 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 200 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 205 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 210 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 215 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 13.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 220 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 225 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 230 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 235 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 240 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 245 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 250 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 255 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 260 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 265 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 270 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 275 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 280 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 285 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 290 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 295 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 300 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 305 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 310 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 315 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 320 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 325 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 330 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 335 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 340 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 100.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 345 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 350 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 355 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 16.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 360 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 365 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 370 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 17.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 377 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 382 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 387 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 392 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 397 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 27.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 402 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 407 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 412 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 417 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 422 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 13.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 427 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 432 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 437 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 12.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 442 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 447 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 28 (type EXCL) for 27 RERS17pb113-PT-4-CTLFireability-09
lola: time limit : 136 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-CTLFireability-00: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-02: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-03: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-07: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-12: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 0/136 0/32 RERS17pb113-PT-4-CTLFireability-09 --

Time elapsed: 461 secs. Pages in use: 0
# running tasks: 1 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
/home/mcc/BenchKit/bin//../lola/bin//../BenchKit_head.sh: line 63: 376 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RERS17pb113-PT-4"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is RERS17pb113-PT-4, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r326-tall-167889197900026"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RERS17pb113-PT-4.tgz
mv RERS17pb113-PT-4 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;