About the Execution of LoLA for RERS17pb113-PT-2
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16205.964 | 3600000.00 | 13829262.00 | 9189.30 | FFFTF??FT?FFFFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r326-tall-167889197900012.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is RERS17pb113-PT-2, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r326-tall-167889197900012
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 15M
-rw-r--r-- 1 mcc users 6.4K Feb 26 18:12 CTLCardinality.txt
-rw-r--r-- 1 mcc users 66K Feb 26 18:12 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K Feb 26 18:11 CTLFireability.txt
-rw-r--r-- 1 mcc users 40K Feb 26 18:11 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 16:37 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:37 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Feb 25 16:37 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:37 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.7K Feb 26 18:18 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 73K Feb 26 18:18 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.6K Feb 26 18:15 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 51K Feb 26 18:15 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:37 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:37 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 15M Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME RERS17pb113-PT-2-LTLFireability-00
FORMULA_NAME RERS17pb113-PT-2-LTLFireability-01
FORMULA_NAME RERS17pb113-PT-2-LTLFireability-02
FORMULA_NAME RERS17pb113-PT-2-LTLFireability-03
FORMULA_NAME RERS17pb113-PT-2-LTLFireability-04
FORMULA_NAME RERS17pb113-PT-2-LTLFireability-05
FORMULA_NAME RERS17pb113-PT-2-LTLFireability-06
FORMULA_NAME RERS17pb113-PT-2-LTLFireability-07
FORMULA_NAME RERS17pb113-PT-2-LTLFireability-08
FORMULA_NAME RERS17pb113-PT-2-LTLFireability-09
FORMULA_NAME RERS17pb113-PT-2-LTLFireability-10
FORMULA_NAME RERS17pb113-PT-2-LTLFireability-11
FORMULA_NAME RERS17pb113-PT-2-LTLFireability-12
FORMULA_NAME RERS17pb113-PT-2-LTLFireability-13
FORMULA_NAME RERS17pb113-PT-2-LTLFireability-14
FORMULA_NAME RERS17pb113-PT-2-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1678931354036
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=LTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RERS17pb113-PT-2
Not applying reductions.
Model is PT
LTLFireability PT
starting LoLA
BK_INPUT RERS17pb113-PT-2
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
LTLFireability
FORMULA RERS17pb113-PT-2-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RERS17pb113-PT-2-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RERS17pb113-PT-2-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RERS17pb113-PT-2-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RERS17pb113-PT-2-LTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RERS17pb113-PT-2-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RERS17pb113-PT-2-LTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RERS17pb113-PT-2-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RERS17pb113-PT-2-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RERS17pb113-PT-2-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RERS17pb113-PT-2-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RERS17pb113-PT-2-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RERS17pb113-PT-2-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 224744 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16231352 kB
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/LTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:409
lola: rewrite Frontend/Parser/formula_rewrite.k:409
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:496
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:373
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:379
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-2-LTLFireability-00: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-05: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-11: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-13: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 21 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-2-LTLFireability-00: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-05: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-11: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-13: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 26 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-2-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-2-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-05: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-11: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-13: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 31 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-2-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-2-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-02: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-05: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-11: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-12: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-13: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-2-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 36 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
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64 ER EXCL 13/164 1/32 RERS17pb113-PT-2-LTLFireability-12 --
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59 LTL EXCL 1/218 1/32 RERS17pb113-PT-2-LTLFireability-14 32593 m, 6518 m/sec, 32592 t fired, .
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67 EF STEQ 23/1625 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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28 LTL EXCL 3/233 2/32 RERS17pb113-PT-2-LTLFireability-09 84323 m, 16864 m/sec, 84323 t fired, .
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67 EF STEQ 28/1622 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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28 LTL EXCL 8/233 4/32 RERS17pb113-PT-2-LTLFireability-09 199722 m, 23079 m/sec, 199749 t fired, .
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67 EF STEQ 33/1619 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
70 EF SRCH 33/1619 1/5 RERS17pb113-PT-2-LTLFireability-05 2992 m, 160 m/sec, 2991 t fired, .
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28 LTL EXCL 13/233 5/32 RERS17pb113-PT-2-LTLFireability-09 309801 m, 22015 m/sec, 309881 t fired, .
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67 EF STEQ 38/1614 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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28 LTL EXCL 18/233 7/32 RERS17pb113-PT-2-LTLFireability-09 429778 m, 23995 m/sec, 429941 t fired, .
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67 EF STEQ 43/1606 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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28 LTL EXCL 23/233 9/32 RERS17pb113-PT-2-LTLFireability-09 567539 m, 27552 m/sec, 567796 t fired, .
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67 EF STEQ 48/1604 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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28 LTL EXCL 28/233 11/32 RERS17pb113-PT-2-LTLFireability-09 710595 m, 28611 m/sec, 710999 t fired, .
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67 EF STEQ 53/1599 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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67 EF STEQ 58/1594 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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67 EF STEQ 63/1589 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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28 LTL EXCL 43/233 17/32 RERS17pb113-PT-2-LTLFireability-09 1125054 m, 28279 m/sec, 1126069 t fired, .
66 EF FNDP 68/1584 0/5 RERS17pb113-PT-2-LTLFireability-05 10334 t fired, 1 attempts, .
67 EF STEQ 68/1584 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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28 LTL EXCL 48/233 19/32 RERS17pb113-PT-2-LTLFireability-09 1266791 m, 28347 m/sec, 1267984 t fired, .
66 EF FNDP 73/1579 0/5 RERS17pb113-PT-2-LTLFireability-05 11509 t fired, 1 attempts, .
67 EF STEQ 73/1579 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
70 EF SRCH 73/1579 1/5 RERS17pb113-PT-2-LTLFireability-05 11787 m, 236 m/sec, 37100 t fired, .
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28 LTL EXCL 53/233 22/32 RERS17pb113-PT-2-LTLFireability-09 1406982 m, 28038 m/sec, 1408357 t fired, .
66 EF FNDP 78/1574 0/5 RERS17pb113-PT-2-LTLFireability-05 12665 t fired, 1 attempts, .
67 EF STEQ 78/1574 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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28 LTL EXCL 58/233 24/32 RERS17pb113-PT-2-LTLFireability-09 1546381 m, 27879 m/sec, 1547960 t fired, .
66 EF FNDP 83/1569 0/5 RERS17pb113-PT-2-LTLFireability-05 13833 t fired, 1 attempts, .
67 EF STEQ 83/1569 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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28 LTL EXCL 63/233 25/32 RERS17pb113-PT-2-LTLFireability-09 1677143 m, 26152 m/sec, 1678916 t fired, .
66 EF FNDP 88/1564 0/5 RERS17pb113-PT-2-LTLFireability-05 14940 t fired, 1 attempts, .
67 EF STEQ 88/1564 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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28 LTL EXCL 68/233 27/32 RERS17pb113-PT-2-LTLFireability-09 1807100 m, 25991 m/sec, 1809148 t fired, .
66 EF FNDP 93/1559 0/5 RERS17pb113-PT-2-LTLFireability-05 15936 t fired, 1 attempts, .
67 EF STEQ 93/1559 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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28 LTL EXCL 73/233 29/32 RERS17pb113-PT-2-LTLFireability-09 1930993 m, 24778 m/sec, 1933325 t fired, .
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67 EF STEQ 98/1554 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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28 LTL EXCL 78/233 31/32 RERS17pb113-PT-2-LTLFireability-09 2060789 m, 25959 m/sec, 2063379 t fired, .
66 EF FNDP 103/1549 0/5 RERS17pb113-PT-2-LTLFireability-05 18075 t fired, 1 attempts, .
67 EF STEQ 103/1549 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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67 EF STEQ 108/1544 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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66 EF FNDP 118/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 21109 t fired, 1 attempts, .
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66 EF FNDP 123/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 22285 t fired, 1 attempts, .
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66 EF FNDP 128/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 23459 t fired, 1 attempts, .
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66 EF FNDP 293/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 63295 t fired, 1 attempts, .
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66 EF FNDP 408/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 91837 t fired, 1 attempts, .
67 EF STEQ 408/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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66 EF FNDP 413/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 93072 t fired, 1 attempts, .
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66 EF FNDP 418/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 94342 t fired, 1 attempts, .
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66 EF FNDP 423/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 95533 t fired, 1 attempts, .
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66 EF FNDP 428/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 96718 t fired, 1 attempts, .
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66 EF FNDP 523/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 120217 t fired, 1 attempts, .
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66 EF FNDP 528/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 121481 t fired, 1 attempts, .
67 EF STEQ 528/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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66 EF FNDP 583/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 134253 t fired, 1 attempts, .
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66 EF FNDP 698/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 158912 t fired, 1 attempts, .
67 EF STEQ 698/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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66 EF FNDP 703/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 160056 t fired, 1 attempts, .
67 EF STEQ 703/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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66 EF FNDP 708/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 161292 t fired, 1 attempts, .
67 EF STEQ 708/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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66 EF FNDP 713/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 162505 t fired, 1 attempts, .
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66 EF FNDP 718/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 163696 t fired, 1 attempts, .
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66 EF FNDP 723/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 164906 t fired, 1 attempts, .
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66 EF FNDP 728/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 166095 t fired, 1 attempts, .
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66 EF FNDP 753/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 172010 t fired, 1 attempts, .
67 EF STEQ 753/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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66 EF FNDP 758/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 173174 t fired, 1 attempts, .
67 EF STEQ 758/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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66 EF FNDP 763/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 174368 t fired, 1 attempts, .
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66 EF FNDP 773/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 176736 t fired, 1 attempts, .
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66 EF FNDP 813/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 185606 t fired, 1 attempts, .
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66 EF FNDP 818/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 186630 t fired, 1 attempts, .
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66 EF FNDP 823/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 187723 t fired, 1 attempts, .
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66 EF FNDP 828/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 188872 t fired, 1 attempts, .
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66 EF FNDP 928/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 212173 t fired, 1 attempts, .
67 EF STEQ 928/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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66 EF FNDP 933/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 213374 t fired, 1 attempts, .
67 EF STEQ 933/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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66 EF FNDP 938/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 214557 t fired, 1 attempts, .
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66 EF FNDP 943/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 215742 t fired, 1 attempts, .
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66 EF FNDP 948/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 216932 t fired, 1 attempts, .
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66 EF FNDP 983/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 224862 t fired, 1 attempts, .
67 EF STEQ 983/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
68 EG EXCL 410/453 1/32 RERS17pb113-PT-2-LTLFireability-11 31339 m, 76 m/sec, 31338 t fired, .
70 EF SRCH 983/3294 2/5 RERS17pb113-PT-2-LTLFireability-05 224675 m, 227 m/sec, 1450819 t fired, .
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66 EF FNDP 988/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 226021 t fired, 1 attempts, .
67 EF STEQ 988/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
68 EG EXCL 415/453 1/32 RERS17pb113-PT-2-LTLFireability-11 31725 m, 77 m/sec, 31724 t fired, .
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66 EF FNDP 993/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 227171 t fired, 1 attempts, .
67 EF STEQ 993/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
68 EG EXCL 420/453 1/32 RERS17pb113-PT-2-LTLFireability-11 32115 m, 78 m/sec, 32114 t fired, .
70 EF SRCH 993/3294 2/5 RERS17pb113-PT-2-LTLFireability-05 226976 m, 229 m/sec, 1467849 t fired, .
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66 EF FNDP 998/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 228344 t fired, 1 attempts, .
67 EF STEQ 998/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
68 EG EXCL 425/453 1/32 RERS17pb113-PT-2-LTLFireability-11 32513 m, 79 m/sec, 32512 t fired, .
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66 EF FNDP 1003/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 229449 t fired, 1 attempts, .
67 EF STEQ 1003/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
68 EG EXCL 430/453 1/32 RERS17pb113-PT-2-LTLFireability-11 32899 m, 77 m/sec, 32898 t fired, .
70 EF SRCH 1003/3294 2/5 RERS17pb113-PT-2-LTLFireability-05 229247 m, 220 m/sec, 1483598 t fired, .
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66 EF FNDP 1008/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 230534 t fired, 1 attempts, .
67 EF STEQ 1008/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
68 EG EXCL 435/453 1/32 RERS17pb113-PT-2-LTLFireability-11 33285 m, 77 m/sec, 33284 t fired, .
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66 EF FNDP 1013/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 231638 t fired, 1 attempts, .
67 EF STEQ 1013/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
68 EG EXCL 440/453 1/32 RERS17pb113-PT-2-LTLFireability-11 33663 m, 75 m/sec, 33662 t fired, .
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66 EF FNDP 1018/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 232735 t fired, 1 attempts, .
67 EF STEQ 1018/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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56 LTL EXCL 4/567 1/32 RERS17pb113-PT-2-LTLFireability-13 312 m, 62 m/sec, 311 t fired, .
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67 EF STEQ 1028/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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56 LTL EXCL 9/567 1/32 RERS17pb113-PT-2-LTLFireability-13 649 m, 67 m/sec, 648 t fired, .
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56 LTL EXCL 14/567 1/32 RERS17pb113-PT-2-LTLFireability-13 1016 m, 73 m/sec, 1015 t fired, .
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56 LTL EXCL 19/567 1/32 RERS17pb113-PT-2-LTLFireability-13 1391 m, 75 m/sec, 1390 t fired, .
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56 LTL EXCL 24/567 1/32 RERS17pb113-PT-2-LTLFireability-13 1769 m, 75 m/sec, 1768 t fired, .
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56 LTL EXCL 29/567 1/32 RERS17pb113-PT-2-LTLFireability-13 2160 m, 78 m/sec, 2159 t fired, .
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56 LTL EXCL 34/567 1/32 RERS17pb113-PT-2-LTLFireability-13 2551 m, 78 m/sec, 2550 t fired, .
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56 LTL EXCL 39/567 1/32 RERS17pb113-PT-2-LTLFireability-13 2934 m, 76 m/sec, 2933 t fired, .
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56 LTL EXCL 134/567 1/32 RERS17pb113-PT-2-LTLFireability-13 10240 m, 79 m/sec, 10239 t fired, .
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56 LTL EXCL 139/567 1/32 RERS17pb113-PT-2-LTLFireability-13 10624 m, 76 m/sec, 10623 t fired, .
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56 LTL EXCL 149/567 1/32 RERS17pb113-PT-2-LTLFireability-13 11362 m, 73 m/sec, 11361 t fired, .
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56 LTL EXCL 154/567 1/32 RERS17pb113-PT-2-LTLFireability-13 11707 m, 69 m/sec, 11706 t fired, .
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56 LTL EXCL 159/567 1/32 RERS17pb113-PT-2-LTLFireability-13 12088 m, 76 m/sec, 12087 t fired, .
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56 LTL EXCL 365/567 1/32 RERS17pb113-PT-2-LTLFireability-13 27598 m, 77 m/sec, 27597 t fired, .
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56 LTL EXCL 540/567 1/32 RERS17pb113-PT-2-LTLFireability-13 41041 m, 79 m/sec, 41041 t fired, .
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56 LTL EXCL 545/567 1/32 RERS17pb113-PT-2-LTLFireability-13 41433 m, 78 m/sec, 41433 t fired, .
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56 LTL EXCL 550/567 1/32 RERS17pb113-PT-2-LTLFireability-13 41819 m, 77 m/sec, 41819 t fired, .
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54 LTL EXCL 30/566 1/32 RERS17pb113-PT-2-LTLFireability-13 2240 m, 78 m/sec, 2239 t fired, .
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54 LTL EXCL 45/566 1/32 RERS17pb113-PT-2-LTLFireability-13 3405 m, 77 m/sec, 3404 t fired, .
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54 LTL EXCL 85/566 1/32 RERS17pb113-PT-2-LTLFireability-13 6486 m, 74 m/sec, 6485 t fired, .
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54 LTL EXCL 90/566 1/32 RERS17pb113-PT-2-LTLFireability-13 6874 m, 77 m/sec, 6873 t fired, .
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54 LTL EXCL 95/566 1/32 RERS17pb113-PT-2-LTLFireability-13 7270 m, 79 m/sec, 7269 t fired, .
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54 LTL EXCL 100/566 1/32 RERS17pb113-PT-2-LTLFireability-13 7650 m, 76 m/sec, 7649 t fired, .
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54 LTL EXCL 145/566 1/32 RERS17pb113-PT-2-LTLFireability-13 11133 m, 78 m/sec, 11132 t fired, .
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54 LTL EXCL 150/566 1/32 RERS17pb113-PT-2-LTLFireability-13 11507 m, 74 m/sec, 11506 t fired, .
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54 LTL EXCL 155/566 1/32 RERS17pb113-PT-2-LTLFireability-13 11888 m, 76 m/sec, 11887 t fired, .
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54 LTL EXCL 160/566 1/32 RERS17pb113-PT-2-LTLFireability-13 12275 m, 77 m/sec, 12274 t fired, .
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54 LTL EXCL 165/566 1/32 RERS17pb113-PT-2-LTLFireability-13 12653 m, 75 m/sec, 12652 t fired, .
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54 LTL EXCL 200/566 1/32 RERS17pb113-PT-2-LTLFireability-13 15357 m, 76 m/sec, 15356 t fired, .
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54 LTL EXCL 205/566 1/32 RERS17pb113-PT-2-LTLFireability-13 15751 m, 78 m/sec, 15750 t fired, .
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54 LTL EXCL 210/566 1/32 RERS17pb113-PT-2-LTLFireability-13 16130 m, 75 m/sec, 16129 t fired, .
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54 LTL EXCL 215/566 1/32 RERS17pb113-PT-2-LTLFireability-13 16518 m, 77 m/sec, 16517 t fired, .
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54 LTL EXCL 225/566 1/32 RERS17pb113-PT-2-LTLFireability-13 17291 m, 76 m/sec, 17290 t fired, .
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54 LTL EXCL 260/566 1/32 RERS17pb113-PT-2-LTLFireability-13 19960 m, 77 m/sec, 19959 t fired, .
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54 LTL EXCL 265/566 1/32 RERS17pb113-PT-2-LTLFireability-13 20346 m, 77 m/sec, 20345 t fired, .
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54 LTL EXCL 270/566 1/32 RERS17pb113-PT-2-LTLFireability-13 20737 m, 78 m/sec, 20736 t fired, .
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54 LTL EXCL 275/566 1/32 RERS17pb113-PT-2-LTLFireability-13 21127 m, 78 m/sec, 21126 t fired, .
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54 LTL EXCL 280/566 1/32 RERS17pb113-PT-2-LTLFireability-13 21532 m, 81 m/sec, 21531 t fired, .
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54 LTL EXCL 315/566 1/32 RERS17pb113-PT-2-LTLFireability-13 24227 m, 77 m/sec, 24226 t fired, .
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67 EF STEQ 1909/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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54 LTL EXCL 320/566 1/32 RERS17pb113-PT-2-LTLFireability-13 24600 m, 74 m/sec, 24599 t fired, .
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67 EF STEQ 1914/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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54 LTL EXCL 325/566 1/32 RERS17pb113-PT-2-LTLFireability-13 24994 m, 78 m/sec, 24993 t fired, .
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54 LTL EXCL 330/566 1/32 RERS17pb113-PT-2-LTLFireability-13 25390 m, 79 m/sec, 25389 t fired, .
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54 LTL EXCL 335/566 1/32 RERS17pb113-PT-2-LTLFireability-13 25778 m, 77 m/sec, 25777 t fired, .
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67 EF STEQ 1929/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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54 LTL EXCL 340/566 1/32 RERS17pb113-PT-2-LTLFireability-13 26159 m, 76 m/sec, 26158 t fired, .
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54 LTL EXCL 345/566 1/32 RERS17pb113-PT-2-LTLFireability-13 26552 m, 78 m/sec, 26551 t fired, .
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54 LTL EXCL 350/566 1/32 RERS17pb113-PT-2-LTLFireability-13 26944 m, 78 m/sec, 26943 t fired, .
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54 LTL EXCL 355/566 1/32 RERS17pb113-PT-2-LTLFireability-13 27317 m, 74 m/sec, 27316 t fired, .
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54 LTL EXCL 375/566 1/32 RERS17pb113-PT-2-LTLFireability-13 28844 m, 78 m/sec, 28843 t fired, .
66 EF FNDP 1969/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 449215 t fired, 1 attempts, .
67 EF STEQ 1969/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
70 EF SRCH 1969/3294 3/5 RERS17pb113-PT-2-LTLFireability-05 447683 m, 240 m/sec, 2938169 t fired, .
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54 LTL EXCL 380/566 1/32 RERS17pb113-PT-2-LTLFireability-13 29239 m, 79 m/sec, 29238 t fired, .
66 EF FNDP 1974/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 450380 t fired, 1 attempts, .
67 EF STEQ 1974/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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54 LTL EXCL 385/566 1/32 RERS17pb113-PT-2-LTLFireability-13 29632 m, 78 m/sec, 29631 t fired, .
66 EF FNDP 1979/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 451513 t fired, 1 attempts, .
67 EF STEQ 1979/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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54 LTL EXCL 390/566 1/32 RERS17pb113-PT-2-LTLFireability-13 30021 m, 77 m/sec, 30020 t fired, .
66 EF FNDP 1984/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 452623 t fired, 1 attempts, .
67 EF STEQ 1984/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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54 LTL EXCL 395/566 1/32 RERS17pb113-PT-2-LTLFireability-13 30413 m, 78 m/sec, 30412 t fired, .
66 EF FNDP 1989/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 453737 t fired, 1 attempts, .
67 EF STEQ 1989/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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54 LTL EXCL 400/566 1/32 RERS17pb113-PT-2-LTLFireability-13 30805 m, 78 m/sec, 30804 t fired, .
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67 EF STEQ 1994/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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54 LTL EXCL 405/566 1/32 RERS17pb113-PT-2-LTLFireability-13 31199 m, 78 m/sec, 31198 t fired, .
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54 LTL EXCL 410/566 1/32 RERS17pb113-PT-2-LTLFireability-13 31583 m, 76 m/sec, 31582 t fired, .
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54 LTL EXCL 415/566 1/32 RERS17pb113-PT-2-LTLFireability-13 31973 m, 78 m/sec, 31972 t fired, .
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54 LTL EXCL 430/566 1/32 RERS17pb113-PT-2-LTLFireability-13 33119 m, 75 m/sec, 33118 t fired, .
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54 LTL EXCL 435/566 1/32 RERS17pb113-PT-2-LTLFireability-13 33476 m, 71 m/sec, 33475 t fired, .
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67 EF STEQ 2029/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
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RERS17pb113-PT-2-LTLFireability-04: LTL false LTL model checker
RERS17pb113-PT-2-LTLFireability-08: LTL true LTL model checker
RERS17pb113-PT-2-LTLFireability-10: CONJ false preprocessing
RERS17pb113-PT-2-LTLFireability-11: CONJ false state space / EG
RERS17pb113-PT-2-LTLFireability-12: CONJ false state space /ER
RERS17pb113-PT-2-LTLFireability-13: CONJ false LTL model checker
RERS17pb113-PT-2-LTLFireability-14: LTL false LTL model checker
RERS17pb113-PT-2-LTLFireability-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-2-LTLFireability-05: AG 0 0 3 0 1 1 0 0
RERS17pb113-PT-2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-2-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-2-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 LTL EXCL 160/627 1/32 RERS17pb113-PT-2-LTLFireability-07 12128 m, 76 m/sec, 12127 t fired, .
66 EF FNDP 2199/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 500591 t fired, 1 attempts, .
67 EF STEQ 2199/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
70 EF SRCH 2199/3294 3/5 RERS17pb113-PT-2-LTLFireability-05 498756 m, 221 m/sec, 3302747 t fired, .
Time elapsed: 2505 secs. Pages in use: 33
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-2-LTLFireability-00: LTL false LTL model checker
RERS17pb113-PT-2-LTLFireability-01: LTL false LTL model checker
RERS17pb113-PT-2-LTLFireability-02: AG false state space
RERS17pb113-PT-2-LTLFireability-03: LTL true LTL model checker
RERS17pb113-PT-2-LTLFireability-04: LTL false LTL model checker
RERS17pb113-PT-2-LTLFireability-08: LTL true LTL model checker
RERS17pb113-PT-2-LTLFireability-10: CONJ false preprocessing
RERS17pb113-PT-2-LTLFireability-11: CONJ false state space / EG
RERS17pb113-PT-2-LTLFireability-12: CONJ false state space /ER
RERS17pb113-PT-2-LTLFireability-13: CONJ false LTL model checker
RERS17pb113-PT-2-LTLFireability-14: LTL false LTL model checker
RERS17pb113-PT-2-LTLFireability-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-2-LTLFireability-05: AG 0 0 3 0 1 1 0 0
RERS17pb113-PT-2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-2-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-2-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 LTL EXCL 165/627 1/32 RERS17pb113-PT-2-LTLFireability-07 12539 m, 82 m/sec, 12538 t fired, .
66 EF FNDP 2204/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 501793 t fired, 1 attempts, .
67 EF STEQ 2204/3294 0/5 RERS17pb113-PT-2-LTLFireability-05 sara is running.
70 EF SRCH 2204/3294 3/5 RERS17pb113-PT-2-LTLFireability-05 499950 m, 238 m/sec, 3311258 t fired, .
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RERS17pb113-PT-2"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is RERS17pb113-PT-2, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r326-tall-167889197900012"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/RERS17pb113-PT-2.tgz
mv RERS17pb113-PT-2 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;