About the Execution of Marcie for RingSingleMessageInMbox-PT-d1m020
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
9598.048 | 3600000.00 | 3600101.00 | 0.00 | [undef] | Time out reached |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r321-tall-167889192700850.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...............
=====================================================================
Generated by BenchKit 2-5348
Executing tool marcie
Input is RingSingleMessageInMbox-PT-d1m020, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 1
Run identifier is r321-tall-167889192700850
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 6.3M
-rw-r--r-- 1 mcc users 8.8K Feb 26 05:06 CTLCardinality.txt
-rw-r--r-- 1 mcc users 93K Feb 26 05:06 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.4K Feb 26 05:04 CTLFireability.txt
-rw-r--r-- 1 mcc users 45K Feb 26 05:04 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:46 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:46 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 16:46 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:46 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 26 05:11 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 141K Feb 26 05:11 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.3K Feb 26 05:09 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 66K Feb 26 05:09 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 25 16:46 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:46 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 7 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 5.8M Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME RingSingleMessageInMbox-PT-d1m020-CTLFireability-00
FORMULA_NAME RingSingleMessageInMbox-PT-d1m020-CTLFireability-01
FORMULA_NAME RingSingleMessageInMbox-PT-d1m020-CTLFireability-02
FORMULA_NAME RingSingleMessageInMbox-PT-d1m020-CTLFireability-03
FORMULA_NAME RingSingleMessageInMbox-PT-d1m020-CTLFireability-04
FORMULA_NAME RingSingleMessageInMbox-PT-d1m020-CTLFireability-05
FORMULA_NAME RingSingleMessageInMbox-PT-d1m020-CTLFireability-06
FORMULA_NAME RingSingleMessageInMbox-PT-d1m020-CTLFireability-07
FORMULA_NAME RingSingleMessageInMbox-PT-d1m020-CTLFireability-08
FORMULA_NAME RingSingleMessageInMbox-PT-d1m020-CTLFireability-09
FORMULA_NAME RingSingleMessageInMbox-PT-d1m020-CTLFireability-10
FORMULA_NAME RingSingleMessageInMbox-PT-d1m020-CTLFireability-11
FORMULA_NAME RingSingleMessageInMbox-PT-d1m020-CTLFireability-12
FORMULA_NAME RingSingleMessageInMbox-PT-d1m020-CTLFireability-13
FORMULA_NAME RingSingleMessageInMbox-PT-d1m020-CTLFireability-14
FORMULA_NAME RingSingleMessageInMbox-PT-d1m020-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678943651600
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=marcie
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RingSingleMessageInMbox-PT-d1m020
Not applying reductions.
Model is PT
CTLFireability PT
timeout --kill-after=10s --signal=SIGINT 1m for testing only
Marcie built on Linux at 2019-11-18.
A model checker for Generalized Stochastic Petri nets
authors: Alex Tovchigrechko (IDD package and CTL model checking)
Martin Schwarick (Symbolic numerical analysis and CSL model checking)
Christian Rohr (Simulative and approximative numerical model checking)
marcie@informatik.tu-cottbus.de
called as: /home/mcc/BenchKit/bin//../marcie/bin/marcie --net-file=model.pnml --mcc-file=CTLFireability.xml --memory=6 --mcc-mode
parse successfull
net created successfully
Net: RingSingleMessageInMbox_PT_d1m020
(NrP: 6690 NrTr: 11934 NrArc: 47736)
parse formulas
formulas created successfully
place and transition orderings generation:0m19.594sec
net check time: 0m 0.007sec
init dd package: 0m 2.852sec
before gc: list nodes free: 1295330
after gc: idd nodes used:206634, unused:63793366; list nodes free:261262916
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393916 kB
MemFree: 6630604 kB
After kill :
MemTotal: 16393916 kB
MemFree: 16175128 kB
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
check for maximal unmarked siphon
found
The net has a maximal unmarked siphon:
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l4999
l5000
l5002
l5003
l5004
l5005
l5006
l5007
l5008
l5009
l5010
l5011
l5013
l5014
l5015
l5016
l5017
l5018
l5019
l5020
l5021
l5022
l5025
l5026
l5027
l5028
l5029
l5030
l5031
l5032
l5033
l5034
l5036
l5037
l5038
l5039
l5040
l5041
l5042
l5043
l5044
l5045
l5047
l5048
l5049
l5050
l5051
l5052
l5053
l5054
l5055
l5056
l5058
l5059
l5060
l5061
l5062
l5063
l5064
l5065
l5066
l5067
l5069
l5070
l5071
l5072
l5073
l5074
l5075
l5076
l5077
l5078
l5080
l5081
l5082
l5083
l5084
l5085
l5086
l5087
l5088
l5089
l5091
l5092
l5093
l5094
l5095
l5096
l5097
l5098
l5099
l5100
l5102
l5103
l5104
l5105
l5106
l5107
l5108
l5109
l5110
l5111
l5113
l5114
l5115
l5116
l5117
l5118
l5119
l5120
l5121
l5122
l5124
l5125
l5126
l5127
l5128
l5129
l5130
l5131
l5132
l5133
l5136
l5137
l5138
l5139
l5140
l5141
l5142
l5143
l5144
l5145
l5147
l5148
l5149
l5150
l5151
l5152
l5153
l5154
l5155
l5156
l5158
l5159
l5160
l5161
l5162
l5163
l5164
l5165
l5166
l5167
l5169
l5170
l5171
l5172
l5173
l5174
l5175
l5176
l5177
l5178
l5180
l5181
l5182
l5183
l5184
l5185
l5186
l5187
l5188
l5189
l5191
l5192
l5193
l5194
l5195
l5196
l5197
l5198
l5199
l5200
l5202
l5203
l5204
l5205
l5206
l5207
l5208
l5209
l5210
l5211
l5213
l5214
l5215
l5216
l5217
l5218
l5219
l5220
l5221
l5222
l5224
l5225
l5226
l5227
l5228
l5229
l5230
l5231
l5232
l5233
l5235
l5236
l5237
l5238
l5239
l5240
l5241
l5242
l5243
l5244
l5248
l5249
l5250
l5251
l5252
l5253
l5254
l5255
l5256
l5257
l5259
l5260
l5261
l5262
l5263
l5264
l5265
l5266
l5267
l5268
l5270
l5271
l5272
l5273
l5274
l5275
l5276
l5277
l5278
l5279
l5281
l5282
l5283
l5284
l5285
l5286
l5287
l5288
l5289
l5290
l5292
l5293
l5294
l5295
l5296
l5297
l5298
l5299
l5300
l5301
l5303
l5304
l5305
l5306
l5307
l5308
l5309
l5310
l5311
l5312
l5314
l5315
l5316
l5317
l5318
l5319
l5320
l5321
l5322
l5323
l5325
l5326
l5327
l5328
l5329
l5330
l5331
l5332
l5333
l5334
l5336
l5337
l5338
l5339
l5340
l5341
l5342
l5343
l5344
l5345
l5347
l5348
l5349
l5350
l5351
l5352
l5353
l5354
l5355
l5356
l5359
l5360
l5361
l5362
l5363
l5364
l5365
l5366
l5367
l5368
l5370
l5371
l5372
l5373
l5374
l5375
l5376
l5377
l5378
l5379
l5381
l5382
l5383
l5384
l5385
l5386
l5387
l5388
l5389
l5390
l5392
l5393
l5394
l5395
l5396
l5397
l5398
l5399
l5400
l5401
l5403
l5404
l5405
l5406
l5407
l5408
l5409
l5410
l5411
l5412
l5414
l5415
l5416
l5417
l5418
l5419
l5420
l5421
l5422
l5423
l5425
l5426
l5427
l5428
l5429
l5430
l5431
l5448
l5449
l5450
l5451
l5452
l5453
l5454
l5455
l5456
l5458
l5459
l5460
l5461
l5462
l5463
l5472
l5473
l5474
l5475
l5476
l5477
l5478
l5479
l5481
l5482
l5483
l5484
l5485
l5486
l5487
l5488
l5489
l5490
l5492
l5493
l5494
l5495
l5496
l5497
l5498
l5499
l5500
l5501
l5503
l5504
l5505
l5506
l5507
l5508
l5510
l5511
l5512
l5514
l5515
l5516
l5517
l5519
l5520
l5521
l5522
l5523
l5525
l5526
l5528
l5529
l5530
l5531
l5532
l5533
l5534
l5537
l5538
l5539
l5540
l5541
l5542
l5543
l5552
l5553
l5554
l5555
l2
l3
l4
l5
l6
l7
l8
l10
l11
l12
l13
l14
l15
l16
l17
l18
l19
l21
l22
l23
l24
l25
l26
l27
l28
l29
l30
l32
l33
l34
l35
l36
l37
l38
l39
l40
l41
l43
l44
l45
l46
l47
l48
l49
l50
l51
l52
l54
l55
l58
l61
l62
l63
l65
l66
l67
l68
l69
l70
l71
l72
l73
l74
l76
l77
l78
l79
l80
l81
l82
l83
l84
l85
l87
l88
l89
l90
l91
l92
l93
l94
l95
l96
l99
l100
l101
l102
l103
l104
l105
l107
l110
l111
l112
l113
l114
l115
l116
l117
l118
l119
l121
l122
l123
l124
l125
l126
l127
l128
l129
l130
l132
l133
l134
l135
l136
l137
l138
l139
l140
l141
l143
l144
l145
l146
l147
l148
l149
l150
l151
l152
l154
l155
l156
l157
l158
l159
l161
l165
l166
l167
l168
l169
l170
l171
l172
l173
l174
l176
l177
l178
l179
l180
l181
l182
l183
l184
l185
l187
l188
l189
l190
l194
l196
l198
l199
l200
l201
l202
l203
l204
l205
l206
l207
l210
l211
l212
l213
l214
l215
l216
l217
l218
l219
l221
l222
l223
l224
l225
l226
l227
l228
l229
l230
l232
l233
l234
l235
l236
l237
l238
l239
l240
l241
l243
l244
l245
l246
l247
l248
l249
l250
l251
l252
l254
l255
l256
l257
l258
l259
l260
l261
l262
l263
l265
l266
l267
l268
l269
l270
l271
l272
l273
l274
l276
l277
l278
l279
l280
l281
l282
l283
l284
l285
l290
l291
l292
l293
l294
l295
l296
l298
l299
l300
l301
l302
l303
l304
l305
l306
l307
l309
l310
l311
l312
l313
l314
l315
l316
l317
l318
l321
l322
l323
l324
l325
l326
l327
l328
l329
l330
l332
l333
l334
l335
l336
l337
l338
l339
l340
l341
l343
l344
l345
l346
l347
l348
l349
l350
l351
l352
l354
l355
l356
l357
l358
l359
l360
l361
l362
l363
l365
l366
l367
l368
l369
l370
l371
l372
l373
l374
l376
l377
l378
l379
l380
l381
l382
l383
l384
l385
l387
l388
l389
l390
l391
l392
l393
l394
l395
l396
l398
l399
l400
l401
l402
l403
l404
l405
l406
l407
l409
l410
l411
l412
l413
l414
l415
l416
l417
l418
l420
l421
l422
l423
l424
l425
l426
l427
l428
l429
l432
l433
l434
l435
l436
l437
l438
l439
l440
l441
l443
l444
l445
l446
l447
l448
l449
l450
l451
l452
l454
l455
l456
l457
l458
l459
l460
l461
l462
l463
l465
l466
l467
l468
l469
l470
l471
l472
l473
l474
l476
l477
l478
l479
l480
l481
l482
l483
l484
l485
l487
l488
l489
l490
l491
l492
l493
l494
l495
l496
l498
l499
l500
l501
l502
l503
l504
l505
l506
l507
l509
l510
l511
l512
l513
l514
l515
l516
l517
l518
l520
l521
l522
l523
l524
l525
l526
l527
l528
l529
l531
l532
l533
l534
l535
l536
l537
l538
l539
l540
l543
l544
l545
l546
l547
l548
l549
l550
l551
l552
l554
l555
l556
l557
l558
l559
l560
l561
l562
l563
l565
l566
l567
l568
l569
l570
l571
l572
l573
l574
l576
l577
l578
l579
l580
l581
l582
l583
l584
l585
l587
l588
l589
l590
l591
l592
l593
l594
l595
l596
l598
l599
l600
l601
l602
l603
l604
l605
l606
l607
l609
l610
l611
l612
l613
l614
l615
l616
l617
l618
l620
l621
l622
l623
l624
l625
l626
l627
l628
l629
l631
l632
l633
l634
l635
l636
l637
l638
l639
l640
l642
l643
l644
l645
l646
l647
l648
l649
l650
l651
l654
l655
l656
l657
l658
l659
l660
l661
l662
l663
l665
l666
l667
l668
l669
l670
l671
l672
l673
l674
l676
l677
l678
l679
l680
l681
l682
l683
l684
l685
l687
l688
l689
l690
l691
l692
l693
l694
l695
l696
l698
l699
l700
l701
l702
l703
l704
l705
l706
l707
l709
l710
l711
l712
l713
l714
l715
l716
l717
l718
l720
l721
l722
l723
l724
l725
l726
l727
l728
l729
l731
l732
l733
l734
l735
l736
l737
l738
l739
l740
l742
l743
l744
l745
l746
l747
l748
l749
l750
l751
l753
l754
l755
l756
l757
l758
l759
l760
l761
l762
l765
l766
l767
l768
l769
l770
l771
l772
l773
l774
l776
l777
l778
l779
l780
l781
l782
l783
l784
l785
l787
l788
l789
l790
l791
l792
l793
l794
l795
l796
l798
l799
l800
l801
l802
l803
l804
l805
l806
l807
l809
l810
l811
l812
l813
l814
l815
l816
l817
l818
l820
l821
l822
l823
l824
l825
l826
l827
l828
l829
l831
l832
l833
l834
l835
l836
l837
l838
l839
l840
l842
l843
l844
l845
l846
l847
l848
l849
l850
l851
l853
l854
l855
l856
l857
l858
l859
l860
l861
l862
l864
l865
l866
l867
l868
l869
l870
l871
l872
l873
l876
l877
l878
l879
l880
l881
l882
l883
l884
l885
l887
l888
l889
l890
l891
l892
l893
l894
l895
l896
l898
l899
l900
l901
l902
l903
l904
l905
l906
l907
l909
l910
l911
l912
l913
l914
l915
l916
l917
l918
l920
l921
l922
l923
l924
l925
l926
l927
l928
l930
l931
l932
l933
l934
l935
l936
l937
l938
l939
l941
l942
l943
l944
l945
l946
l947
l948
l949
l950
l952
l953
l954
l955
l956
l957
l958
l959
l960
l961
l963
l964
l965
l966
l967
l968
l969
l970
l971
l972
l974
l975
l976
l977
l978
l979
l980
l981
l982
l983
l986
l987
l988
l989
l990
l991
l992
l993
l994
l995
l997
l998
l999
l1000
l1001
l1002
l1003
l1004
l1005
l1006
l1008
l1009
l1010
l1011
l1012
l1013
l1014
l1015
l1016
l1017
l1019
l1020
l1021
l1022
The net has transition(s) that can never fire:
check for constant places
l2
l3
l4
l5
l6
l7
l8
l9
l10
l11
l12
l13
l14
l15
l16
l17
l18
l19
l20
l21
l22
l23
l24
l25
l26
l27
l28
l29
l30
l31
l32
l33
l34
l35
l36
l37
l38
l39
l40
l41
l42
l43
l44
l45
l46
l47
l48
l49
l50
l51
l52
l53
l54
l55
l58
l61
l62
l63
l64
l65
l66
l67
l68
l69
l70
l71
l72
l73
l74
l75
l76
l77
l78
l79
l80
l81
l82
l83
l84
l85
l86
l87
l88
l89
l90
l91
l92
l93
l94
l95
l96
l97
l98
l99
l100
l101
l102
l103
l104
l105
l107
l109
l110
l111
l112
l113
l114
l115
l116
l117
l118
l119
l120
l121
l122
l123
l124
l125
l126
l127
l128
l129
l130
l131
l132
l133
l134
l135
l136
l137
l138
l139
l140
l141
l142
l143
l144
l145
l146
l147
l148
l149
l150
l151
l152
l153
l154
l155
l156
l157
l158
l159
l161
l164
l165
l166
l167
l168
l169
l170
l171
l172
l173
l174
l175
l176
l177
l178
l179
l180
l181
l182
l183
l184
l185
l186
l187
l188
l189
l190
l194
l196
l197
l198
l199
l200
l201
l202
l203
l204
l205
l206
l207
l208
l209
l210
l211
l212
l213
l214
l215
l216
l217
l218
l219
l220
l221
l222
l223
l224
l225
l226
l227
l228
l229
l230
l231
l232
l233
l234
l235
l236
l237
l238
l239
l240
l241
l242
l243
l244
l245
l246
l247
l248
l249
l250
l251
l252
l253
l254
l255
l256
l257
l258
l259
l260
l261
l262
l263
l264
l265
l266
l267
l268
l269
l270
l271
l272
l273
l274
l276
l277
l278
l279
l280
l281
l282
l283
l284
l285
l290
l291
l292
l293
l294
l295
l296
l297
l298
l299
l300
l301
l302
l303
l304
l305
l306
l307
l308
l309
l310
l311
l312
l313
l314
l315
l316
l317
l318
l319
l320
l321
l322
l323
l324
l325
l326
l327
l328
l329
l330
l331
l332
l333
l334
l335
l336
l337
l338
l339
l340
l341
l342
l343
l344
l345
l346
l347
l348
l349
l350
l351
l352
l353
l354
l355
l356
l357
l358
l359
l360
l361
l362
l363
l364
l365
l366
l367
l368
l369
l370
l371
l372
l373
l374
l375
l376
l377
l378
l379
l380
l381
l382
l383
l384
l385
l386
l387
l388
l389
l390
l391
l392
l393
l394
l395
l396
l397
l398
l399
l400
l401
l402
l403
l404
l405
l406
l407
l408
l409
l410
l411
l412
l413
l414
l415
l416
l417
l418
l419
l420
l421
l422
l423
l424
l425
l426
l427
l428
l429
l430
l431
l432
l433
l434
l435
l436
l437
l438
l439
l440
l441
l442
l443
l444
l445
l446
l447
l448
l449
l450
l451
l452
l453
l454
l455
l456
l457
l458
l459
l460
l461
l462
l463
l464
l465
l466
l467
l468
l469
l470
l471
l472
l473
l474
l475
l476
l477
l478
l479
l480
l481
l482
l483
l484
l485
l486
l487
l488
l489
l490
l491
l492
l493
l494
l495
l496
l497
l498
l499
l500
l501
l502
l503
l504
l505
l506
l507
l508
l509
l510
l511
l512
l513
l514
l515
l516
l517
l518
l519
l520
l521
l522
l523
l524
l525
l526
l527
l528
l529
l530
l531
l532
l533
l534
l535
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found 4305 constant places
check if there are places and transitions
ok
check if there are transitions without pre-places
ok
check if at least one transition is enabled in m0
ok
check if there are transitions that can never fire
ok
initing FirstDep: 0m 0.011sec
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RingSingleMessageInMbox-PT-d1m020"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="marcie"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool marcie"
echo " Input is RingSingleMessageInMbox-PT-d1m020, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 1"
echo " Run identifier is r321-tall-167889192700850"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/RingSingleMessageInMbox-PT-d1m020.tgz
mv RingSingleMessageInMbox-PT-d1m020 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;