Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r308-tall-167873962200413.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is PolyORBNT-COL-S05J60, examination is StableMarking
Time confinement is 1800 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r308-tall-167873962200413
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 556K
-rw-r--r-- 1 mcc users 8.8K Feb 25 23:30 CTLCardinality.txt
-rw-r--r-- 1 mcc users 90K Feb 25 23:30 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.9K Feb 25 23:27 CTLFireability.txt
-rw-r--r-- 1 mcc users 61K Feb 25 23:27 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 4.0K Feb 25 16:36 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:36 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K Feb 25 16:36 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:36 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.5K Feb 25 23:41 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 81K Feb 25 23:41 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 23:38 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 89K Feb 25 23:38 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 16:36 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:36 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_pt
-rw-r--r-- 1 mcc users 7 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 94K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

FORMULA_NAME StableMarking

=== Now, execution of the tool begins

BK_START 1678884515893

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=StableMarking
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=1800
BK_INPUT=PolyORBNT-COL-S05J60
Not applying reductions.
Model is COL
StableMarking COL
starting LoLA
BK_INPUT PolyORBNT-COL-S05J60
BK_EXAMINATION: StableMarking
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
GlobalProperty: StableMarking

BK_STOP 1678884516469

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains High-Level net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Places: 969, Transitions: 2030
lola: @ trans NoJob
lola: @ trans fi1
lola: @ trans fi3
lola: @ trans trans_689
lola: @ trans DummyOR1
lola: @ trans fo3
lola: @ trans fi2
lola: @ trans trans_457
lola: @ trans WillPerformWork
lola: @ trans trans_461
lola: @ trans MustCheck
lola: @ trans trans_508
lola: @ trans trans_509
lola: @ trans trans_534
lola: @ trans fo2
lola: @ trans LeaveCSTCS
lola: @ trans trans_478
lola: @ trans trans_459
lola: @ trans trans_533
lola: @ trans trans_510
lola: @ trans GoPerformWork
lola: @ trans Run
lola: @ trans trans_685
lola: @ trans GoCheckSource
lola: @ trans fo1
lola: @ trans trans_486
lola: @ trans trans_511
lola: @ trans JobExist
lola: @ trans NotifyEventEndOfCheckSources
lola: @ trans EnterCSTCS
lola: @ trans trans_489
lola: @ trans IsEvt
lola: @ trans trans_463
lola: @ trans trans_776
lola: @ trans trans_488
lola: @ trans trans_487
lola: @ trans DummyOR2
lola: @ trans trans_376
lola: finished unfolding
lola: REM DEA TR: t = t1112
lola: REM DEA TR: t = t1113
lola: REM DEA TR: t = t1114
lola: REM DEA TR: t = t1115
lola: REM DEA TR: t = t1116
lola: REM DEA TR: t = t1117
lola: REM DEA TR: t = t1118
lola: REM DEA TR: t = t1119
lola: REM DEA TR: t = t1120
lola: REM DEA TR: t = t1121
lola: REM DEA TR: t = t1122
lola: REM DEA TR: t = t1123
lola: REM DEA TR: t = t1124
lola: REM DEA TR: t = t1125
lola: REM DEA TR: t = t1126
lola: REM DEA TR: t = t1127
lola: REM DEA TR: t = t1128
lola: REM DEA TR: t = t1129
lola: REM DEA TR: t = t1130
lola: REM DEA TR: t = t1131
lola: REM DEA TR: t = t1132
lola: REM DEA TR: t = t1133
lola: REM DEA TR: t = t1134
lola: REM DEA TR: t = t1135
lola: REM DEA TR: t = t1136
lola: REM DEA TR: t = t1137
lola: REM DEA TR: t = t1138
lola: REM DEA TR: t = t1139
lola: REM DEA TR: t = t1140
lola: REM DEA TR: t = t1141
lola: REM DEA TR: t = t1142
lola: REM DEA TR: t = t1143
lola: REM DEA TR: t = t1144
lola: REM DEA TR: t = t1145
lola: REM DEA TR: t = t1146
lola: REM DEA TR: t = t1147
lola: REM DEA TR: t = t1148
lola: REM DEA TR: t = t1149
lola: REM DEA TR: t = t1150
lola: REM DEA TR: t = t1151
lola: REM DEA TR: t = t1152
lola: REM DEA TR: t = t1153
lola: REM DEA TR: t = t1154
lola: REM DEA TR: t = t1155
lola: REM DEA TR: t = t1156
lola: REM DEA TR: t = t1157
lola: REM DEA TR: t = t1158
lola: REM DEA TR: t = t1159
lola: REM DEA TR: t = t1160
lola: REM DEA TR: t = t1161
lola: REM DEA TR: t = t1162
lola: REM DEA TR: t = t1163
lola: REM DEA TR: t = t1164
lola: REM DEA TR: t = t1165
lola: REM DEA TR: t = t1166
lola: REM DEA TR: t = t1167
lola: REM DEA TR: t = t1168
lola: REM DEA TR: t = t1169
lola: REM DEA TR: t = t1170
lola: REM DEA TR: t = t1171
lola: STATE EQUATION TRIES TRANSITION t312
lola: LAUNCH SYMM
sara: try reading problem file stateEquationProblem-QuasiLiveness-707.sara.
/home/mcc/BenchKit/bin//../lola/bin//../BenchKit_head.sh: line 63: 374 Segmentation fault lola --conf=$BIN_DIR/configfiles/globalconf --check=StableMarking $DIR/model.pnml
sara: place or transition ordering is non-deterministic

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PolyORBNT-COL-S05J60"
export BK_EXAMINATION="StableMarking"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="1800"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is PolyORBNT-COL-S05J60, examination is StableMarking"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r308-tall-167873962200413"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/PolyORBNT-COL-S05J60.tgz
mv PolyORBNT-COL-S05J60 execution
cd execution
if [ "StableMarking" = "ReachabilityDeadlock" ] || [ "StableMarking" = "UpperBounds" ] || [ "StableMarking" = "QuasiLiveness" ] || [ "StableMarking" = "StableMarking" ] || [ "StableMarking" = "Liveness" ] || [ "StableMarking" = "OneSafe" ] || [ "StableMarking" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "StableMarking" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "StableMarking" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "StableMarking.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property StableMarking.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "StableMarking.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' StableMarking.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "StableMarking" = "ReachabilityDeadlock" ] || [ "StableMarking" = "QuasiLiveness" ] || [ "StableMarking" = "StableMarking" ] || [ "StableMarking" = "Liveness" ] || [ "StableMarking" = "OneSafe" ] ; then
echo "FORMULA_NAME StableMarking"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;