About the Execution of LoLa+red for QuasiCertifProtocol-PT-10
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 2664.084 | 599628.00 | 595068.00 | 2927.40 | ???T?TTTFT?FT?T? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r295-tall-167873948500874.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is QuasiCertifProtocol-PT-10, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r295-tall-167873948500874
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1000K
-rw-r--r-- 1 mcc users 30K Feb 26 01:23 CTLCardinality.txt
-rw-r--r-- 1 mcc users 235K Feb 26 01:23 CTLCardinality.xml
-rw-r--r-- 1 mcc users 9.4K Feb 26 01:20 CTLFireability.txt
-rw-r--r-- 1 mcc users 68K Feb 26 01:20 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.8K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 6.3K Feb 25 16:37 LTLCardinality.txt
-rw-r--r-- 1 mcc users 37K Feb 25 16:37 LTLCardinality.xml
-rw-r--r-- 1 mcc users 4.6K Feb 25 16:37 LTLFireability.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:37 LTLFireability.xml
-rw-r--r-- 1 mcc users 35K Feb 26 01:25 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 262K Feb 26 01:25 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.7K Feb 26 01:24 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 63K Feb 26 01:24 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 16:37 UpperBounds.txt
-rw-r--r-- 1 mcc users 5.2K Feb 25 16:37 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 149K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME QuasiCertifProtocol-PT-10-CTLFireability-00
FORMULA_NAME QuasiCertifProtocol-PT-10-CTLFireability-01
FORMULA_NAME QuasiCertifProtocol-PT-10-CTLFireability-02
FORMULA_NAME QuasiCertifProtocol-PT-10-CTLFireability-03
FORMULA_NAME QuasiCertifProtocol-PT-10-CTLFireability-04
FORMULA_NAME QuasiCertifProtocol-PT-10-CTLFireability-05
FORMULA_NAME QuasiCertifProtocol-PT-10-CTLFireability-06
FORMULA_NAME QuasiCertifProtocol-PT-10-CTLFireability-07
FORMULA_NAME QuasiCertifProtocol-PT-10-CTLFireability-08
FORMULA_NAME QuasiCertifProtocol-PT-10-CTLFireability-09
FORMULA_NAME QuasiCertifProtocol-PT-10-CTLFireability-10
FORMULA_NAME QuasiCertifProtocol-PT-10-CTLFireability-11
FORMULA_NAME QuasiCertifProtocol-PT-10-CTLFireability-12
FORMULA_NAME QuasiCertifProtocol-PT-10-CTLFireability-13
FORMULA_NAME QuasiCertifProtocol-PT-10-CTLFireability-14
FORMULA_NAME QuasiCertifProtocol-PT-10-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678917309002
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=QuasiCertifProtocol-PT-10
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-15 21:55:10] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-15 21:55:10] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-15 21:55:10] [INFO ] Load time of PNML (sax parser for PT used): 56 ms
[2023-03-15 21:55:10] [INFO ] Transformed 550 places.
[2023-03-15 21:55:10] [INFO ] Transformed 176 transitions.
[2023-03-15 21:55:10] [INFO ] Parsed PT model containing 550 places and 176 transitions and 1287 arcs in 117 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 10 ms.
Support contains 502 out of 550 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 550/550 places, 176/176 transitions.
Reduce places removed 26 places and 0 transitions.
Iterating post reduction 0 with 26 rules applied. Total rules applied 26 place count 524 transition count 176
Applied a total of 26 rules in 15 ms. Remains 524 /550 variables (removed 26) and now considering 176/176 (removed 0) transitions.
// Phase 1: matrix 176 rows 524 cols
[2023-03-15 21:55:10] [INFO ] Computed 350 place invariants in 36 ms
[2023-03-15 21:55:11] [INFO ] Implicit Places using invariants in 411 ms returned []
[2023-03-15 21:55:11] [INFO ] Invariant cache hit.
[2023-03-15 21:55:11] [INFO ] Implicit Places using invariants and state equation in 256 ms returned []
Implicit Place search using SMT with State Equation took 695 ms to find 0 implicit places.
[2023-03-15 21:55:11] [INFO ] Invariant cache hit.
[2023-03-15 21:55:11] [INFO ] Dead Transitions using invariants and state equation in 198 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 524/550 places, 176/176 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 910 ms. Remains : 524/550 places, 176/176 transitions.
Support contains 502 out of 524 places after structural reductions.
[2023-03-15 21:55:11] [INFO ] Flatten gal took : 64 ms
[2023-03-15 21:55:11] [INFO ] Flatten gal took : 47 ms
[2023-03-15 21:55:12] [INFO ] Input system was already deterministic with 176 transitions.
Incomplete random walk after 10000 steps, including 691 resets, run finished after 449 ms. (steps per millisecond=22 ) properties (out of 58) seen :11
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 8 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 8 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 10 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 9 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 9 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 8 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1000 steps, including 8 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1000 steps, including 5 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 8 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1000 steps, including 8 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 8 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 8 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 9 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 9 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 8 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 9 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 8 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Running SMT prover for 47 properties.
[2023-03-15 21:55:12] [INFO ] Invariant cache hit.
[2023-03-15 21:55:13] [INFO ] [Real]Absence check using 0 positive and 350 generalized place invariants in 68 ms returned sat
[2023-03-15 21:55:13] [INFO ] After 677ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0 real:46
[2023-03-15 21:55:14] [INFO ] [Nat]Absence check using 0 positive and 350 generalized place invariants in 48 ms returned sat
[2023-03-15 21:55:16] [INFO ] After 1717ms SMT Verify possible using state equation in natural domain returned unsat :2 sat :45
[2023-03-15 21:55:18] [INFO ] After 3467ms SMT Verify possible using trap constraints in natural domain returned unsat :2 sat :45
Attempting to minimize the solution found.
Minimization took 1146 ms.
[2023-03-15 21:55:19] [INFO ] After 5541ms SMT Verify possible using all constraints in natural domain returned unsat :2 sat :45
Fused 47 Parikh solutions to 44 different solutions.
Finished Parikh walk after 83 steps, including 0 resets, run visited all 6 properties in 3 ms. (steps per millisecond=27 )
Parikh walk visited 45 properties in 39 ms.
Successfully simplified 2 atomic propositions for a total of 16 simplifications.
[2023-03-15 21:55:19] [INFO ] Flatten gal took : 28 ms
[2023-03-15 21:55:19] [INFO ] Flatten gal took : 27 ms
[2023-03-15 21:55:19] [INFO ] Input system was already deterministic with 176 transitions.
Computed a total of 524 stabilizing places and 176 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 524 transition count 176
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 1 formulas.
FORMULA QuasiCertifProtocol-PT-10-CTLFireability-05 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Starting structural reductions in LTL mode, iteration 0 : 524/524 places, 176/176 transitions.
Applied a total of 0 rules in 37 ms. Remains 524 /524 variables (removed 0) and now considering 176/176 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 37 ms. Remains : 524/524 places, 176/176 transitions.
[2023-03-15 21:55:19] [INFO ] Flatten gal took : 18 ms
[2023-03-15 21:55:19] [INFO ] Flatten gal took : 18 ms
[2023-03-15 21:55:19] [INFO ] Input system was already deterministic with 176 transitions.
Starting structural reductions in LTL mode, iteration 0 : 524/524 places, 176/176 transitions.
Applied a total of 0 rules in 9 ms. Remains 524 /524 variables (removed 0) and now considering 176/176 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 524/524 places, 176/176 transitions.
[2023-03-15 21:55:19] [INFO ] Flatten gal took : 17 ms
[2023-03-15 21:55:19] [INFO ] Flatten gal took : 18 ms
[2023-03-15 21:55:19] [INFO ] Input system was already deterministic with 176 transitions.
Starting structural reductions in LTL mode, iteration 0 : 524/524 places, 176/176 transitions.
Applied a total of 0 rules in 3 ms. Remains 524 /524 variables (removed 0) and now considering 176/176 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 524/524 places, 176/176 transitions.
[2023-03-15 21:55:19] [INFO ] Flatten gal took : 14 ms
[2023-03-15 21:55:19] [INFO ] Flatten gal took : 15 ms
[2023-03-15 21:55:19] [INFO ] Input system was already deterministic with 176 transitions.
Starting structural reductions in LTL mode, iteration 0 : 524/524 places, 176/176 transitions.
Applied a total of 0 rules in 7 ms. Remains 524 /524 variables (removed 0) and now considering 176/176 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 524/524 places, 176/176 transitions.
[2023-03-15 21:55:19] [INFO ] Flatten gal took : 13 ms
[2023-03-15 21:55:19] [INFO ] Flatten gal took : 14 ms
[2023-03-15 21:55:19] [INFO ] Input system was already deterministic with 176 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 524/524 places, 176/176 transitions.
Graph (complete) has 2161 edges and 524 vertex of which 512 are kept as prefixes of interest. Removing 12 places using SCC suffix rule.5 ms
Discarding 12 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Reduce places removed 1 places and 1 transitions.
Applied a total of 1 rules in 26 ms. Remains 511 /524 variables (removed 13) and now considering 173/176 (removed 3) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 26 ms. Remains : 511/524 places, 173/176 transitions.
[2023-03-15 21:55:19] [INFO ] Flatten gal took : 12 ms
[2023-03-15 21:55:19] [INFO ] Flatten gal took : 12 ms
[2023-03-15 21:55:19] [INFO ] Input system was already deterministic with 173 transitions.
Starting structural reductions in LTL mode, iteration 0 : 524/524 places, 176/176 transitions.
Applied a total of 0 rules in 3 ms. Remains 524 /524 variables (removed 0) and now considering 176/176 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 524/524 places, 176/176 transitions.
[2023-03-15 21:55:19] [INFO ] Flatten gal took : 12 ms
[2023-03-15 21:55:19] [INFO ] Flatten gal took : 13 ms
[2023-03-15 21:55:19] [INFO ] Input system was already deterministic with 176 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 524/524 places, 176/176 transitions.
Graph (complete) has 2161 edges and 524 vertex of which 512 are kept as prefixes of interest. Removing 12 places using SCC suffix rule.3 ms
Discarding 12 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Reduce places removed 1 places and 1 transitions.
Applied a total of 1 rules in 19 ms. Remains 511 /524 variables (removed 13) and now considering 173/176 (removed 3) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 19 ms. Remains : 511/524 places, 173/176 transitions.
[2023-03-15 21:55:19] [INFO ] Flatten gal took : 11 ms
[2023-03-15 21:55:19] [INFO ] Flatten gal took : 12 ms
[2023-03-15 21:55:19] [INFO ] Input system was already deterministic with 173 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 524/524 places, 176/176 transitions.
Graph (complete) has 2161 edges and 524 vertex of which 512 are kept as prefixes of interest. Removing 12 places using SCC suffix rule.3 ms
Discarding 12 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Applied a total of 1 rules in 18 ms. Remains 512 /524 variables (removed 12) and now considering 174/176 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 18 ms. Remains : 512/524 places, 174/176 transitions.
[2023-03-15 21:55:20] [INFO ] Flatten gal took : 11 ms
[2023-03-15 21:55:20] [INFO ] Flatten gal took : 12 ms
[2023-03-15 21:55:20] [INFO ] Input system was already deterministic with 174 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 524/524 places, 176/176 transitions.
Graph (complete) has 2161 edges and 524 vertex of which 512 are kept as prefixes of interest. Removing 12 places using SCC suffix rule.3 ms
Discarding 12 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Reduce places removed 1 places and 1 transitions.
Applied a total of 1 rules in 17 ms. Remains 511 /524 variables (removed 13) and now considering 173/176 (removed 3) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 17 ms. Remains : 511/524 places, 173/176 transitions.
[2023-03-15 21:55:20] [INFO ] Flatten gal took : 11 ms
[2023-03-15 21:55:20] [INFO ] Flatten gal took : 10 ms
[2023-03-15 21:55:20] [INFO ] Input system was already deterministic with 173 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 524/524 places, 176/176 transitions.
Graph (complete) has 2161 edges and 524 vertex of which 512 are kept as prefixes of interest. Removing 12 places using SCC suffix rule.2 ms
Discarding 12 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Reduce places removed 1 places and 1 transitions.
Applied a total of 1 rules in 15 ms. Remains 511 /524 variables (removed 13) and now considering 173/176 (removed 3) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 19 ms. Remains : 511/524 places, 173/176 transitions.
[2023-03-15 21:55:20] [INFO ] Flatten gal took : 12 ms
[2023-03-15 21:55:20] [INFO ] Flatten gal took : 12 ms
[2023-03-15 21:55:20] [INFO ] Input system was already deterministic with 173 transitions.
Starting structural reductions in LTL mode, iteration 0 : 524/524 places, 176/176 transitions.
Applied a total of 0 rules in 6 ms. Remains 524 /524 variables (removed 0) and now considering 176/176 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 524/524 places, 176/176 transitions.
[2023-03-15 21:55:20] [INFO ] Flatten gal took : 11 ms
[2023-03-15 21:55:20] [INFO ] Flatten gal took : 11 ms
[2023-03-15 21:55:20] [INFO ] Input system was already deterministic with 176 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 524/524 places, 176/176 transitions.
Graph (complete) has 2161 edges and 524 vertex of which 357 are kept as prefixes of interest. Removing 167 places using SCC suffix rule.2 ms
Discarding 167 places :
Also discarding 25 output transitions
Drop transitions removed 25 transitions
Reduce places removed 1 places and 1 transitions.
Ensure Unique test removed 22 transitions
Reduce isomorphic transitions removed 22 transitions.
Iterating post reduction 0 with 22 rules applied. Total rules applied 23 place count 356 transition count 128
Applied a total of 23 rules in 13 ms. Remains 356 /524 variables (removed 168) and now considering 128/176 (removed 48) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 14 ms. Remains : 356/524 places, 128/176 transitions.
[2023-03-15 21:55:20] [INFO ] Flatten gal took : 7 ms
[2023-03-15 21:55:20] [INFO ] Flatten gal took : 7 ms
[2023-03-15 21:55:20] [INFO ] Input system was already deterministic with 128 transitions.
Finished random walk after 729 steps, including 43 resets, run visited all 1 properties in 4 ms. (steps per millisecond=182 )
FORMULA QuasiCertifProtocol-PT-10-CTLFireability-12 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 524/524 places, 176/176 transitions.
Applied a total of 0 rules in 9 ms. Remains 524 /524 variables (removed 0) and now considering 176/176 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 524/524 places, 176/176 transitions.
[2023-03-15 21:55:20] [INFO ] Flatten gal took : 12 ms
[2023-03-15 21:55:20] [INFO ] Flatten gal took : 12 ms
[2023-03-15 21:55:20] [INFO ] Input system was already deterministic with 176 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 524/524 places, 176/176 transitions.
Graph (complete) has 2161 edges and 524 vertex of which 512 are kept as prefixes of interest. Removing 12 places using SCC suffix rule.1 ms
Discarding 12 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Reduce places removed 1 places and 1 transitions.
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 511 transition count 173
Applied a total of 2 rules in 29 ms. Remains 511 /524 variables (removed 13) and now considering 173/176 (removed 3) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 30 ms. Remains : 511/524 places, 173/176 transitions.
[2023-03-15 21:55:20] [INFO ] Flatten gal took : 11 ms
[2023-03-15 21:55:20] [INFO ] Flatten gal took : 11 ms
[2023-03-15 21:55:20] [INFO ] Input system was already deterministic with 173 transitions.
Starting structural reductions in LTL mode, iteration 0 : 524/524 places, 176/176 transitions.
Applied a total of 0 rules in 6 ms. Remains 524 /524 variables (removed 0) and now considering 176/176 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 524/524 places, 176/176 transitions.
[2023-03-15 21:55:20] [INFO ] Flatten gal took : 10 ms
[2023-03-15 21:55:20] [INFO ] Flatten gal took : 10 ms
[2023-03-15 21:55:20] [INFO ] Input system was already deterministic with 176 transitions.
[2023-03-15 21:55:20] [INFO ] Flatten gal took : 14 ms
[2023-03-15 21:55:20] [INFO ] Flatten gal took : 14 ms
[2023-03-15 21:55:20] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 8 ms.
[2023-03-15 21:55:20] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 524 places, 176 transitions and 1182 arcs took 2 ms.
Total runtime 10203 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT QuasiCertifProtocol-PT-10
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability
FORMULA QuasiCertifProtocol-PT-10-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA QuasiCertifProtocol-PT-10-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA QuasiCertifProtocol-PT-10-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA QuasiCertifProtocol-PT-10-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA QuasiCertifProtocol-PT-10-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA QuasiCertifProtocol-PT-10-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA QuasiCertifProtocol-PT-10-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678917908630
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ perl -pe 's/.*\.//g'
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 47 (type SKEL/FNDP) for 24 QuasiCertifProtocol-PT-10-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 48 (type SKEL/EQUN) for 24 QuasiCertifProtocol-PT-10-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 49 (type SKEL/SRCH) for 24 QuasiCertifProtocol-PT-10-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 50 (type SKEL/SRCH) for 24 QuasiCertifProtocol-PT-10-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 50 (type SKEL/SRCH) for QuasiCertifProtocol-PT-10-CTLFireability-09
lola: result : unknown
lola: markings : 11
lola: fired transitions : 11
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 47 (type SKEL/FNDP) for QuasiCertifProtocol-PT-10-CTLFireability-09
lola: result : true
lola: fired transitions : 27
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 48 (type EQUN) for QuasiCertifProtocol-PT-10-CTLFireability-09 (obsolete)
lola: CANCELED task # 49 (type SRCH) for QuasiCertifProtocol-PT-10-CTLFireability-09 (obsolete)
sara: try reading problem file /home/mcc/execution/374/CTLFireability-48.sara.
lola: LAUNCH task # 4 (type EXCL) for 3 QuasiCertifProtocol-PT-10-CTLFireability-01
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 51 (type FNDP) for 24 QuasiCertifProtocol-PT-10-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 52 (type EQUN) for 24 QuasiCertifProtocol-PT-10-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 54 (type SRCH) for 24 QuasiCertifProtocol-PT-10-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 54 (type SRCH) for QuasiCertifProtocol-PT-10-CTLFireability-09
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: FINISHED task # 48 (type SKEL/EQUN) for QuasiCertifProtocol-PT-10-CTLFireability-09
lola: result : true
lola: FINISHED task # 51 (type FNDP) for QuasiCertifProtocol-PT-10-CTLFireability-09
lola: result : true
lola: fired transitions : 11
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 52 (type EQUN) for QuasiCertifProtocol-PT-10-CTLFireability-09 (obsolete)
lola: Created skeleton in 0.000000 secs.
lola: planning for (null) stopped (result already fixed).
lola: FINISHED task # 52 (type EQUN) for QuasiCertifProtocol-PT-10-CTLFireability-09
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-PT-10-CTLFireability-09: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-PT-10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-08: SP ACTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/276 4/32 QuasiCertifProtocol-PT-10-CTLFireability-01 650675 m, 130135 m/sec, 3411951 t fired, .
Time elapsed: 7 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 14
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QuasiCertifProtocol-PT-10-CTLFireability-09: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-PT-10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
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QuasiCertifProtocol-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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QuasiCertifProtocol-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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QuasiCertifProtocol-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-08: SP ACTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/276 8/32 QuasiCertifProtocol-PT-10-CTLFireability-01 1228238 m, 115512 m/sec, 6904073 t fired, .
Time elapsed: 12 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-PT-10-CTLFireability-09: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-PT-10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-08: SP ACTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/276 10/32 QuasiCertifProtocol-PT-10-CTLFireability-01 1612022 m, 76756 m/sec, 10267031 t fired, .
Time elapsed: 17 secs. Pages in use: 10
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-PT-10-CTLFireability-09: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-PT-10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
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QuasiCertifProtocol-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-08: SP ACTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
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QuasiCertifProtocol-PT-10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 20/276 12/32 QuasiCertifProtocol-PT-10-CTLFireability-01 1942569 m, 66109 m/sec, 13563493 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-PT-10-CTLFireability-09: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-PT-10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-10-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="QuasiCertifProtocol-PT-10"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is QuasiCertifProtocol-PT-10, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r295-tall-167873948500874"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/QuasiCertifProtocol-PT-10.tgz
mv QuasiCertifProtocol-PT-10 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;