About the Execution of LoLa+red for QuasiCertifProtocol-COL-06
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 991.964 | 108393.00 | 117921.00 | 591.00 | TTTTFTFTFTFFFFTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r295-tall-167873948400810.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...............................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is QuasiCertifProtocol-COL-06, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r295-tall-167873948400810
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 564K
-rw-r--r-- 1 mcc users 7.6K Feb 26 01:28 CTLCardinality.txt
-rw-r--r-- 1 mcc users 82K Feb 26 01:28 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.5K Feb 26 01:27 CTLFireability.txt
-rw-r--r-- 1 mcc users 59K Feb 26 01:27 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.8K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 16:37 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Feb 25 16:37 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 16:37 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 16:37 LTLFireability.xml
-rw-r--r-- 1 mcc users 16K Feb 26 01:31 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 171K Feb 26 01:31 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.2K Feb 26 01:30 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 53K Feb 26 01:30 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 16:37 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:37 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_pt
-rw-r--r-- 1 mcc users 3 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 61K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME QuasiCertifProtocol-COL-06-CTLFireability-00
FORMULA_NAME QuasiCertifProtocol-COL-06-CTLFireability-01
FORMULA_NAME QuasiCertifProtocol-COL-06-CTLFireability-02
FORMULA_NAME QuasiCertifProtocol-COL-06-CTLFireability-03
FORMULA_NAME QuasiCertifProtocol-COL-06-CTLFireability-04
FORMULA_NAME QuasiCertifProtocol-COL-06-CTLFireability-05
FORMULA_NAME QuasiCertifProtocol-COL-06-CTLFireability-06
FORMULA_NAME QuasiCertifProtocol-COL-06-CTLFireability-07
FORMULA_NAME QuasiCertifProtocol-COL-06-CTLFireability-08
FORMULA_NAME QuasiCertifProtocol-COL-06-CTLFireability-09
FORMULA_NAME QuasiCertifProtocol-COL-06-CTLFireability-10
FORMULA_NAME QuasiCertifProtocol-COL-06-CTLFireability-11
FORMULA_NAME QuasiCertifProtocol-COL-06-CTLFireability-12
FORMULA_NAME QuasiCertifProtocol-COL-06-CTLFireability-13
FORMULA_NAME QuasiCertifProtocol-COL-06-CTLFireability-14
FORMULA_NAME QuasiCertifProtocol-COL-06-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678912484111
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=QuasiCertifProtocol-COL-06
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-15 20:34:45] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-15 20:34:45] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-15 20:34:45] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-15 20:34:45] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-15 20:34:46] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 684 ms
[2023-03-15 20:34:46] [INFO ] Imported 30 HL places and 26 HL transitions for a total of 270 PT places and 116.0 transition bindings in 14 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 13 ms.
[2023-03-15 20:34:46] [INFO ] Built PT skeleton of HLPN with 30 places and 26 transitions 77 arcs in 4 ms.
[2023-03-15 20:34:46] [INFO ] Skeletonized 16 HLPN properties in 2 ms.
Computed a total of 30 stabilizing places and 26 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 30 transition count 26
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 9 formulas.
FORMULA QuasiCertifProtocol-COL-06-CTLFireability-06 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA QuasiCertifProtocol-COL-06-CTLFireability-11 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Remains 11 properties that can be checked using skeleton over-approximation.
Computed a total of 30 stabilizing places and 26 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 30 transition count 26
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
Incomplete random walk after 10003 steps, including 752 resets, run finished after 187 ms. (steps per millisecond=53 ) properties (out of 27) seen :23
Incomplete Best-First random walk after 10000 steps, including 262 resets, run finished after 52 ms. (steps per millisecond=192 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 264 resets, run finished after 38 ms. (steps per millisecond=263 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 261 resets, run finished after 39 ms. (steps per millisecond=256 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 262 resets, run finished after 35 ms. (steps per millisecond=285 ) properties (out of 4) seen :0
Running SMT prover for 4 properties.
// Phase 1: matrix 26 rows 30 cols
[2023-03-15 20:34:46] [INFO ] Computed 5 place invariants in 3 ms
[2023-03-15 20:34:46] [INFO ] [Real]Absence check using 5 positive place invariants in 3 ms returned sat
[2023-03-15 20:34:46] [INFO ] After 166ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:4
[2023-03-15 20:34:46] [INFO ] [Nat]Absence check using 5 positive place invariants in 2 ms returned sat
[2023-03-15 20:34:46] [INFO ] After 27ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :4
[2023-03-15 20:34:46] [INFO ] After 45ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :4
Attempting to minimize the solution found.
Minimization took 11 ms.
[2023-03-15 20:34:46] [INFO ] After 111ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :4
Fused 4 Parikh solutions to 3 different solutions.
Finished Parikh walk after 24 steps, including 0 resets, run visited all 2 properties in 1 ms. (steps per millisecond=24 )
Parikh walk visited 4 properties in 3 ms.
[2023-03-15 20:34:47] [INFO ] Initial state reduction rules for CTL removed 2 formulas.
[2023-03-15 20:34:47] [INFO ] Flatten gal took : 32 ms
FORMULA QuasiCertifProtocol-COL-06-CTLFireability-09 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA QuasiCertifProtocol-COL-06-CTLFireability-04 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-15 20:34:47] [INFO ] Flatten gal took : 4 ms
Domain [tsid(7), tsid(7)] of place n9 breaks symmetries in sort tsid
[2023-03-15 20:34:47] [INFO ] Unfolded HLPN to a Petri net with 270 places and 116 transitions 659 arcs in 9 ms.
[2023-03-15 20:34:47] [INFO ] Unfolded 12 HLPN properties in 1 ms.
Support contains 252 out of 270 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 270/270 places, 116/116 transitions.
Reduce places removed 18 places and 0 transitions.
Iterating post reduction 0 with 18 rules applied. Total rules applied 18 place count 252 transition count 116
Applied a total of 18 rules in 7 ms. Remains 252 /270 variables (removed 18) and now considering 116/116 (removed 0) transitions.
// Phase 1: matrix 116 rows 252 cols
[2023-03-15 20:34:47] [INFO ] Computed 138 place invariants in 18 ms
[2023-03-15 20:34:47] [INFO ] Implicit Places using invariants in 86 ms returned []
[2023-03-15 20:34:47] [INFO ] Invariant cache hit.
[2023-03-15 20:34:47] [INFO ] Implicit Places using invariants and state equation in 115 ms returned []
Implicit Place search using SMT with State Equation took 205 ms to find 0 implicit places.
[2023-03-15 20:34:47] [INFO ] Invariant cache hit.
[2023-03-15 20:34:47] [INFO ] Dead Transitions using invariants and state equation in 102 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 252/270 places, 116/116 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 316 ms. Remains : 252/270 places, 116/116 transitions.
Support contains 252 out of 252 places after structural reductions.
[2023-03-15 20:34:47] [INFO ] Flatten gal took : 22 ms
[2023-03-15 20:34:47] [INFO ] Flatten gal took : 24 ms
[2023-03-15 20:34:47] [INFO ] Input system was already deterministic with 116 transitions.
Incomplete random walk after 10000 steps, including 981 resets, run finished after 229 ms. (steps per millisecond=43 ) properties (out of 42) seen :11
Incomplete Best-First random walk after 1001 steps, including 18 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 11 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 11 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 17 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 18 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 16 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 18 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 10 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 10 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1000 steps, including 11 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 18 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 11 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 20 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 18 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 11 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 31) seen :1
Incomplete Best-First random walk after 1001 steps, including 11 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1001 steps, including 11 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1001 steps, including 22 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1001 steps, including 10 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1001 steps, including 10 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1001 steps, including 10 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1001 steps, including 16 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1001 steps, including 10 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1001 steps, including 16 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1000 steps, including 18 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1001 steps, including 16 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1001 steps, including 10 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1000 steps, including 18 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1001 steps, including 17 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1001 steps, including 11 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1001 steps, including 10 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 30) seen :0
Running SMT prover for 30 properties.
[2023-03-15 20:34:48] [INFO ] Invariant cache hit.
[2023-03-15 20:34:48] [INFO ] [Real]Absence check using 0 positive and 138 generalized place invariants in 20 ms returned sat
[2023-03-15 20:34:48] [INFO ] After 260ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:30
[2023-03-15 20:34:48] [INFO ] [Nat]Absence check using 0 positive and 138 generalized place invariants in 20 ms returned sat
[2023-03-15 20:34:49] [INFO ] After 769ms SMT Verify possible using state equation in natural domain returned unsat :5 sat :25
[2023-03-15 20:34:50] [INFO ] After 1519ms SMT Verify possible using trap constraints in natural domain returned unsat :5 sat :25
Attempting to minimize the solution found.
Minimization took 468 ms.
[2023-03-15 20:34:50] [INFO ] After 2319ms SMT Verify possible using all constraints in natural domain returned unsat :5 sat :25
Fused 30 Parikh solutions to 25 different solutions.
Finished Parikh walk after 54 steps, including 0 resets, run visited all 14 properties in 4 ms. (steps per millisecond=13 )
Parikh walk visited 25 properties in 10 ms.
Successfully simplified 5 atomic propositions for a total of 12 simplifications.
[2023-03-15 20:34:50] [INFO ] Flatten gal took : 15 ms
[2023-03-15 20:34:50] [INFO ] Flatten gal took : 16 ms
[2023-03-15 20:34:50] [INFO ] Input system was already deterministic with 116 transitions.
Computed a total of 252 stabilizing places and 116 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 252 transition count 116
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
Starting structural reductions in LTL mode, iteration 0 : 252/252 places, 116/116 transitions.
Applied a total of 0 rules in 10 ms. Remains 252 /252 variables (removed 0) and now considering 116/116 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10 ms. Remains : 252/252 places, 116/116 transitions.
[2023-03-15 20:34:50] [INFO ] Flatten gal took : 10 ms
[2023-03-15 20:34:50] [INFO ] Flatten gal took : 11 ms
[2023-03-15 20:34:50] [INFO ] Input system was already deterministic with 116 transitions.
Starting structural reductions in LTL mode, iteration 0 : 252/252 places, 116/116 transitions.
Applied a total of 0 rules in 15 ms. Remains 252 /252 variables (removed 0) and now considering 116/116 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 15 ms. Remains : 252/252 places, 116/116 transitions.
[2023-03-15 20:34:50] [INFO ] Flatten gal took : 9 ms
[2023-03-15 20:34:50] [INFO ] Flatten gal took : 10 ms
[2023-03-15 20:34:50] [INFO ] Input system was already deterministic with 116 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 252/252 places, 116/116 transitions.
Graph (complete) has 733 edges and 252 vertex of which 244 are kept as prefixes of interest. Removing 8 places using SCC suffix rule.2 ms
Discarding 8 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Reduce places removed 1 places and 1 transitions.
Applied a total of 1 rules in 12 ms. Remains 243 /252 variables (removed 9) and now considering 113/116 (removed 3) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 12 ms. Remains : 243/252 places, 113/116 transitions.
[2023-03-15 20:34:51] [INFO ] Flatten gal took : 8 ms
[2023-03-15 20:34:51] [INFO ] Flatten gal took : 8 ms
[2023-03-15 20:34:51] [INFO ] Input system was already deterministic with 113 transitions.
Starting structural reductions in LTL mode, iteration 0 : 252/252 places, 116/116 transitions.
Applied a total of 0 rules in 4 ms. Remains 252 /252 variables (removed 0) and now considering 116/116 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 252/252 places, 116/116 transitions.
[2023-03-15 20:34:51] [INFO ] Flatten gal took : 8 ms
[2023-03-15 20:34:51] [INFO ] Flatten gal took : 10 ms
[2023-03-15 20:34:51] [INFO ] Input system was already deterministic with 116 transitions.
Starting structural reductions in LTL mode, iteration 0 : 252/252 places, 116/116 transitions.
Applied a total of 0 rules in 2 ms. Remains 252 /252 variables (removed 0) and now considering 116/116 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 252/252 places, 116/116 transitions.
[2023-03-15 20:34:51] [INFO ] Flatten gal took : 9 ms
[2023-03-15 20:34:51] [INFO ] Flatten gal took : 10 ms
[2023-03-15 20:34:51] [INFO ] Input system was already deterministic with 116 transitions.
Starting structural reductions in LTL mode, iteration 0 : 252/252 places, 116/116 transitions.
Applied a total of 0 rules in 5 ms. Remains 252 /252 variables (removed 0) and now considering 116/116 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 252/252 places, 116/116 transitions.
[2023-03-15 20:34:51] [INFO ] Flatten gal took : 8 ms
[2023-03-15 20:34:51] [INFO ] Flatten gal took : 8 ms
[2023-03-15 20:34:51] [INFO ] Input system was already deterministic with 116 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 252/252 places, 116/116 transitions.
Graph (complete) has 733 edges and 252 vertex of which 244 are kept as prefixes of interest. Removing 8 places using SCC suffix rule.1 ms
Discarding 8 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Reduce places removed 1 places and 1 transitions.
Applied a total of 1 rules in 7 ms. Remains 243 /252 variables (removed 9) and now considering 113/116 (removed 3) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 7 ms. Remains : 243/252 places, 113/116 transitions.
[2023-03-15 20:34:51] [INFO ] Flatten gal took : 6 ms
[2023-03-15 20:34:51] [INFO ] Flatten gal took : 7 ms
[2023-03-15 20:34:51] [INFO ] Input system was already deterministic with 113 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 252/252 places, 116/116 transitions.
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 1 place count 252 transition count 116
Applied a total of 1 rules in 14 ms. Remains 252 /252 variables (removed 0) and now considering 116/116 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 14 ms. Remains : 252/252 places, 116/116 transitions.
[2023-03-15 20:34:51] [INFO ] Flatten gal took : 7 ms
[2023-03-15 20:34:51] [INFO ] Flatten gal took : 7 ms
[2023-03-15 20:34:51] [INFO ] Input system was already deterministic with 116 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 252/252 places, 116/116 transitions.
Reduce places removed 1 places and 1 transitions.
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 1 place count 251 transition count 115
Applied a total of 1 rules in 15 ms. Remains 251 /252 variables (removed 1) and now considering 115/116 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 15 ms. Remains : 251/252 places, 115/116 transitions.
[2023-03-15 20:34:51] [INFO ] Flatten gal took : 6 ms
[2023-03-15 20:34:51] [INFO ] Flatten gal took : 7 ms
[2023-03-15 20:34:51] [INFO ] Input system was already deterministic with 115 transitions.
Starting structural reductions in LTL mode, iteration 0 : 252/252 places, 116/116 transitions.
Applied a total of 0 rules in 2 ms. Remains 252 /252 variables (removed 0) and now considering 116/116 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 252/252 places, 116/116 transitions.
[2023-03-15 20:34:51] [INFO ] Flatten gal took : 7 ms
[2023-03-15 20:34:51] [INFO ] Flatten gal took : 7 ms
[2023-03-15 20:34:51] [INFO ] Input system was already deterministic with 116 transitions.
Starting structural reductions in LTL mode, iteration 0 : 252/252 places, 116/116 transitions.
Applied a total of 0 rules in 1 ms. Remains 252 /252 variables (removed 0) and now considering 116/116 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 252/252 places, 116/116 transitions.
[2023-03-15 20:34:51] [INFO ] Flatten gal took : 7 ms
[2023-03-15 20:34:51] [INFO ] Flatten gal took : 7 ms
[2023-03-15 20:34:51] [INFO ] Input system was already deterministic with 116 transitions.
Starting structural reductions in LTL mode, iteration 0 : 252/252 places, 116/116 transitions.
Applied a total of 0 rules in 3 ms. Remains 252 /252 variables (removed 0) and now considering 116/116 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 252/252 places, 116/116 transitions.
[2023-03-15 20:34:51] [INFO ] Flatten gal took : 7 ms
[2023-03-15 20:34:51] [INFO ] Flatten gal took : 7 ms
[2023-03-15 20:34:51] [INFO ] Input system was already deterministic with 116 transitions.
[2023-03-15 20:34:51] [INFO ] Flatten gal took : 13 ms
[2023-03-15 20:34:51] [INFO ] Flatten gal took : 11 ms
[2023-03-15 20:34:51] [INFO ] Export to MCC of 12 properties in file /home/mcc/execution/CTLFireability.sr.xml took 8 ms.
[2023-03-15 20:34:51] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 252 places, 116 transitions and 590 arcs took 1 ms.
Total runtime 6001 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT QuasiCertifProtocol-COL-06
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/372
CTLFireability
FORMULA QuasiCertifProtocol-COL-06-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA QuasiCertifProtocol-COL-06-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA QuasiCertifProtocol-COL-06-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA QuasiCertifProtocol-COL-06-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA QuasiCertifProtocol-COL-06-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA QuasiCertifProtocol-COL-06-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA QuasiCertifProtocol-COL-06-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA QuasiCertifProtocol-COL-06-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA QuasiCertifProtocol-COL-06-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA QuasiCertifProtocol-COL-06-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA QuasiCertifProtocol-COL-06-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA QuasiCertifProtocol-COL-06-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678912592504
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/372/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/372/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/372/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 7 (type EXCL) for 6 QuasiCertifProtocol-COL-06-CTLFireability-02
lola: time limit : 199 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 7 (type EXCL) for QuasiCertifProtocol-COL-06-CTLFireability-02
lola: result : true
lola: markings : 27156
lola: fired transitions : 152816
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 38 (type EXCL) for 37 QuasiCertifProtocol-COL-06-CTLFireability-15
lola: time limit : 299 sec
lola: memory limit: 32 pages
lola: FINISHED task # 38 (type EXCL) for QuasiCertifProtocol-COL-06-CTLFireability-15
lola: result : true
lola: markings : 401656
lola: fired transitions : 3191684
lola: time used : 5.000000
lola: memory pages used : 3
lola: LAUNCH task # 35 (type EXCL) for 34 QuasiCertifProtocol-COL-06-CTLFireability-14
lola: time limit : 326 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-06-CTLFireability-02: CTL true CTL model checker
QuasiCertifProtocol-COL-06-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-08: F 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 0/326 1/32 QuasiCertifProtocol-COL-06-CTLFireability-14 1997 m, 399 m/sec, 9725 t fired, .
Time elapsed: 6 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-06-CTLFireability-02: CTL true CTL model checker
QuasiCertifProtocol-COL-06-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-08: F 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 5/326 3/32 QuasiCertifProtocol-COL-06-CTLFireability-14 562495 m, 112099 m/sec, 4789219 t fired, .
Time elapsed: 11 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-06-CTLFireability-02: CTL true CTL model checker
QuasiCertifProtocol-COL-06-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-08: F 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 10/326 5/32 QuasiCertifProtocol-COL-06-CTLFireability-14 1093256 m, 106152 m/sec, 9587878 t fired, .
Time elapsed: 16 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-06-CTLFireability-02: CTL true CTL model checker
QuasiCertifProtocol-COL-06-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-08: F 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 15/326 7/32 QuasiCertifProtocol-COL-06-CTLFireability-14 1569243 m, 95197 m/sec, 14270347 t fired, .
Time elapsed: 21 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-06-CTLFireability-02: CTL true CTL model checker
QuasiCertifProtocol-COL-06-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-08: F 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 20/326 10/32 QuasiCertifProtocol-COL-06-CTLFireability-14 2055892 m, 97329 m/sec, 18792042 t fired, .
Time elapsed: 26 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 12
lola: FINISHED task # 35 (type EXCL) for QuasiCertifProtocol-COL-06-CTLFireability-14
lola: result : true
lola: markings : 2196321
lola: fired transitions : 20060513
lola: time used : 21.000000
lola: memory pages used : 10
lola: LAUNCH task # 32 (type EXCL) for 31 QuasiCertifProtocol-COL-06-CTLFireability-13
lola: time limit : 357 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-06-CTLFireability-02: CTL true CTL model checker
QuasiCertifProtocol-COL-06-CTLFireability-14: CTL true CTL model checker
QuasiCertifProtocol-COL-06-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-08: F 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-06-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 4/357 3/32 QuasiCertifProtocol-COL-06-CTLFireability-13 527998 m, 105599 m/sec, 3428449 t fired, .
Time elapsed: 31 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-06-CTLFireability-02: CTL true CTL model checker
QuasiCertifProtocol-COL-06-CTLFireability-14: CTL true CTL model checker
QuasiCertifProtocol-COL-06-CTLFireability-15: CTL true CTL model checker
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="QuasiCertifProtocol-COL-06"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is QuasiCertifProtocol-COL-06, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r295-tall-167873948400810"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/QuasiCertifProtocol-COL-06.tgz
mv QuasiCertifProtocol-COL-06 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;