Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r295-tall-167873948400802.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
............................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is QuasiCertifProtocol-COL-02, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r295-tall-167873948400802
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 460K
-rw-r--r-- 1 mcc users 7.4K Feb 26 01:27 CTLCardinality.txt
-rw-r--r-- 1 mcc users 81K Feb 26 01:27 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.4K Feb 26 01:26 CTLFireability.txt
-rw-r--r-- 1 mcc users 46K Feb 26 01:26 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.8K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:36 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:36 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 16:37 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 16:37 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 26 01:29 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 115K Feb 26 01:29 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.5K Feb 26 01:28 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 46K Feb 26 01:28 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 16:37 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:37 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_pt
-rw-r--r-- 1 mcc users 3 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 34K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME QuasiCertifProtocol-COL-02-CTLFireability-00
FORMULA_NAME QuasiCertifProtocol-COL-02-CTLFireability-01
FORMULA_NAME QuasiCertifProtocol-COL-02-CTLFireability-02
FORMULA_NAME QuasiCertifProtocol-COL-02-CTLFireability-03
FORMULA_NAME QuasiCertifProtocol-COL-02-CTLFireability-04
FORMULA_NAME QuasiCertifProtocol-COL-02-CTLFireability-05
FORMULA_NAME QuasiCertifProtocol-COL-02-CTLFireability-06
FORMULA_NAME QuasiCertifProtocol-COL-02-CTLFireability-07
FORMULA_NAME QuasiCertifProtocol-COL-02-CTLFireability-08
FORMULA_NAME QuasiCertifProtocol-COL-02-CTLFireability-09
FORMULA_NAME QuasiCertifProtocol-COL-02-CTLFireability-10
FORMULA_NAME QuasiCertifProtocol-COL-02-CTLFireability-11
FORMULA_NAME QuasiCertifProtocol-COL-02-CTLFireability-12
FORMULA_NAME QuasiCertifProtocol-COL-02-CTLFireability-13
FORMULA_NAME QuasiCertifProtocol-COL-02-CTLFireability-14
FORMULA_NAME QuasiCertifProtocol-COL-02-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678912432100

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=QuasiCertifProtocol-COL-02
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-15 20:33:53] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-15 20:33:53] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-15 20:33:53] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-15 20:33:53] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-15 20:33:54] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 637 ms
[2023-03-15 20:33:54] [INFO ] Imported 30 HL places and 26 HL transitions for a total of 86 PT places and 56.0 transition bindings in 13 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 13 ms.
[2023-03-15 20:33:54] [INFO ] Built PT skeleton of HLPN with 30 places and 26 transitions 77 arcs in 3 ms.
[2023-03-15 20:33:54] [INFO ] Skeletonized 16 HLPN properties in 2 ms.
Initial state reduction rules removed 1 formulas.
FORMULA QuasiCertifProtocol-COL-02-CTLFireability-15 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Computed a total of 30 stabilizing places and 26 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 30 transition count 26
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 8 formulas.
FORMULA QuasiCertifProtocol-COL-02-CTLFireability-11 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA QuasiCertifProtocol-COL-02-CTLFireability-13 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Remains 10 properties that can be checked using skeleton over-approximation.
Initial state reduction rules removed 1 formulas.
FORMULA QuasiCertifProtocol-COL-02-CTLFireability-09 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Computed a total of 30 stabilizing places and 26 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 30 transition count 26
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
Incomplete random walk after 10000 steps, including 1327 resets, run finished after 360 ms. (steps per millisecond=27 ) properties (out of 26) seen :22
Incomplete Best-First random walk after 10001 steps, including 400 resets, run finished after 47 ms. (steps per millisecond=212 ) properties (out of 4) seen :1
Incomplete Best-First random walk after 10000 steps, including 450 resets, run finished after 45 ms. (steps per millisecond=222 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10000 steps, including 445 resets, run finished after 48 ms. (steps per millisecond=208 ) properties (out of 3) seen :0
Running SMT prover for 3 properties.
// Phase 1: matrix 26 rows 30 cols
[2023-03-15 20:33:54] [INFO ] Computed 5 place invariants in 6 ms
[2023-03-15 20:33:54] [INFO ] [Real]Absence check using 5 positive place invariants in 3 ms returned sat
[2023-03-15 20:33:54] [INFO ] After 181ms SMT Verify possible using all constraints in real domain returned unsat :2 sat :0 real:1
[2023-03-15 20:33:55] [INFO ] [Nat]Absence check using 5 positive place invariants in 5 ms returned sat
[2023-03-15 20:33:55] [INFO ] After 21ms SMT Verify possible using state equation in natural domain returned unsat :2 sat :1
[2023-03-15 20:33:55] [INFO ] After 30ms SMT Verify possible using trap constraints in natural domain returned unsat :2 sat :1
Attempting to minimize the solution found.
Minimization took 6 ms.
[2023-03-15 20:33:55] [INFO ] After 83ms SMT Verify possible using all constraints in natural domain returned unsat :2 sat :1
Fused 3 Parikh solutions to 1 different solutions.
Finished Parikh walk after 20 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=20 )
Parikh walk visited 1 properties in 2 ms.
Successfully simplified 2 atomic propositions for a total of 9 simplifications.
FORMULA QuasiCertifProtocol-COL-02-CTLFireability-01 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-15 20:33:55] [INFO ] Flatten gal took : 17 ms
[2023-03-15 20:33:55] [INFO ] Flatten gal took : 5 ms
Domain [tsid(3), tsid(3)] of place n9 breaks symmetries in sort tsid
[2023-03-15 20:33:55] [INFO ] Unfolded HLPN to a Petri net with 86 places and 56 transitions 223 arcs in 11 ms.
[2023-03-15 20:33:55] [INFO ] Unfolded 11 HLPN properties in 0 ms.
Support contains 76 out of 86 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 86/86 places, 56/56 transitions.
Reduce places removed 10 places and 0 transitions.
Iterating post reduction 0 with 10 rules applied. Total rules applied 10 place count 76 transition count 56
Applied a total of 10 rules in 6 ms. Remains 76 /86 variables (removed 10) and now considering 56/56 (removed 0) transitions.
// Phase 1: matrix 56 rows 76 cols
[2023-03-15 20:33:55] [INFO ] Computed 22 place invariants in 5 ms
[2023-03-15 20:33:55] [INFO ] Implicit Places using invariants in 50 ms returned []
[2023-03-15 20:33:55] [INFO ] Invariant cache hit.
[2023-03-15 20:33:55] [INFO ] Implicit Places using invariants and state equation in 65 ms returned []
Implicit Place search using SMT with State Equation took 119 ms to find 0 implicit places.
[2023-03-15 20:33:55] [INFO ] Invariant cache hit.
[2023-03-15 20:33:55] [INFO ] Dead Transitions using invariants and state equation in 63 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 76/86 places, 56/56 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 189 ms. Remains : 76/86 places, 56/56 transitions.
Support contains 76 out of 76 places after structural reductions.
[2023-03-15 20:33:55] [INFO ] Flatten gal took : 9 ms
[2023-03-15 20:33:55] [INFO ] Flatten gal took : 9 ms
[2023-03-15 20:33:55] [INFO ] Input system was already deterministic with 56 transitions.
Incomplete random walk after 10000 steps, including 1644 resets, run finished after 435 ms. (steps per millisecond=22 ) properties (out of 33) seen :12
Incomplete Best-First random walk after 1001 steps, including 58 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1001 steps, including 55 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1001 steps, including 24 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 21) seen :1
Incomplete Best-First random walk after 1001 steps, including 52 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 20) seen :0
Incomplete Best-First random walk after 1001 steps, including 56 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 20) seen :0
Incomplete Best-First random walk after 1001 steps, including 26 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 20) seen :2
Incomplete Best-First random walk after 1001 steps, including 36 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 29 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 54 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 24 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 26 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 25 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1000 steps, including 56 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 25 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 27 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1000 steps, including 55 resets, run finished after 13 ms. (steps per millisecond=76 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 55 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 26 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 18) seen :4
Running SMT prover for 14 properties.
[2023-03-15 20:33:56] [INFO ] Invariant cache hit.
[2023-03-15 20:33:56] [INFO ] [Real]Absence check using 0 positive and 22 generalized place invariants in 4 ms returned sat
[2023-03-15 20:33:56] [INFO ] After 93ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:14
[2023-03-15 20:33:56] [INFO ] [Nat]Absence check using 0 positive and 22 generalized place invariants in 3 ms returned sat
[2023-03-15 20:33:56] [INFO ] After 80ms SMT Verify possible using state equation in natural domain returned unsat :4 sat :10
[2023-03-15 20:33:56] [INFO ] After 157ms SMT Verify possible using trap constraints in natural domain returned unsat :4 sat :10
Attempting to minimize the solution found.
Minimization took 41 ms.
[2023-03-15 20:33:56] [INFO ] After 282ms SMT Verify possible using all constraints in natural domain returned unsat :4 sat :10
Fused 14 Parikh solutions to 9 different solutions.
Finished Parikh walk after 27 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=27 )
Parikh walk visited 10 properties in 1 ms.
Successfully simplified 4 atomic propositions for a total of 11 simplifications.
[2023-03-15 20:33:56] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-15 20:33:56] [INFO ] Flatten gal took : 7 ms
FORMULA QuasiCertifProtocol-COL-02-CTLFireability-05 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-15 20:33:56] [INFO ] Flatten gal took : 6 ms
[2023-03-15 20:33:56] [INFO ] Input system was already deterministic with 56 transitions.
Computed a total of 76 stabilizing places and 56 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 76 transition count 56
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 1 formulas.
Starting structural reductions in SI_CTL mode, iteration 0 : 76/76 places, 56/56 transitions.
Reduce places removed 1 places and 1 transitions.
Partial Post-agglomeration rule applied 2 times.
Drop transitions removed 2 transitions
Iterating global reduction 0 with 2 rules applied. Total rules applied 2 place count 75 transition count 55
Applied a total of 2 rules in 13 ms. Remains 75 /76 variables (removed 1) and now considering 55/56 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 13 ms. Remains : 75/76 places, 55/56 transitions.
[2023-03-15 20:33:56] [INFO ] Flatten gal took : 5 ms
[2023-03-15 20:33:56] [INFO ] Flatten gal took : 4 ms
[2023-03-15 20:33:56] [INFO ] Input system was already deterministic with 55 transitions.
Starting structural reductions in LTL mode, iteration 0 : 76/76 places, 56/56 transitions.
Applied a total of 0 rules in 1 ms. Remains 76 /76 variables (removed 0) and now considering 56/56 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 76/76 places, 56/56 transitions.
[2023-03-15 20:33:56] [INFO ] Flatten gal took : 4 ms
[2023-03-15 20:33:56] [INFO ] Flatten gal took : 4 ms
[2023-03-15 20:33:56] [INFO ] Input system was already deterministic with 56 transitions.
Starting structural reductions in LTL mode, iteration 0 : 76/76 places, 56/56 transitions.
Applied a total of 0 rules in 2 ms. Remains 76 /76 variables (removed 0) and now considering 56/56 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 76/76 places, 56/56 transitions.
[2023-03-15 20:33:56] [INFO ] Flatten gal took : 4 ms
[2023-03-15 20:33:56] [INFO ] Flatten gal took : 4 ms
[2023-03-15 20:33:56] [INFO ] Input system was already deterministic with 56 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 76/76 places, 56/56 transitions.
Graph (complete) has 137 edges and 76 vertex of which 72 are kept as prefixes of interest. Removing 4 places using SCC suffix rule.1 ms
Discarding 4 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 72 transition count 54
Applied a total of 2 rules in 7 ms. Remains 72 /76 variables (removed 4) and now considering 54/56 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 7 ms. Remains : 72/76 places, 54/56 transitions.
[2023-03-15 20:33:56] [INFO ] Flatten gal took : 4 ms
[2023-03-15 20:33:56] [INFO ] Flatten gal took : 4 ms
[2023-03-15 20:33:56] [INFO ] Input system was already deterministic with 54 transitions.
Starting structural reductions in LTL mode, iteration 0 : 76/76 places, 56/56 transitions.
Applied a total of 0 rules in 1 ms. Remains 76 /76 variables (removed 0) and now considering 56/56 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 76/76 places, 56/56 transitions.
[2023-03-15 20:33:56] [INFO ] Flatten gal took : 4 ms
[2023-03-15 20:33:56] [INFO ] Flatten gal took : 4 ms
[2023-03-15 20:33:56] [INFO ] Input system was already deterministic with 56 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 76/76 places, 56/56 transitions.
Graph (complete) has 137 edges and 76 vertex of which 72 are kept as prefixes of interest. Removing 4 places using SCC suffix rule.0 ms
Discarding 4 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Reduce places removed 1 places and 1 transitions.
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 71 transition count 53
Applied a total of 2 rules in 6 ms. Remains 71 /76 variables (removed 5) and now considering 53/56 (removed 3) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 7 ms. Remains : 71/76 places, 53/56 transitions.
[2023-03-15 20:33:56] [INFO ] Flatten gal took : 3 ms
[2023-03-15 20:33:56] [INFO ] Flatten gal took : 4 ms
[2023-03-15 20:33:56] [INFO ] Input system was already deterministic with 53 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 76/76 places, 56/56 transitions.
Graph (complete) has 137 edges and 76 vertex of which 72 are kept as prefixes of interest. Removing 4 places using SCC suffix rule.0 ms
Discarding 4 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 72 transition count 54
Applied a total of 2 rules in 5 ms. Remains 72 /76 variables (removed 4) and now considering 54/56 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 72/76 places, 54/56 transitions.
[2023-03-15 20:33:56] [INFO ] Flatten gal took : 3 ms
[2023-03-15 20:33:56] [INFO ] Flatten gal took : 3 ms
[2023-03-15 20:33:56] [INFO ] Input system was already deterministic with 54 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 76/76 places, 56/56 transitions.
Graph (complete) has 137 edges and 76 vertex of which 13 are kept as prefixes of interest. Removing 63 places using SCC suffix rule.0 ms
Discarding 63 places :
Also discarding 27 output transitions
Drop transitions removed 27 transitions
Reduce places removed 1 places and 1 transitions.
Ensure Unique test removed 18 transitions
Reduce isomorphic transitions removed 18 transitions.
Iterating post reduction 0 with 18 rules applied. Total rules applied 19 place count 12 transition count 10
Applied a total of 19 rules in 2 ms. Remains 12 /76 variables (removed 64) and now considering 10/56 (removed 46) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 12/76 places, 10/56 transitions.
[2023-03-15 20:33:56] [INFO ] Flatten gal took : 1 ms
[2023-03-15 20:33:56] [INFO ] Flatten gal took : 1 ms
[2023-03-15 20:33:56] [INFO ] Input system was already deterministic with 10 transitions.
Finished random walk after 139 steps, including 25 resets, run visited all 1 properties in 2 ms. (steps per millisecond=69 )
FORMULA QuasiCertifProtocol-COL-02-CTLFireability-10 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 76/76 places, 56/56 transitions.
Applied a total of 0 rules in 1 ms. Remains 76 /76 variables (removed 0) and now considering 56/56 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 76/76 places, 56/56 transitions.
[2023-03-15 20:33:56] [INFO ] Flatten gal took : 4 ms
[2023-03-15 20:33:56] [INFO ] Flatten gal took : 4 ms
[2023-03-15 20:33:56] [INFO ] Input system was already deterministic with 56 transitions.
Starting structural reductions in LTL mode, iteration 0 : 76/76 places, 56/56 transitions.
Applied a total of 0 rules in 1 ms. Remains 76 /76 variables (removed 0) and now considering 56/56 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 76/76 places, 56/56 transitions.
[2023-03-15 20:33:56] [INFO ] Flatten gal took : 4 ms
[2023-03-15 20:33:56] [INFO ] Flatten gal took : 3 ms
[2023-03-15 20:33:56] [INFO ] Input system was already deterministic with 56 transitions.
[2023-03-15 20:33:56] [INFO ] Flatten gal took : 5 ms
[2023-03-15 20:33:56] [INFO ] Flatten gal took : 4 ms
[2023-03-15 20:33:56] [INFO ] Export to MCC of 9 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-15 20:33:56] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 76 places, 56 transitions and 190 arcs took 0 ms.
Total runtime 3219 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT QuasiCertifProtocol-COL-02
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability

FORMULA QuasiCertifProtocol-COL-02-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-COL-02-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-COL-02-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-COL-02-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-COL-02-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-COL-02-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-COL-02-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-COL-02-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-COL-02-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678912437946

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ perl -pe 's/.*\.//g'
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:182
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 1 (type EXCL) for 0 QuasiCertifProtocol-COL-02-CTLFireability-00
lola: time limit : 360 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 1 (type EXCL) for QuasiCertifProtocol-COL-02-CTLFireability-00
lola: result : true
lola: markings : 7
lola: fired transitions : 6
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 QuasiCertifProtocol-COL-02-CTLFireability-04
lola: time limit : 400 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 10 (type EXCL) for QuasiCertifProtocol-COL-02-CTLFireability-04
lola: result : false
lola: markings : 27
lola: fired transitions : 54
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 QuasiCertifProtocol-COL-02-CTLFireability-06
lola: time limit : 450 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: FINISHED task # 13 (type EXCL) for QuasiCertifProtocol-COL-02-CTLFireability-06
lola: result : true
lola: markings : 260
lola: fired transitions : 409
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 7 (type EXCL) for 6 QuasiCertifProtocol-COL-02-CTLFireability-03
lola: time limit : 600 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 7 (type EXCL) for QuasiCertifProtocol-COL-02-CTLFireability-03
lola: result : false
lola: markings : 16
lola: fired transitions : 20
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 QuasiCertifProtocol-COL-02-CTLFireability-12
lola: time limit : 720 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for QuasiCertifProtocol-COL-02-CTLFireability-12
lola: result : true
lola: markings : 34
lola: fired transitions : 188
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 QuasiCertifProtocol-COL-02-CTLFireability-02
lola: time limit : 900 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for QuasiCertifProtocol-COL-02-CTLFireability-02
lola: result : false
lola: markings : 31
lola: fired transitions : 81
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 24 QuasiCertifProtocol-COL-02-CTLFireability-14
lola: time limit : 1200 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for QuasiCertifProtocol-COL-02-CTLFireability-14
lola: result : false
lola: markings : 27
lola: fired transitions : 48
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 QuasiCertifProtocol-COL-02-CTLFireability-07
lola: time limit : 1800 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for QuasiCertifProtocol-COL-02-CTLFireability-07
lola: result : true
lola: markings : 5
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 QuasiCertifProtocol-COL-02-CTLFireability-08
lola: time limit : 3600 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for QuasiCertifProtocol-COL-02-CTLFireability-08
lola: result : false
lola: markings : 33
lola: fired transitions : 68
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-02-CTLFireability-00: EG true state space / EG
QuasiCertifProtocol-COL-02-CTLFireability-02: CTL false CTL model checker
QuasiCertifProtocol-COL-02-CTLFireability-03: CTL false CTL model checker
QuasiCertifProtocol-COL-02-CTLFireability-04: CTL false CTL model checker
QuasiCertifProtocol-COL-02-CTLFireability-06: CTL true CTL model checker
QuasiCertifProtocol-COL-02-CTLFireability-07: EG true state space / EG
QuasiCertifProtocol-COL-02-CTLFireability-08: CTL false CTL model checker
QuasiCertifProtocol-COL-02-CTLFireability-12: CTL true CTL model checker
QuasiCertifProtocol-COL-02-CTLFireability-14: CTL false CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="QuasiCertifProtocol-COL-02"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is QuasiCertifProtocol-COL-02, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r295-tall-167873948400802"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/QuasiCertifProtocol-COL-02.tgz
mv QuasiCertifProtocol-COL-02 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;