fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r295-tall-167873947800402
Last Updated
May 14, 2023

About the Execution of LoLa+red for PolyORBLF-COL-S04J04T08

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
8066.191 807372.00 827828.00 2177.20 ?F????FFTFF????? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r295-tall-167873947800402.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is PolyORBLF-COL-S04J04T08, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r295-tall-167873947800402
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 540K
-rw-r--r-- 1 mcc users 5.8K Feb 26 14:26 CTLCardinality.txt
-rw-r--r-- 1 mcc users 48K Feb 26 14:26 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.7K Feb 26 14:24 CTLFireability.txt
-rw-r--r-- 1 mcc users 59K Feb 26 14:24 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.3K Feb 25 16:35 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:35 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 16:35 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 16:35 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.1K Feb 26 14:38 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 63K Feb 26 14:38 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 26 14:36 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 80K Feb 26 14:36 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 25 16:35 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:35 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_pt
-rw-r--r-- 1 mcc users 10 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 154K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME PolyORBLF-COL-S04J04T08-CTLFireability-00
FORMULA_NAME PolyORBLF-COL-S04J04T08-CTLFireability-01
FORMULA_NAME PolyORBLF-COL-S04J04T08-CTLFireability-02
FORMULA_NAME PolyORBLF-COL-S04J04T08-CTLFireability-03
FORMULA_NAME PolyORBLF-COL-S04J04T08-CTLFireability-04
FORMULA_NAME PolyORBLF-COL-S04J04T08-CTLFireability-05
FORMULA_NAME PolyORBLF-COL-S04J04T08-CTLFireability-06
FORMULA_NAME PolyORBLF-COL-S04J04T08-CTLFireability-07
FORMULA_NAME PolyORBLF-COL-S04J04T08-CTLFireability-08
FORMULA_NAME PolyORBLF-COL-S04J04T08-CTLFireability-09
FORMULA_NAME PolyORBLF-COL-S04J04T08-CTLFireability-10
FORMULA_NAME PolyORBLF-COL-S04J04T08-CTLFireability-11
FORMULA_NAME PolyORBLF-COL-S04J04T08-CTLFireability-12
FORMULA_NAME PolyORBLF-COL-S04J04T08-CTLFireability-13
FORMULA_NAME PolyORBLF-COL-S04J04T08-CTLFireability-14
FORMULA_NAME PolyORBLF-COL-S04J04T08-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678837008957

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=PolyORBLF-COL-S04J04T08
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-14 23:36:50] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-14 23:36:50] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-14 23:36:50] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-14 23:36:50] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-14 23:36:51] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 696 ms
[2023-03-14 23:36:51] [INFO ] Imported 81 HL places and 65 HL transitions for a total of 712 PT places and 4080.0 transition bindings in 22 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 14 ms.
[2023-03-14 23:36:51] [INFO ] Built PT skeleton of HLPN with 81 places and 65 transitions 254 arcs in 5 ms.
[2023-03-14 23:36:51] [INFO ] Skeletonized 12 HLPN properties in 2 ms. Removed 4 properties that had guard overlaps.
Computed a total of 0 stabilizing places and 0 stable transitions
Remains 12 properties that can be checked using skeleton over-approximation.
Computed a total of 0 stabilizing places and 0 stable transitions
Incomplete random walk after 10000 steps, including 2 resets, run finished after 310 ms. (steps per millisecond=32 ) properties (out of 49) seen :45
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 139 ms. (steps per millisecond=71 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 3 resets, run finished after 117 ms. (steps per millisecond=85 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10000 steps, including 3 resets, run finished after 97 ms. (steps per millisecond=103 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 88 ms. (steps per millisecond=113 ) properties (out of 4) seen :0
Running SMT prover for 4 properties.
[2023-03-14 23:36:51] [INFO ] Flow matrix only has 64 transitions (discarded 1 similar events)
// Phase 1: matrix 64 rows 81 cols
[2023-03-14 23:36:51] [INFO ] Computed 26 place invariants in 15 ms
[2023-03-14 23:36:52] [INFO ] [Real]Absence check using 11 positive place invariants in 7 ms returned sat
[2023-03-14 23:36:52] [INFO ] [Real]Absence check using 11 positive and 15 generalized place invariants in 4 ms returned sat
[2023-03-14 23:36:52] [INFO ] After 204ms SMT Verify possible using all constraints in real domain returned unsat :4 sat :0
Fused 4 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 4 atomic propositions for a total of 12 simplifications.
[2023-03-14 23:36:52] [INFO ] Flatten gal took : 32 ms
[2023-03-14 23:36:52] [INFO ] Flatten gal took : 9 ms
Transition T_2315 forces synchronizations/join behavior on parameter t of sort Threads
Transition GoPerformWork forces synchronizations/join behavior on parameter j of sort Jobs
Transition T_0376 forces synchronizations/join behavior on parameter s of sort Sources
[2023-03-14 23:36:52] [INFO ] Unfolded HLPN to a Petri net with 712 places and 4012 transitions 27744 arcs in 75 ms.
[2023-03-14 23:36:52] [INFO ] Unfolded 16 HLPN properties in 1 ms.
[2023-03-14 23:36:52] [INFO ] Reduced 1768 identical enabling conditions.
[2023-03-14 23:36:52] [INFO ] Reduced 352 identical enabling conditions.
[2023-03-14 23:36:52] [INFO ] Reduced 352 identical enabling conditions.
[2023-03-14 23:36:52] [INFO ] Reduced 352 identical enabling conditions.
[2023-03-14 23:36:52] [INFO ] Reduced 48 identical enabling conditions.
[2023-03-14 23:36:52] [INFO ] Reduced 352 identical enabling conditions.
Ensure Unique test removed 2168 transitions
Reduce redundant transitions removed 2168 transitions.
Support contains 591 out of 712 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 712/712 places, 1844/1844 transitions.
Applied a total of 0 rules in 37 ms. Remains 712 /712 variables (removed 0) and now considering 1844/1844 (removed 0) transitions.
[2023-03-14 23:36:52] [INFO ] Flow matrix only has 1812 transitions (discarded 32 similar events)
// Phase 1: matrix 1812 rows 712 cols
[2023-03-14 23:36:52] [INFO ] Computed 54 place invariants in 107 ms
[2023-03-14 23:36:53] [INFO ] Dead Transitions using invariants and state equation in 922 ms found 432 transitions.
Found 432 dead transitions using SMT.
Drop transitions removed 432 transitions
Dead transitions reduction (with SMT) triggered by suspicious arc values removed 432 transitions.
[2023-03-14 23:36:53] [INFO ] Flow matrix only has 1380 transitions (discarded 32 similar events)
// Phase 1: matrix 1380 rows 712 cols
[2023-03-14 23:36:53] [INFO ] Computed 54 place invariants in 46 ms
[2023-03-14 23:36:53] [INFO ] Implicit Places using invariants in 240 ms returned []
[2023-03-14 23:36:53] [INFO ] Flow matrix only has 1380 transitions (discarded 32 similar events)
[2023-03-14 23:36:53] [INFO ] Invariant cache hit.
[2023-03-14 23:36:54] [INFO ] State equation strengthened by 160 read => feed constraints.
[2023-03-14 23:36:54] [INFO ] Implicit Places using invariants and state equation in 869 ms returned []
Implicit Place search using SMT with State Equation took 1111 ms to find 0 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 712/712 places, 1412/1844 transitions.
Applied a total of 0 rules in 24 ms. Remains 712 /712 variables (removed 0) and now considering 1412/1412 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2096 ms. Remains : 712/712 places, 1412/1844 transitions.
Support contains 591 out of 712 places after structural reductions.
[2023-03-14 23:36:54] [INFO ] Flatten gal took : 152 ms
[2023-03-14 23:36:55] [INFO ] Flatten gal took : 123 ms
[2023-03-14 23:36:55] [INFO ] Input system was already deterministic with 1412 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 471 ms. (steps per millisecond=21 ) properties (out of 69) seen :60
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 177 ms. (steps per millisecond=56 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 202 ms. (steps per millisecond=49 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 155 ms. (steps per millisecond=64 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 290 ms. (steps per millisecond=34 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 126 ms. (steps per millisecond=79 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 136 ms. (steps per millisecond=73 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 187 ms. (steps per millisecond=53 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 165 ms. (steps per millisecond=60 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 163 ms. (steps per millisecond=61 ) properties (out of 9) seen :0
Running SMT prover for 9 properties.
[2023-03-14 23:36:57] [INFO ] Flow matrix only has 1380 transitions (discarded 32 similar events)
[2023-03-14 23:36:57] [INFO ] Invariant cache hit.
[2023-03-14 23:36:58] [INFO ] [Real]Absence check using 16 positive place invariants in 7 ms returned sat
[2023-03-14 23:36:58] [INFO ] [Real]Absence check using 16 positive and 38 generalized place invariants in 35 ms returned sat
[2023-03-14 23:36:58] [INFO ] After 334ms SMT Verify possible using all constraints in real domain returned unsat :3 sat :0 real:6
[2023-03-14 23:36:59] [INFO ] [Nat]Absence check using 16 positive place invariants in 11 ms returned sat
[2023-03-14 23:36:59] [INFO ] [Nat]Absence check using 16 positive and 38 generalized place invariants in 41 ms returned sat
[2023-03-14 23:36:59] [INFO ] After 368ms SMT Verify possible using all constraints in natural domain returned unsat :9 sat :0
Fused 9 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 9 atomic propositions for a total of 16 simplifications.
[2023-03-14 23:36:59] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-14 23:36:59] [INFO ] Flatten gal took : 83 ms
FORMULA PolyORBLF-COL-S04J04T08-CTLFireability-09 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-14 23:36:59] [INFO ] Flatten gal took : 87 ms
[2023-03-14 23:37:00] [INFO ] Input system was already deterministic with 1412 transitions.
Support contains 527 out of 712 places (down from 583) after GAL structural reductions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 712/712 places, 1412/1412 transitions.
Ensure Unique test removed 4 places
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 708 transition count 1412
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 12 place count 700 transition count 1404
Iterating global reduction 1 with 8 rules applied. Total rules applied 20 place count 700 transition count 1404
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 28 place count 692 transition count 1396
Iterating global reduction 1 with 8 rules applied. Total rules applied 36 place count 692 transition count 1396
Applied a total of 36 rules in 68 ms. Remains 692 /712 variables (removed 20) and now considering 1396/1412 (removed 16) transitions.
[2023-03-14 23:37:00] [INFO ] Flow matrix only has 1364 transitions (discarded 32 similar events)
// Phase 1: matrix 1364 rows 692 cols
[2023-03-14 23:37:00] [INFO ] Computed 50 place invariants in 26 ms
[2023-03-14 23:37:00] [INFO ] Dead Transitions using invariants and state equation in 600 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 670 ms. Remains : 692/712 places, 1396/1412 transitions.
[2023-03-14 23:37:00] [INFO ] Flatten gal took : 53 ms
[2023-03-14 23:37:00] [INFO ] Flatten gal took : 52 ms
[2023-03-14 23:37:01] [INFO ] Input system was already deterministic with 1396 transitions.
Starting structural reductions in LTL mode, iteration 0 : 712/712 places, 1412/1412 transitions.
Ensure Unique test removed 4 places
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 708 transition count 1412
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 12 place count 700 transition count 1404
Iterating global reduction 1 with 8 rules applied. Total rules applied 20 place count 700 transition count 1404
Applied a total of 20 rules in 28 ms. Remains 700 /712 variables (removed 12) and now considering 1404/1412 (removed 8) transitions.
[2023-03-14 23:37:01] [INFO ] Flow matrix only has 1372 transitions (discarded 32 similar events)
// Phase 1: matrix 1372 rows 700 cols
[2023-03-14 23:37:01] [INFO ] Computed 50 place invariants in 31 ms
[2023-03-14 23:37:01] [INFO ] Dead Transitions using invariants and state equation in 795 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 825 ms. Remains : 700/712 places, 1404/1412 transitions.
[2023-03-14 23:37:01] [INFO ] Flatten gal took : 46 ms
[2023-03-14 23:37:02] [INFO ] Flatten gal took : 48 ms
[2023-03-14 23:37:02] [INFO ] Input system was already deterministic with 1404 transitions.
Starting structural reductions in LTL mode, iteration 0 : 712/712 places, 1412/1412 transitions.
Ensure Unique test removed 4 places
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 708 transition count 1412
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 12 place count 700 transition count 1404
Iterating global reduction 1 with 8 rules applied. Total rules applied 20 place count 700 transition count 1404
Applied a total of 20 rules in 37 ms. Remains 700 /712 variables (removed 12) and now considering 1404/1412 (removed 8) transitions.
[2023-03-14 23:37:02] [INFO ] Flow matrix only has 1372 transitions (discarded 32 similar events)
[2023-03-14 23:37:02] [INFO ] Invariant cache hit.
[2023-03-14 23:37:02] [INFO ] Dead Transitions using invariants and state equation in 566 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 607 ms. Remains : 700/712 places, 1404/1412 transitions.
[2023-03-14 23:37:02] [INFO ] Flatten gal took : 46 ms
[2023-03-14 23:37:02] [INFO ] Flatten gal took : 47 ms
[2023-03-14 23:37:02] [INFO ] Input system was already deterministic with 1404 transitions.
Starting structural reductions in LTL mode, iteration 0 : 712/712 places, 1412/1412 transitions.
Ensure Unique test removed 4 places
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 708 transition count 1412
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 12 place count 700 transition count 1404
Iterating global reduction 1 with 8 rules applied. Total rules applied 20 place count 700 transition count 1404
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 28 place count 692 transition count 1396
Iterating global reduction 1 with 8 rules applied. Total rules applied 36 place count 692 transition count 1396
Applied a total of 36 rules in 57 ms. Remains 692 /712 variables (removed 20) and now considering 1396/1412 (removed 16) transitions.
[2023-03-14 23:37:03] [INFO ] Flow matrix only has 1364 transitions (discarded 32 similar events)
// Phase 1: matrix 1364 rows 692 cols
[2023-03-14 23:37:03] [INFO ] Computed 50 place invariants in 28 ms
[2023-03-14 23:37:03] [INFO ] Dead Transitions using invariants and state equation in 613 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 675 ms. Remains : 692/712 places, 1396/1412 transitions.
[2023-03-14 23:37:03] [INFO ] Flatten gal took : 46 ms
[2023-03-14 23:37:03] [INFO ] Flatten gal took : 52 ms
[2023-03-14 23:37:03] [INFO ] Input system was already deterministic with 1396 transitions.
Starting structural reductions in LTL mode, iteration 0 : 712/712 places, 1412/1412 transitions.
Ensure Unique test removed 4 places
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 708 transition count 1412
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 12 place count 700 transition count 1404
Iterating global reduction 1 with 8 rules applied. Total rules applied 20 place count 700 transition count 1404
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 28 place count 692 transition count 1396
Iterating global reduction 1 with 8 rules applied. Total rules applied 36 place count 692 transition count 1396
Applied a total of 36 rules in 37 ms. Remains 692 /712 variables (removed 20) and now considering 1396/1412 (removed 16) transitions.
[2023-03-14 23:37:03] [INFO ] Flow matrix only has 1364 transitions (discarded 32 similar events)
[2023-03-14 23:37:03] [INFO ] Invariant cache hit.
[2023-03-14 23:37:04] [INFO ] Dead Transitions using invariants and state equation in 552 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 594 ms. Remains : 692/712 places, 1396/1412 transitions.
[2023-03-14 23:37:04] [INFO ] Flatten gal took : 42 ms
[2023-03-14 23:37:04] [INFO ] Flatten gal took : 45 ms
[2023-03-14 23:37:04] [INFO ] Input system was already deterministic with 1396 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 712/712 places, 1412/1412 transitions.
Ensure Unique test removed 4 places
Drop transitions removed 56 transitions
Trivial Post-agglo rules discarded 56 transitions
Performed 56 trivial Post agglomeration. Transition count delta: 56
Iterating post reduction 0 with 56 rules applied. Total rules applied 56 place count 708 transition count 1356
Reduce places removed 56 places and 0 transitions.
Performed 8 Post agglomeration using F-continuation condition.Transition count delta: 8
Iterating post reduction 1 with 64 rules applied. Total rules applied 120 place count 652 transition count 1348
Reduce places removed 8 places and 0 transitions.
Iterating post reduction 2 with 8 rules applied. Total rules applied 128 place count 644 transition count 1348
Performed 80 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 80 Pre rules applied. Total rules applied 128 place count 644 transition count 1268
Deduced a syphon composed of 80 places in 1 ms
Reduce places removed 80 places and 0 transitions.
Iterating global reduction 3 with 160 rules applied. Total rules applied 288 place count 564 transition count 1268
Performed 56 Post agglomeration using F-continuation condition.Transition count delta: 56
Deduced a syphon composed of 56 places in 1 ms
Reduce places removed 56 places and 0 transitions.
Iterating global reduction 3 with 112 rules applied. Total rules applied 400 place count 508 transition count 1212
Applied a total of 400 rules in 100 ms. Remains 508 /712 variables (removed 204) and now considering 1212/1412 (removed 200) transitions.
[2023-03-14 23:37:04] [INFO ] Flow matrix only has 1180 transitions (discarded 32 similar events)
// Phase 1: matrix 1180 rows 508 cols
[2023-03-14 23:37:04] [INFO ] Computed 50 place invariants in 20 ms
[2023-03-14 23:37:05] [INFO ] Dead Transitions using invariants and state equation in 469 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 573 ms. Remains : 508/712 places, 1212/1412 transitions.
[2023-03-14 23:37:05] [INFO ] Flatten gal took : 48 ms
[2023-03-14 23:37:05] [INFO ] Flatten gal took : 46 ms
[2023-03-14 23:37:05] [INFO ] Input system was already deterministic with 1212 transitions.
Starting structural reductions in LTL mode, iteration 0 : 712/712 places, 1412/1412 transitions.
Ensure Unique test removed 4 places
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 708 transition count 1412
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 12 place count 700 transition count 1404
Iterating global reduction 1 with 8 rules applied. Total rules applied 20 place count 700 transition count 1404
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 28 place count 692 transition count 1396
Iterating global reduction 1 with 8 rules applied. Total rules applied 36 place count 692 transition count 1396
Applied a total of 36 rules in 26 ms. Remains 692 /712 variables (removed 20) and now considering 1396/1412 (removed 16) transitions.
[2023-03-14 23:37:05] [INFO ] Flow matrix only has 1364 transitions (discarded 32 similar events)
// Phase 1: matrix 1364 rows 692 cols
[2023-03-14 23:37:05] [INFO ] Computed 50 place invariants in 22 ms
[2023-03-14 23:37:06] [INFO ] Dead Transitions using invariants and state equation in 544 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 574 ms. Remains : 692/712 places, 1396/1412 transitions.
[2023-03-14 23:37:06] [INFO ] Flatten gal took : 39 ms
[2023-03-14 23:37:06] [INFO ] Flatten gal took : 41 ms
[2023-03-14 23:37:06] [INFO ] Input system was already deterministic with 1396 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 712/712 places, 1412/1412 transitions.
Ensure Unique test removed 4 places
Drop transitions removed 72 transitions
Trivial Post-agglo rules discarded 72 transitions
Performed 72 trivial Post agglomeration. Transition count delta: 72
Iterating post reduction 0 with 72 rules applied. Total rules applied 72 place count 708 transition count 1340
Reduce places removed 72 places and 0 transitions.
Iterating post reduction 1 with 72 rules applied. Total rules applied 144 place count 636 transition count 1340
Performed 48 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 48 Pre rules applied. Total rules applied 144 place count 636 transition count 1292
Deduced a syphon composed of 48 places in 3 ms
Reduce places removed 48 places and 0 transitions.
Iterating global reduction 2 with 96 rules applied. Total rules applied 240 place count 588 transition count 1292
Performed 80 Post agglomeration using F-continuation condition.Transition count delta: 80
Deduced a syphon composed of 80 places in 2 ms
Reduce places removed 80 places and 0 transitions.
Iterating global reduction 2 with 160 rules applied. Total rules applied 400 place count 508 transition count 1212
Applied a total of 400 rules in 68 ms. Remains 508 /712 variables (removed 204) and now considering 1212/1412 (removed 200) transitions.
[2023-03-14 23:37:06] [INFO ] Flow matrix only has 1180 transitions (discarded 32 similar events)
// Phase 1: matrix 1180 rows 508 cols
[2023-03-14 23:37:06] [INFO ] Computed 50 place invariants in 17 ms
[2023-03-14 23:37:06] [INFO ] Dead Transitions using invariants and state equation in 478 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 551 ms. Remains : 508/712 places, 1212/1412 transitions.
[2023-03-14 23:37:06] [INFO ] Flatten gal took : 37 ms
[2023-03-14 23:37:06] [INFO ] Flatten gal took : 40 ms
[2023-03-14 23:37:06] [INFO ] Input system was already deterministic with 1212 transitions.
Starting structural reductions in LTL mode, iteration 0 : 712/712 places, 1412/1412 transitions.
Ensure Unique test removed 4 places
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 708 transition count 1412
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 12 place count 700 transition count 1404
Iterating global reduction 1 with 8 rules applied. Total rules applied 20 place count 700 transition count 1404
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 28 place count 692 transition count 1396
Iterating global reduction 1 with 8 rules applied. Total rules applied 36 place count 692 transition count 1396
Applied a total of 36 rules in 39 ms. Remains 692 /712 variables (removed 20) and now considering 1396/1412 (removed 16) transitions.
[2023-03-14 23:37:07] [INFO ] Flow matrix only has 1364 transitions (discarded 32 similar events)
// Phase 1: matrix 1364 rows 692 cols
[2023-03-14 23:37:07] [INFO ] Computed 50 place invariants in 26 ms
[2023-03-14 23:37:07] [INFO ] Dead Transitions using invariants and state equation in 533 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 576 ms. Remains : 692/712 places, 1396/1412 transitions.
[2023-03-14 23:37:07] [INFO ] Flatten gal took : 38 ms
[2023-03-14 23:37:07] [INFO ] Flatten gal took : 42 ms
[2023-03-14 23:37:07] [INFO ] Input system was already deterministic with 1396 transitions.
Starting structural reductions in LTL mode, iteration 0 : 712/712 places, 1412/1412 transitions.
Applied a total of 0 rules in 7 ms. Remains 712 /712 variables (removed 0) and now considering 1412/1412 (removed 0) transitions.
[2023-03-14 23:37:07] [INFO ] Flow matrix only has 1380 transitions (discarded 32 similar events)
// Phase 1: matrix 1380 rows 712 cols
[2023-03-14 23:37:07] [INFO ] Computed 54 place invariants in 27 ms
[2023-03-14 23:37:08] [INFO ] Dead Transitions using invariants and state equation in 551 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 559 ms. Remains : 712/712 places, 1412/1412 transitions.
[2023-03-14 23:37:08] [INFO ] Flatten gal took : 40 ms
[2023-03-14 23:37:08] [INFO ] Flatten gal took : 43 ms
[2023-03-14 23:37:08] [INFO ] Input system was already deterministic with 1412 transitions.
Starting structural reductions in LTL mode, iteration 0 : 712/712 places, 1412/1412 transitions.
Ensure Unique test removed 4 places
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 708 transition count 1412
Applied a total of 4 rules in 15 ms. Remains 708 /712 variables (removed 4) and now considering 1412/1412 (removed 0) transitions.
[2023-03-14 23:37:08] [INFO ] Flow matrix only has 1380 transitions (discarded 32 similar events)
// Phase 1: matrix 1380 rows 708 cols
[2023-03-14 23:37:08] [INFO ] Computed 50 place invariants in 23 ms
[2023-03-14 23:37:09] [INFO ] Dead Transitions using invariants and state equation in 586 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 602 ms. Remains : 708/712 places, 1412/1412 transitions.
[2023-03-14 23:37:09] [INFO ] Flatten gal took : 42 ms
[2023-03-14 23:37:09] [INFO ] Flatten gal took : 45 ms
[2023-03-14 23:37:09] [INFO ] Input system was already deterministic with 1412 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 712/712 places, 1412/1412 transitions.
Ensure Unique test removed 4 places
Drop transitions removed 72 transitions
Trivial Post-agglo rules discarded 72 transitions
Performed 72 trivial Post agglomeration. Transition count delta: 72
Iterating post reduction 0 with 72 rules applied. Total rules applied 72 place count 708 transition count 1340
Reduce places removed 72 places and 0 transitions.
Iterating post reduction 1 with 72 rules applied. Total rules applied 144 place count 636 transition count 1340
Performed 80 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 80 Pre rules applied. Total rules applied 144 place count 636 transition count 1260
Deduced a syphon composed of 80 places in 1 ms
Reduce places removed 80 places and 0 transitions.
Iterating global reduction 2 with 160 rules applied. Total rules applied 304 place count 556 transition count 1260
Performed 72 Post agglomeration using F-continuation condition.Transition count delta: 72
Deduced a syphon composed of 72 places in 0 ms
Reduce places removed 72 places and 0 transitions.
Iterating global reduction 2 with 144 rules applied. Total rules applied 448 place count 484 transition count 1188
Applied a total of 448 rules in 52 ms. Remains 484 /712 variables (removed 228) and now considering 1188/1412 (removed 224) transitions.
[2023-03-14 23:37:09] [INFO ] Flow matrix only has 1156 transitions (discarded 32 similar events)
// Phase 1: matrix 1156 rows 484 cols
[2023-03-14 23:37:09] [INFO ] Computed 50 place invariants in 20 ms
[2023-03-14 23:37:09] [INFO ] Dead Transitions using invariants and state equation in 501 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 555 ms. Remains : 484/712 places, 1188/1412 transitions.
[2023-03-14 23:37:09] [INFO ] Flatten gal took : 38 ms
[2023-03-14 23:37:09] [INFO ] Flatten gal took : 42 ms
[2023-03-14 23:37:10] [INFO ] Input system was already deterministic with 1188 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 712/712 places, 1412/1412 transitions.
Ensure Unique test removed 4 places
Drop transitions removed 48 transitions
Trivial Post-agglo rules discarded 48 transitions
Performed 48 trivial Post agglomeration. Transition count delta: 48
Iterating post reduction 0 with 48 rules applied. Total rules applied 48 place count 708 transition count 1364
Reduce places removed 48 places and 0 transitions.
Performed 16 Post agglomeration using F-continuation condition.Transition count delta: 16
Iterating post reduction 1 with 64 rules applied. Total rules applied 112 place count 660 transition count 1348
Reduce places removed 16 places and 0 transitions.
Iterating post reduction 2 with 16 rules applied. Total rules applied 128 place count 644 transition count 1348
Performed 88 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 88 Pre rules applied. Total rules applied 128 place count 644 transition count 1260
Deduced a syphon composed of 88 places in 1 ms
Reduce places removed 88 places and 0 transitions.
Iterating global reduction 3 with 176 rules applied. Total rules applied 304 place count 556 transition count 1260
Performed 24 Post agglomeration using F-continuation condition.Transition count delta: 24
Deduced a syphon composed of 24 places in 1 ms
Reduce places removed 24 places and 0 transitions.
Iterating global reduction 3 with 48 rules applied. Total rules applied 352 place count 532 transition count 1236
Applied a total of 352 rules in 51 ms. Remains 532 /712 variables (removed 180) and now considering 1236/1412 (removed 176) transitions.
[2023-03-14 23:37:10] [INFO ] Flow matrix only has 1204 transitions (discarded 32 similar events)
// Phase 1: matrix 1204 rows 532 cols
[2023-03-14 23:37:10] [INFO ] Computed 50 place invariants in 22 ms
[2023-03-14 23:37:10] [INFO ] Dead Transitions using invariants and state equation in 550 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 601 ms. Remains : 532/712 places, 1236/1412 transitions.
[2023-03-14 23:37:10] [INFO ] Flatten gal took : 37 ms
[2023-03-14 23:37:10] [INFO ] Flatten gal took : 40 ms
[2023-03-14 23:37:10] [INFO ] Input system was already deterministic with 1236 transitions.
Starting structural reductions in LTL mode, iteration 0 : 712/712 places, 1412/1412 transitions.
Ensure Unique test removed 4 places
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 708 transition count 1412
Applied a total of 4 rules in 8 ms. Remains 708 /712 variables (removed 4) and now considering 1412/1412 (removed 0) transitions.
[2023-03-14 23:37:10] [INFO ] Flow matrix only has 1380 transitions (discarded 32 similar events)
// Phase 1: matrix 1380 rows 708 cols
[2023-03-14 23:37:10] [INFO ] Computed 50 place invariants in 24 ms
[2023-03-14 23:37:11] [INFO ] Dead Transitions using invariants and state equation in 578 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 586 ms. Remains : 708/712 places, 1412/1412 transitions.
[2023-03-14 23:37:11] [INFO ] Flatten gal took : 42 ms
[2023-03-14 23:37:11] [INFO ] Flatten gal took : 45 ms
[2023-03-14 23:37:11] [INFO ] Input system was already deterministic with 1412 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 712/712 places, 1412/1412 transitions.
Ensure Unique test removed 4 places
Drop transitions removed 64 transitions
Trivial Post-agglo rules discarded 64 transitions
Performed 64 trivial Post agglomeration. Transition count delta: 64
Iterating post reduction 0 with 64 rules applied. Total rules applied 64 place count 708 transition count 1348
Reduce places removed 64 places and 0 transitions.
Iterating post reduction 1 with 64 rules applied. Total rules applied 128 place count 644 transition count 1348
Performed 80 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 80 Pre rules applied. Total rules applied 128 place count 644 transition count 1268
Deduced a syphon composed of 80 places in 0 ms
Reduce places removed 80 places and 0 transitions.
Iterating global reduction 2 with 160 rules applied. Total rules applied 288 place count 564 transition count 1268
Performed 72 Post agglomeration using F-continuation condition.Transition count delta: 72
Deduced a syphon composed of 72 places in 0 ms
Reduce places removed 72 places and 0 transitions.
Iterating global reduction 2 with 144 rules applied. Total rules applied 432 place count 492 transition count 1196
Applied a total of 432 rules in 43 ms. Remains 492 /712 variables (removed 220) and now considering 1196/1412 (removed 216) transitions.
[2023-03-14 23:37:11] [INFO ] Flow matrix only has 1164 transitions (discarded 32 similar events)
// Phase 1: matrix 1164 rows 492 cols
[2023-03-14 23:37:11] [INFO ] Computed 50 place invariants in 20 ms
[2023-03-14 23:37:12] [INFO ] Dead Transitions using invariants and state equation in 498 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 542 ms. Remains : 492/712 places, 1196/1412 transitions.
[2023-03-14 23:37:12] [INFO ] Flatten gal took : 35 ms
[2023-03-14 23:37:12] [INFO ] Flatten gal took : 39 ms
[2023-03-14 23:37:12] [INFO ] Input system was already deterministic with 1196 transitions.
[2023-03-14 23:37:12] [INFO ] Flatten gal took : 82 ms
[2023-03-14 23:37:12] [INFO ] Flatten gal took : 68 ms
[2023-03-14 23:37:12] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 19 ms.
[2023-03-14 23:37:12] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 712 places, 1412 transitions and 6376 arcs took 6 ms.
Total runtime 22594 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT PolyORBLF-COL-S04J04T08
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA PolyORBLF-COL-S04J04T08-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PolyORBLF-COL-S04J04T08-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PolyORBLF-COL-S04J04T08-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PolyORBLF-COL-S04J04T08-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PolyORBLF-COL-S04J04T08-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678837816329

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: LAUNCH task # 8 (type EXCL) for 7 PolyORBLF-COL-S04J04T08-CTLFireability-01
lola: time limit : 178 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 8 (type EXCL) for PolyORBLF-COL-S04J04T08-CTLFireability-01
lola: result : false
lola: markings : 938
lola: fired transitions : 947
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 57 (type EXCL) for 25 PolyORBLF-COL-S04J04T08-CTLFireability-07
lola: time limit : 187 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 57 (type EXCL) for PolyORBLF-COL-S04J04T08-CTLFireability-07
lola: result : true
lola: markings : 733
lola: fired transitions : 753
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 14 (type EXCL) for 13 PolyORBLF-COL-S04J04T08-CTLFireability-03
lola: time limit : 197 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 4/222 5/32 PolyORBLF-COL-S04J04T08-CTLFireability-03 435167 m, 87033 m/sec, 839933 t fired, .

Time elapsed: 42 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 9/222 11/32 PolyORBLF-COL-S04J04T08-CTLFireability-03 943398 m, 101646 m/sec, 1912555 t fired, .

Time elapsed: 47 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 14/222 16/32 PolyORBLF-COL-S04J04T08-CTLFireability-03 1420946 m, 95509 m/sec, 3023665 t fired, .

Time elapsed: 52 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 19/222 21/32 PolyORBLF-COL-S04J04T08-CTLFireability-03 1868357 m, 89482 m/sec, 4173502 t fired, .

Time elapsed: 57 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 24/222 26/32 PolyORBLF-COL-S04J04T08-CTLFireability-03 2292538 m, 84836 m/sec, 5319275 t fired, .

Time elapsed: 62 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 29/222 30/32 PolyORBLF-COL-S04J04T08-CTLFireability-03 2730384 m, 87569 m/sec, 6441855 t fired, .

Time elapsed: 67 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 14 (type EXCL) for PolyORBLF-COL-S04J04T08-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 72 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 52 (type EXCL) for 43 PolyORBLF-COL-S04J04T08-CTLFireability-14
lola: time limit : 235 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 2 1 0 3 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 5/235 4/32 PolyORBLF-COL-S04J04T08-CTLFireability-14 361184 m, 72236 m/sec, 904687 t fired, .

Time elapsed: 77 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 2 1 0 3 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 10/235 6/32 PolyORBLF-COL-S04J04T08-CTLFireability-14 708396 m, 69442 m/sec, 1852037 t fired, .

Time elapsed: 82 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 2 1 0 3 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 15/235 9/32 PolyORBLF-COL-S04J04T08-CTLFireability-14 1011832 m, 60687 m/sec, 2829609 t fired, .

Time elapsed: 87 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 2 1 0 3 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 20/235 11/32 PolyORBLF-COL-S04J04T08-CTLFireability-14 1316481 m, 60929 m/sec, 3800680 t fired, .

Time elapsed: 92 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 2 1 0 3 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 25/235 14/32 PolyORBLF-COL-S04J04T08-CTLFireability-14 1611899 m, 59083 m/sec, 4791118 t fired, .

Time elapsed: 97 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 2 1 0 3 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 30/235 16/32 PolyORBLF-COL-S04J04T08-CTLFireability-14 1907363 m, 59092 m/sec, 5773936 t fired, .

Time elapsed: 102 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 2 1 0 3 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 35/235 19/32 PolyORBLF-COL-S04J04T08-CTLFireability-14 2213630 m, 61253 m/sec, 6758282 t fired, .

Time elapsed: 107 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 2 1 0 3 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 40/235 21/32 PolyORBLF-COL-S04J04T08-CTLFireability-14 2509809 m, 59235 m/sec, 7740401 t fired, .

Time elapsed: 112 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 2 1 0 3 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 45/235 24/32 PolyORBLF-COL-S04J04T08-CTLFireability-14 2813616 m, 60761 m/sec, 8721317 t fired, .

Time elapsed: 117 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 2 1 0 3 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 50/235 26/32 PolyORBLF-COL-S04J04T08-CTLFireability-14 3108812 m, 59039 m/sec, 9696483 t fired, .

Time elapsed: 122 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 2 1 0 3 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 55/235 29/32 PolyORBLF-COL-S04J04T08-CTLFireability-14 3411980 m, 60633 m/sec, 10662519 t fired, .

Time elapsed: 127 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 2 1 0 3 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 60/235 31/32 PolyORBLF-COL-S04J04T08-CTLFireability-14 3748936 m, 67391 m/sec, 11576135 t fired, .

Time elapsed: 132 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 52 (type EXCL) for PolyORBLF-COL-S04J04T08-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 2 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 137 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 50 (type EXCL) for 43 PolyORBLF-COL-S04J04T08-CTLFireability-14
lola: time limit : 247 sec
lola: memory limit: 32 pages
lola: FINISHED task # 50 (type EXCL) for PolyORBLF-COL-S04J04T08-CTLFireability-14
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 35 (type EXCL) for 34 PolyORBLF-COL-S04J04T08-CTLFireability-11
lola: time limit : 288 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 5/288 4/32 PolyORBLF-COL-S04J04T08-CTLFireability-11 289015 m, 57803 m/sec, 1030959 t fired, .

Time elapsed: 142 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 10/288 7/32 PolyORBLF-COL-S04J04T08-CTLFireability-11 569972 m, 56191 m/sec, 2055936 t fired, .

Time elapsed: 147 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 15/288 10/32 PolyORBLF-COL-S04J04T08-CTLFireability-11 846605 m, 55326 m/sec, 3072425 t fired, .

Time elapsed: 152 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 20/288 13/32 PolyORBLF-COL-S04J04T08-CTLFireability-11 1126294 m, 55937 m/sec, 4092168 t fired, .

Time elapsed: 157 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 25/288 15/32 PolyORBLF-COL-S04J04T08-CTLFireability-11 1363551 m, 47451 m/sec, 5191508 t fired, .

Time elapsed: 162 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 30/288 18/32 PolyORBLF-COL-S04J04T08-CTLFireability-11 1599849 m, 47259 m/sec, 6284080 t fired, .

Time elapsed: 167 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 35/288 21/32 PolyORBLF-COL-S04J04T08-CTLFireability-11 1837179 m, 47466 m/sec, 7363898 t fired, .

Time elapsed: 172 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 40/288 23/32 PolyORBLF-COL-S04J04T08-CTLFireability-11 2071956 m, 46955 m/sec, 8449878 t fired, .

Time elapsed: 177 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 45/288 26/32 PolyORBLF-COL-S04J04T08-CTLFireability-11 2307493 m, 47107 m/sec, 9523418 t fired, .

Time elapsed: 182 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 50/288 28/32 PolyORBLF-COL-S04J04T08-CTLFireability-11 2527594 m, 44020 m/sec, 10602719 t fired, .

Time elapsed: 187 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 55/288 30/32 PolyORBLF-COL-S04J04T08-CTLFireability-11 2762117 m, 46904 m/sec, 11671610 t fired, .

Time elapsed: 192 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 35 (type EXCL) for PolyORBLF-COL-S04J04T08-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 197 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 29 (type EXCL) for 28 PolyORBLF-COL-S04J04T08-CTLFireability-08
lola: time limit : 309 sec
lola: memory limit: 32 pages
lola: FINISHED task # 29 (type EXCL) for PolyORBLF-COL-S04J04T08-CTLFireability-08
lola: result : true
lola: markings : 1001
lola: fired transitions : 2868
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 23 (type EXCL) for 22 PolyORBLF-COL-S04J04T08-CTLFireability-06
lola: time limit : 340 sec
lola: memory limit: 32 pages
lola: FINISHED task # 23 (type EXCL) for PolyORBLF-COL-S04J04T08-CTLFireability-06
lola: result : false
lola: markings : 10763
lola: fired transitions : 23068
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 17 (type EXCL) for 16 PolyORBLF-COL-S04J04T08-CTLFireability-04
lola: time limit : 378 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 5/378 5/32 PolyORBLF-COL-S04J04T08-CTLFireability-04 409396 m, 81879 m/sec, 863529 t fired, .

Time elapsed: 202 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 10/378 8/32 PolyORBLF-COL-S04J04T08-CTLFireability-04 820460 m, 82212 m/sec, 1739242 t fired, .

Time elapsed: 207 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 15/378 12/32 PolyORBLF-COL-S04J04T08-CTLFireability-04 1225360 m, 80980 m/sec, 2608879 t fired, .

Time elapsed: 212 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 20/378 16/32 PolyORBLF-COL-S04J04T08-CTLFireability-04 1627586 m, 80445 m/sec, 3475190 t fired, .

Time elapsed: 217 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 25/378 19/32 PolyORBLF-COL-S04J04T08-CTLFireability-04 2027482 m, 79979 m/sec, 4339293 t fired, .

Time elapsed: 222 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 30/378 23/32 PolyORBLF-COL-S04J04T08-CTLFireability-04 2424328 m, 79369 m/sec, 5200421 t fired, .

Time elapsed: 227 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 35/378 27/32 PolyORBLF-COL-S04J04T08-CTLFireability-04 2821820 m, 79498 m/sec, 6061377 t fired, .

Time elapsed: 232 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 40/378 30/32 PolyORBLF-COL-S04J04T08-CTLFireability-04 3212104 m, 78056 m/sec, 6915586 t fired, .

Time elapsed: 237 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 17 (type EXCL) for PolyORBLF-COL-S04J04T08-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 242 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 11 (type EXCL) for 10 PolyORBLF-COL-S04J04T08-CTLFireability-02
lola: time limit : 419 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 5/419 4/32 PolyORBLF-COL-S04J04T08-CTLFireability-02 395567 m, 79113 m/sec, 1062321 t fired, .

Time elapsed: 247 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 10/419 8/32 PolyORBLF-COL-S04J04T08-CTLFireability-02 772555 m, 75397 m/sec, 2104461 t fired, .

Time elapsed: 252 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 15/419 11/32 PolyORBLF-COL-S04J04T08-CTLFireability-02 1139505 m, 73390 m/sec, 3131891 t fired, .

Time elapsed: 257 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 20/419 15/32 PolyORBLF-COL-S04J04T08-CTLFireability-02 1498374 m, 71773 m/sec, 4140385 t fired, .

Time elapsed: 262 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 25/419 18/32 PolyORBLF-COL-S04J04T08-CTLFireability-02 1854161 m, 71157 m/sec, 5146159 t fired, .

Time elapsed: 267 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 30/419 21/32 PolyORBLF-COL-S04J04T08-CTLFireability-02 2204327 m, 70033 m/sec, 6145838 t fired, .

Time elapsed: 272 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 35/419 24/32 PolyORBLF-COL-S04J04T08-CTLFireability-02 2552324 m, 69599 m/sec, 7149022 t fired, .

Time elapsed: 277 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 40/419 27/32 PolyORBLF-COL-S04J04T08-CTLFireability-02 2898069 m, 69149 m/sec, 8145911 t fired, .

Time elapsed: 282 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 45/419 30/32 PolyORBLF-COL-S04J04T08-CTLFireability-02 3243641 m, 69114 m/sec, 9141640 t fired, .

Time elapsed: 287 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 11 (type EXCL) for PolyORBLF-COL-S04J04T08-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 292 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 5 (type EXCL) for 0 PolyORBLF-COL-S04J04T08-CTLFireability-00
lola: time limit : 472 sec
lola: memory limit: 32 pages
lola: FINISHED task # 5 (type EXCL) for PolyORBLF-COL-S04J04T08-CTLFireability-00
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 3 (type EXCL) for 0 PolyORBLF-COL-S04J04T08-CTLFireability-00
lola: time limit : 551 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 1 0 3 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 CTL EXCL 5/551 4/32 PolyORBLF-COL-S04J04T08-CTLFireability-00 336626 m, 67325 m/sec, 1080230 t fired, .

Time elapsed: 297 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 1 0 3 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 CTL EXCL 10/551 8/32 PolyORBLF-COL-S04J04T08-CTLFireability-00 688695 m, 70413 m/sec, 2154800 t fired, .

Time elapsed: 302 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 1 0 3 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 CTL EXCL 15/551 12/32 PolyORBLF-COL-S04J04T08-CTLFireability-00 1041976 m, 70656 m/sec, 3253572 t fired, .

Time elapsed: 307 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 1 0 3 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 CTL EXCL 20/551 16/32 PolyORBLF-COL-S04J04T08-CTLFireability-00 1382495 m, 68103 m/sec, 4336665 t fired, .

Time elapsed: 312 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 1 0 3 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 CTL EXCL 25/551 19/32 PolyORBLF-COL-S04J04T08-CTLFireability-00 1699551 m, 63411 m/sec, 5420189 t fired, .

Time elapsed: 317 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 1 0 3 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 CTL EXCL 30/551 22/32 PolyORBLF-COL-S04J04T08-CTLFireability-00 2023564 m, 64802 m/sec, 6510174 t fired, .

Time elapsed: 322 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 1 0 3 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 CTL EXCL 35/551 25/32 PolyORBLF-COL-S04J04T08-CTLFireability-00 2318157 m, 58918 m/sec, 7607654 t fired, .

Time elapsed: 327 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 1 0 3 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 CTL EXCL 40/551 29/32 PolyORBLF-COL-S04J04T08-CTLFireability-00 2644351 m, 65238 m/sec, 8674723 t fired, .

Time elapsed: 332 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 3 (type EXCL) for PolyORBLF-COL-S04J04T08-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 337 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 20 (type EXCL) for 19 PolyORBLF-COL-S04J04T08-CTLFireability-05
lola: time limit : 652 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 EG EXCL 5/652 2/32 PolyORBLF-COL-S04J04T08-CTLFireability-05 174913 m, 34982 m/sec, 691150 t fired, .

Time elapsed: 342 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 EG EXCL 10/652 3/32 PolyORBLF-COL-S04J04T08-CTLFireability-05 352890 m, 35595 m/sec, 1374075 t fired, .

Time elapsed: 347 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 EG EXCL 15/652 4/32 PolyORBLF-COL-S04J04T08-CTLFireability-05 535556 m, 36533 m/sec, 2056571 t fired, .

Time elapsed: 352 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 EG EXCL 20/652 5/32 PolyORBLF-COL-S04J04T08-CTLFireability-05 699326 m, 32754 m/sec, 2617070 t fired, .

Time elapsed: 357 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 EG EXCL 25/652 7/32 PolyORBLF-COL-S04J04T08-CTLFireability-05 863589 m, 32852 m/sec, 3176735 t fired, .

Time elapsed: 362 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 EG EXCL 30/652 8/32 PolyORBLF-COL-S04J04T08-CTLFireability-05 1041837 m, 35649 m/sec, 3871074 t fired, .

Time elapsed: 367 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 EG EXCL 35/652 9/32 PolyORBLF-COL-S04J04T08-CTLFireability-05 1216066 m, 34845 m/sec, 4488649 t fired, .

Time elapsed: 372 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 EG EXCL 40/652 10/32 PolyORBLF-COL-S04J04T08-CTLFireability-05 1382128 m, 33212 m/sec, 5045878 t fired, .

Time elapsed: 377 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 EG EXCL 45/652 11/32 PolyORBLF-COL-S04J04T08-CTLFireability-05 1562343 m, 36043 m/sec, 5711895 t fired, .

Time elapsed: 382 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 EG EXCL 50/652 12/32 PolyORBLF-COL-S04J04T08-CTLFireability-05 1722920 m, 32115 m/sec, 6256677 t fired, .

Time elapsed: 387 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 EG EXCL 55/652 14/32 PolyORBLF-COL-S04J04T08-CTLFireability-05 1907404 m, 36896 m/sec, 6953338 t fired, .

Time elapsed: 392 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 EG EXCL 60/652 15/32 PolyORBLF-COL-S04J04T08-CTLFireability-05 2088129 m, 36145 m/sec, 7588329 t fired, .

Time elapsed: 397 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 EG EXCL 65/652 16/32 PolyORBLF-COL-S04J04T08-CTLFireability-05 2270338 m, 36441 m/sec, 8216352 t fired, .

Time elapsed: 402 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 EG EXCL 70/652 17/32 PolyORBLF-COL-S04J04T08-CTLFireability-05 2443856 m, 34703 m/sec, 8770907 t fired, .

Time elapsed: 407 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 EG EXCL 75/652 19/32 PolyORBLF-COL-S04J04T08-CTLFireability-05 2601470 m, 31522 m/sec, 9306169 t fired, .

Time elapsed: 412 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 EG EXCL 80/652 20/32 PolyORBLF-COL-S04J04T08-CTLFireability-05 2777486 m, 35203 m/sec, 9895713 t fired, .

Time elapsed: 417 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 EG EXCL 85/652 21/32 PolyORBLF-COL-S04J04T08-CTLFireability-05 2951784 m, 34859 m/sec, 10435258 t fired, .

Time elapsed: 422 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 EG EXCL 90/652 22/32 PolyORBLF-COL-S04J04T08-CTLFireability-05 3110564 m, 31756 m/sec, 10977130 t fired, .

Time elapsed: 427 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 EG EXCL 95/652 23/32 PolyORBLF-COL-S04J04T08-CTLFireability-05 3282586 m, 34404 m/sec, 11549785 t fired, .

Time elapsed: 432 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 EG EXCL 100/652 24/32 PolyORBLF-COL-S04J04T08-CTLFireability-05 3458242 m, 35131 m/sec, 12108738 t fired, .

Time elapsed: 437 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 EG EXCL 105/652 26/32 PolyORBLF-COL-S04J04T08-CTLFireability-05 3623943 m, 33140 m/sec, 12642919 t fired, .

Time elapsed: 442 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 EG EXCL 110/652 27/32 PolyORBLF-COL-S04J04T08-CTLFireability-05 3780578 m, 31327 m/sec, 13161878 t fired, .

Time elapsed: 447 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 EG EXCL 115/652 28/32 PolyORBLF-COL-S04J04T08-CTLFireability-05 3950688 m, 34022 m/sec, 13685389 t fired, .

Time elapsed: 452 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 EG EXCL 120/652 29/32 PolyORBLF-COL-S04J04T08-CTLFireability-05 4114176 m, 32697 m/sec, 14201913 t fired, .

Time elapsed: 457 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 EG EXCL 125/652 30/32 PolyORBLF-COL-S04J04T08-CTLFireability-05 4271170 m, 31398 m/sec, 14719957 t fired, .

Time elapsed: 462 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 EG EXCL 130/652 31/32 PolyORBLF-COL-S04J04T08-CTLFireability-05 4438760 m, 33518 m/sec, 15221102 t fired, .

Time elapsed: 467 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 EG EXCL 135/652 32/32 PolyORBLF-COL-S04J04T08-CTLFireability-05 4612681 m, 34784 m/sec, 15790832 t fired, .

Time elapsed: 472 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 20 (type EXCL) for PolyORBLF-COL-S04J04T08-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 477 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 58 (type EXCL) for 37 PolyORBLF-COL-S04J04T08-CTLFireability-12
lola: time limit : 780 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 5/780 2/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 133728 m, 26745 m/sec, 218697 t fired, .

Time elapsed: 482 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 10/780 3/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 264404 m, 26135 m/sec, 448698 t fired, .

Time elapsed: 487 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 15/780 4/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 366308 m, 20380 m/sec, 674740 t fired, .

Time elapsed: 492 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 20/780 5/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 471565 m, 21051 m/sec, 924435 t fired, .

Time elapsed: 497 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 25/780 6/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 576130 m, 20913 m/sec, 1152246 t fired, .

Time elapsed: 502 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 30/780 7/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 680881 m, 20950 m/sec, 1388354 t fired, .

Time elapsed: 507 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 35/780 7/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 790088 m, 21841 m/sec, 1658052 t fired, .

Time elapsed: 512 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 40/780 8/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 893365 m, 20655 m/sec, 1886288 t fired, .

Time elapsed: 517 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 45/780 9/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 1000588 m, 21444 m/sec, 2133448 t fired, .

Time elapsed: 522 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 50/780 10/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 1108188 m, 21520 m/sec, 2389807 t fired, .

Time elapsed: 527 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 55/780 11/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 1213725 m, 21107 m/sec, 2627550 t fired, .

Time elapsed: 532 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 60/780 12/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 1319683 m, 21191 m/sec, 2878750 t fired, .

Time elapsed: 537 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 65/780 13/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 1428344 m, 21732 m/sec, 3173772 t fired, .

Time elapsed: 542 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 70/780 14/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 1538040 m, 21939 m/sec, 3470315 t fired, .

Time elapsed: 547 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 75/780 15/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 1643248 m, 21041 m/sec, 3723102 t fired, .

Time elapsed: 552 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 80/780 16/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 1745013 m, 20353 m/sec, 3961454 t fired, .

Time elapsed: 557 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 85/780 16/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 1848056 m, 20608 m/sec, 4193430 t fired, .

Time elapsed: 562 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 90/780 17/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 1949152 m, 20219 m/sec, 4435044 t fired, .

Time elapsed: 567 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 95/780 18/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 2054140 m, 20997 m/sec, 4672591 t fired, .

Time elapsed: 572 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 100/780 19/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 2156100 m, 20392 m/sec, 4901845 t fired, .

Time elapsed: 577 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 105/780 20/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 2258426 m, 20465 m/sec, 5145137 t fired, .

Time elapsed: 582 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 110/780 21/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 2361788 m, 20672 m/sec, 5427056 t fired, .

Time elapsed: 587 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 115/780 22/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 2464713 m, 20585 m/sec, 5658320 t fired, .

Time elapsed: 592 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 120/780 22/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 2564317 m, 19920 m/sec, 5900310 t fired, .

Time elapsed: 597 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 125/780 23/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 2667883 m, 20713 m/sec, 6137729 t fired, .

Time elapsed: 602 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 130/780 24/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 2772012 m, 20825 m/sec, 6391429 t fired, .

Time elapsed: 607 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 135/780 25/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 2875450 m, 20687 m/sec, 6628534 t fired, .

Time elapsed: 612 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 140/780 26/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 2978864 m, 20682 m/sec, 6872640 t fired, .

Time elapsed: 617 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 145/780 27/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 3084292 m, 21085 m/sec, 7106825 t fired, .

Time elapsed: 622 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 150/780 28/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 3187927 m, 20727 m/sec, 7355284 t fired, .

Time elapsed: 627 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 155/780 28/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 3292931 m, 21000 m/sec, 7644157 t fired, .

Time elapsed: 632 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 160/780 29/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 3398368 m, 21087 m/sec, 7914872 t fired, .

Time elapsed: 637 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 165/780 30/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 3500737 m, 20473 m/sec, 8148816 t fired, .

Time elapsed: 642 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 170/780 31/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 3602265 m, 20305 m/sec, 8393973 t fired, .

Time elapsed: 647 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EG EXCL 175/780 32/32 PolyORBLF-COL-S04J04T08-CTLFireability-12 3705884 m, 20723 m/sec, 8632986 t fired, .

Time elapsed: 652 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 58 (type EXCL) for PolyORBLF-COL-S04J04T08-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 657 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 41 (type EXCL) for 40 PolyORBLF-COL-S04J04T08-CTLFireability-13
lola: time limit : 981 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 5/981 2/32 PolyORBLF-COL-S04J04T08-CTLFireability-13 191448 m, 38289 m/sec, 1159572 t fired, .

Time elapsed: 662 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 10/981 4/32 PolyORBLF-COL-S04J04T08-CTLFireability-13 418693 m, 45449 m/sec, 2309198 t fired, .

Time elapsed: 667 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 15/981 7/32 PolyORBLF-COL-S04J04T08-CTLFireability-13 659050 m, 48071 m/sec, 3449733 t fired, .

Time elapsed: 672 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 20/981 9/32 PolyORBLF-COL-S04J04T08-CTLFireability-13 897127 m, 47615 m/sec, 4583045 t fired, .

Time elapsed: 677 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 25/981 11/32 PolyORBLF-COL-S04J04T08-CTLFireability-13 1136840 m, 47942 m/sec, 5705265 t fired, .

Time elapsed: 682 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 30/981 14/32 PolyORBLF-COL-S04J04T08-CTLFireability-13 1372546 m, 47141 m/sec, 6822610 t fired, .

Time elapsed: 687 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 35/981 16/32 PolyORBLF-COL-S04J04T08-CTLFireability-13 1614895 m, 48469 m/sec, 7925308 t fired, .

Time elapsed: 692 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 40/981 18/32 PolyORBLF-COL-S04J04T08-CTLFireability-13 1853456 m, 47712 m/sec, 9029140 t fired, .

Time elapsed: 697 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 45/981 20/32 PolyORBLF-COL-S04J04T08-CTLFireability-13 2088680 m, 47044 m/sec, 10123952 t fired, .

Time elapsed: 702 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 50/981 22/32 PolyORBLF-COL-S04J04T08-CTLFireability-13 2328473 m, 47958 m/sec, 11224493 t fired, .

Time elapsed: 707 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 55/981 24/32 PolyORBLF-COL-S04J04T08-CTLFireability-13 2564355 m, 47176 m/sec, 12325598 t fired, .

Time elapsed: 712 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 60/981 26/32 PolyORBLF-COL-S04J04T08-CTLFireability-13 2801492 m, 47427 m/sec, 13420561 t fired, .

Time elapsed: 717 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 65/981 29/32 PolyORBLF-COL-S04J04T08-CTLFireability-13 3035951 m, 46891 m/sec, 14514867 t fired, .

Time elapsed: 722 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 70/981 31/32 PolyORBLF-COL-S04J04T08-CTLFireability-13 3257755 m, 44360 m/sec, 15625204 t fired, .

Time elapsed: 727 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 41 (type EXCL) for PolyORBLF-COL-S04J04T08-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 732 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 55 (type EXCL) for 54 PolyORBLF-COL-S04J04T08-CTLFireability-15
lola: time limit : 1434 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 5/1434 4/32 PolyORBLF-COL-S04J04T08-CTLFireability-15 446222 m, 89244 m/sec, 1383140 t fired, .

Time elapsed: 737 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 10/1434 8/32 PolyORBLF-COL-S04J04T08-CTLFireability-15 874597 m, 85675 m/sec, 2735081 t fired, .

Time elapsed: 742 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 15/1434 12/32 PolyORBLF-COL-S04J04T08-CTLFireability-15 1292346 m, 83549 m/sec, 4074884 t fired, .

Time elapsed: 747 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 20/1434 15/32 PolyORBLF-COL-S04J04T08-CTLFireability-15 1703124 m, 82155 m/sec, 5403899 t fired, .

Time elapsed: 752 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 25/1434 18/32 PolyORBLF-COL-S04J04T08-CTLFireability-15 2112546 m, 81884 m/sec, 6734782 t fired, .

Time elapsed: 757 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 30/1434 22/32 PolyORBLF-COL-S04J04T08-CTLFireability-15 2514376 m, 80366 m/sec, 8052294 t fired, .

Time elapsed: 762 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 35/1434 25/32 PolyORBLF-COL-S04J04T08-CTLFireability-15 2912853 m, 79695 m/sec, 9360808 t fired, .

Time elapsed: 767 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 40/1434 28/32 PolyORBLF-COL-S04J04T08-CTLFireability-15 3310067 m, 79442 m/sec, 10671354 t fired, .

Time elapsed: 772 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 45/1434 31/32 PolyORBLF-COL-S04J04T08-CTLFireability-15 3702573 m, 78501 m/sec, 11966933 t fired, .

Time elapsed: 777 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 55 (type EXCL) for PolyORBLF-COL-S04J04T08-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ 0 0 0 0 3 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-12: F 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ 0 0 0 0 4 0 1 1
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 782 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 32 (type EXCL) for 31 PolyORBLF-COL-S04J04T08-CTLFireability-10
lola: time limit : 2818 sec
lola: memory limit: 32 pages
lola: FINISHED task # 32 (type EXCL) for PolyORBLF-COL-S04J04T08-CTLFireability-10
lola: result : false
lola: markings : 1688
lola: fired transitions : 1959
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 15

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-COL-S04J04T08-CTLFireability-00: DISJ unknown DISJ
PolyORBLF-COL-S04J04T08-CTLFireability-01: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-02: CTL unknown AGGR
PolyORBLF-COL-S04J04T08-CTLFireability-03: CTL unknown AGGR
PolyORBLF-COL-S04J04T08-CTLFireability-04: CTL unknown AGGR
PolyORBLF-COL-S04J04T08-CTLFireability-05: EG unknown AGGR
PolyORBLF-COL-S04J04T08-CTLFireability-06: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-07: F false state space / EG
PolyORBLF-COL-S04J04T08-CTLFireability-08: CTL true CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-10: CTL false CTL model checker
PolyORBLF-COL-S04J04T08-CTLFireability-11: CTL unknown AGGR
PolyORBLF-COL-S04J04T08-CTLFireability-12: F unknown AGGR
PolyORBLF-COL-S04J04T08-CTLFireability-13: CTL unknown AGGR
PolyORBLF-COL-S04J04T08-CTLFireability-14: DISJ unknown DISJ
PolyORBLF-COL-S04J04T08-CTLFireability-15: CTL unknown AGGR


Time elapsed: 782 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PolyORBLF-COL-S04J04T08"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is PolyORBLF-COL-S04J04T08, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r295-tall-167873947800402"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/PolyORBLF-COL-S04J04T08.tgz
mv PolyORBLF-COL-S04J04T08 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;