fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r295-tall-167873947700338
Last Updated
May 14, 2023

About the Execution of LoLa+red for Planning-PT-none

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16215.968 434261.00 374380.00 12716.70 ????????????T??? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r295-tall-167873947700338.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is Planning-PT-none, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r295-tall-167873947700338
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 508K
-rw-r--r-- 1 mcc users 7.2K Feb 26 15:18 CTLCardinality.txt
-rw-r--r-- 1 mcc users 83K Feb 26 15:18 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.9K Feb 26 15:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 72K Feb 26 15:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 16:34 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:34 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 16:34 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 16:34 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.8K Feb 26 15:20 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 75K Feb 26 15:20 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.8K Feb 26 15:19 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 91K Feb 26 15:19 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:34 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:34 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 56K Mar 5 18:23 model.pnml
-rw-r--r-- 1 mcc users 1 Mar 5 18:23 unfinite

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Planning-PT-none-CTLFireability-00
FORMULA_NAME Planning-PT-none-CTLFireability-01
FORMULA_NAME Planning-PT-none-CTLFireability-02
FORMULA_NAME Planning-PT-none-CTLFireability-03
FORMULA_NAME Planning-PT-none-CTLFireability-04
FORMULA_NAME Planning-PT-none-CTLFireability-05
FORMULA_NAME Planning-PT-none-CTLFireability-06
FORMULA_NAME Planning-PT-none-CTLFireability-07
FORMULA_NAME Planning-PT-none-CTLFireability-08
FORMULA_NAME Planning-PT-none-CTLFireability-09
FORMULA_NAME Planning-PT-none-CTLFireability-10
FORMULA_NAME Planning-PT-none-CTLFireability-11
FORMULA_NAME Planning-PT-none-CTLFireability-12
FORMULA_NAME Planning-PT-none-CTLFireability-13
FORMULA_NAME Planning-PT-none-CTLFireability-14
FORMULA_NAME Planning-PT-none-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678827540923

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Planning-PT-none
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-14 20:59:02] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-14 20:59:02] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-14 20:59:02] [INFO ] Load time of PNML (sax parser for PT used): 39 ms
[2023-03-14 20:59:02] [INFO ] Transformed 126 places.
[2023-03-14 20:59:02] [INFO ] Transformed 128 transitions.
[2023-03-14 20:59:02] [INFO ] Parsed PT model containing 126 places and 128 transitions and 652 arcs in 100 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 10 ms.
Reduce places removed 2 places and 0 transitions.
Support contains 84 out of 124 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 124/124 places, 128/128 transitions.
Reduce places removed 26 places and 0 transitions.
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 0 with 31 rules applied. Total rules applied 31 place count 98 transition count 123
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 35 place count 94 transition count 119
Iterating global reduction 1 with 4 rules applied. Total rules applied 39 place count 94 transition count 119
Applied a total of 39 rules in 16 ms. Remains 94 /124 variables (removed 30) and now considering 119/128 (removed 9) transitions.
[2023-03-14 20:59:02] [INFO ] Flow matrix only has 94 transitions (discarded 25 similar events)
// Phase 1: matrix 94 rows 94 cols
[2023-03-14 20:59:02] [INFO ] Computed 37 place invariants in 10 ms
[2023-03-14 20:59:02] [INFO ] Implicit Places using invariants in 187 ms returned []
[2023-03-14 20:59:02] [INFO ] Flow matrix only has 94 transitions (discarded 25 similar events)
[2023-03-14 20:59:02] [INFO ] Invariant cache hit.
[2023-03-14 20:59:02] [INFO ] State equation strengthened by 23 read => feed constraints.
[2023-03-14 20:59:02] [INFO ] Implicit Places using invariants and state equation in 118 ms returned []
Implicit Place search using SMT with State Equation took 328 ms to find 0 implicit places.
[2023-03-14 20:59:02] [INFO ] Flow matrix only has 94 transitions (discarded 25 similar events)
[2023-03-14 20:59:02] [INFO ] Invariant cache hit.
[2023-03-14 20:59:02] [INFO ] Dead Transitions using invariants and state equation in 125 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 94/124 places, 119/128 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 471 ms. Remains : 94/124 places, 119/128 transitions.
Support contains 84 out of 94 places after structural reductions.
[2023-03-14 20:59:03] [INFO ] Flatten gal took : 32 ms
[2023-03-14 20:59:03] [INFO ] Flatten gal took : 14 ms
[2023-03-14 20:59:03] [INFO ] Input system was already deterministic with 119 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 290 ms. (steps per millisecond=34 ) properties (out of 96) seen :94
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=555 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=714 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-14 20:59:03] [INFO ] Flow matrix only has 94 transitions (discarded 25 similar events)
[2023-03-14 20:59:03] [INFO ] Invariant cache hit.
[2023-03-14 20:59:03] [INFO ] [Real]Absence check using 36 positive place invariants in 6 ms returned sat
[2023-03-14 20:59:03] [INFO ] [Real]Absence check using 36 positive and 1 generalized place invariants in 0 ms returned sat
[2023-03-14 20:59:03] [INFO ] After 69ms SMT Verify possible using all constraints in real domain returned unsat :2 sat :0
Fused 2 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 2 atomic propositions for a total of 16 simplifications.
[2023-03-14 20:59:03] [INFO ] Flatten gal took : 9 ms
[2023-03-14 20:59:03] [INFO ] Flatten gal took : 9 ms
[2023-03-14 20:59:03] [INFO ] Input system was already deterministic with 119 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Graph (complete) has 462 edges and 94 vertex of which 82 are kept as prefixes of interest. Removing 12 places using SCC suffix rule.3 ms
Starting structural reductions in SI_CTL mode, iteration 0 : 94/94 places, 119/119 transitions.
Graph (trivial) has 31 edges and 94 vertex of which 26 / 94 are part of one of the 13 SCC in 2 ms
Free SCC test removed 13 places
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Graph (complete) has 442 edges and 81 vertex of which 69 are kept as prefixes of interest. Removing 12 places using SCC suffix rule.1 ms
Discarding 12 places :
Also discarding 12 output transitions
Drop transitions removed 12 transitions
Reduce places removed 13 places and 0 transitions.
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Iterating post reduction 0 with 12 rules applied. Total rules applied 14 place count 56 transition count 82
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 18 place count 52 transition count 60
Iterating global reduction 1 with 4 rules applied. Total rules applied 22 place count 52 transition count 60
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 26 place count 52 transition count 56
Performed 5 Post agglomeration using F-continuation condition.Transition count delta: 5
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 2 with 15 rules applied. Total rules applied 41 place count 42 transition count 51
Applied a total of 41 rules in 17 ms. Remains 42 /94 variables (removed 52) and now considering 51/119 (removed 68) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 17 ms. Remains : 42/94 places, 51/119 transitions.
[2023-03-14 20:59:03] [INFO ] Flatten gal took : 3 ms
[2023-03-14 20:59:03] [INFO ] Flatten gal took : 3 ms
[2023-03-14 20:59:03] [INFO ] Input system was already deterministic with 51 transitions.
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 119/119 transitions.
Discarding 7 places :
Symmetric choice reduction at 0 with 7 rule applications. Total rules 7 place count 87 transition count 111
Iterating global reduction 0 with 7 rules applied. Total rules applied 14 place count 87 transition count 111
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 15 place count 87 transition count 110
Applied a total of 15 rules in 3 ms. Remains 87 /94 variables (removed 7) and now considering 110/119 (removed 9) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 87/94 places, 110/119 transitions.
[2023-03-14 20:59:03] [INFO ] Flatten gal took : 6 ms
[2023-03-14 20:59:03] [INFO ] Flatten gal took : 6 ms
[2023-03-14 20:59:03] [INFO ] Input system was already deterministic with 110 transitions.
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 119/119 transitions.
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 8 place count 86 transition count 110
Iterating global reduction 0 with 8 rules applied. Total rules applied 16 place count 86 transition count 110
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 17 place count 86 transition count 109
Applied a total of 17 rules in 2 ms. Remains 86 /94 variables (removed 8) and now considering 109/119 (removed 10) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 86/94 places, 109/119 transitions.
[2023-03-14 20:59:03] [INFO ] Flatten gal took : 5 ms
[2023-03-14 20:59:03] [INFO ] Flatten gal took : 6 ms
[2023-03-14 20:59:03] [INFO ] Input system was already deterministic with 109 transitions.
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 119/119 transitions.
Discarding 10 places :
Symmetric choice reduction at 0 with 10 rule applications. Total rules 10 place count 84 transition count 109
Iterating global reduction 0 with 10 rules applied. Total rules applied 20 place count 84 transition count 109
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 21 place count 83 transition count 107
Iterating global reduction 0 with 1 rules applied. Total rules applied 22 place count 83 transition count 107
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 23 place count 83 transition count 106
Applied a total of 23 rules in 4 ms. Remains 83 /94 variables (removed 11) and now considering 106/119 (removed 13) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 83/94 places, 106/119 transitions.
[2023-03-14 20:59:03] [INFO ] Flatten gal took : 5 ms
[2023-03-14 20:59:03] [INFO ] Flatten gal took : 6 ms
[2023-03-14 20:59:03] [INFO ] Input system was already deterministic with 106 transitions.
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 119/119 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 82 transition count 106
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 82 transition count 106
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 25 place count 82 transition count 105
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 28 place count 79 transition count 99
Iterating global reduction 1 with 3 rules applied. Total rules applied 31 place count 79 transition count 99
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 1 with 3 rules applied. Total rules applied 34 place count 79 transition count 96
Applied a total of 34 rules in 5 ms. Remains 79 /94 variables (removed 15) and now considering 96/119 (removed 23) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 79/94 places, 96/119 transitions.
[2023-03-14 20:59:03] [INFO ] Flatten gal took : 4 ms
[2023-03-14 20:59:03] [INFO ] Flatten gal took : 5 ms
[2023-03-14 20:59:03] [INFO ] Input system was already deterministic with 96 transitions.
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 119/119 transitions.
Discarding 10 places :
Symmetric choice reduction at 0 with 10 rule applications. Total rules 10 place count 84 transition count 109
Iterating global reduction 0 with 10 rules applied. Total rules applied 20 place count 84 transition count 109
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 23 place count 81 transition count 103
Iterating global reduction 0 with 3 rules applied. Total rules applied 26 place count 81 transition count 103
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 29 place count 81 transition count 100
Applied a total of 29 rules in 3 ms. Remains 81 /94 variables (removed 13) and now considering 100/119 (removed 19) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 81/94 places, 100/119 transitions.
[2023-03-14 20:59:03] [INFO ] Flatten gal took : 4 ms
[2023-03-14 20:59:03] [INFO ] Flatten gal took : 5 ms
[2023-03-14 20:59:03] [INFO ] Input system was already deterministic with 100 transitions.
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 119/119 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 82 transition count 106
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 82 transition count 106
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 25 place count 82 transition count 105
Discarding 2 places :
Symmetric choice reduction at 1 with 2 rule applications. Total rules 27 place count 80 transition count 101
Iterating global reduction 1 with 2 rules applied. Total rules applied 29 place count 80 transition count 101
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 31 place count 80 transition count 99
Applied a total of 31 rules in 5 ms. Remains 80 /94 variables (removed 14) and now considering 99/119 (removed 20) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 80/94 places, 99/119 transitions.
[2023-03-14 20:59:03] [INFO ] Flatten gal took : 4 ms
[2023-03-14 20:59:03] [INFO ] Flatten gal took : 5 ms
[2023-03-14 20:59:03] [INFO ] Input system was already deterministic with 99 transitions.
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 119/119 transitions.
Discarding 11 places :
Symmetric choice reduction at 0 with 11 rule applications. Total rules 11 place count 83 transition count 108
Iterating global reduction 0 with 11 rules applied. Total rules applied 22 place count 83 transition count 108
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 23 place count 82 transition count 106
Iterating global reduction 0 with 1 rules applied. Total rules applied 24 place count 82 transition count 106
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 25 place count 82 transition count 105
Applied a total of 25 rules in 4 ms. Remains 82 /94 variables (removed 12) and now considering 105/119 (removed 14) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 82/94 places, 105/119 transitions.
[2023-03-14 20:59:04] [INFO ] Flatten gal took : 4 ms
[2023-03-14 20:59:04] [INFO ] Flatten gal took : 5 ms
[2023-03-14 20:59:04] [INFO ] Input system was already deterministic with 105 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 94/94 places, 119/119 transitions.
Graph (trivial) has 16 edges and 94 vertex of which 12 / 94 are part of one of the 6 SCC in 1 ms
Free SCC test removed 6 places
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Graph (complete) has 454 edges and 88 vertex of which 76 are kept as prefixes of interest. Removing 12 places using SCC suffix rule.1 ms
Discarding 12 places :
Also discarding 12 output transitions
Drop transitions removed 12 transitions
Reduce places removed 6 places and 0 transitions.
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 0 with 5 rules applied. Total rules applied 7 place count 70 transition count 96
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 10 place count 67 transition count 90
Iterating global reduction 1 with 3 rules applied. Total rules applied 13 place count 67 transition count 90
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 1 with 3 rules applied. Total rules applied 16 place count 67 transition count 87
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 8 places and 0 transitions.
Iterating global reduction 2 with 12 rules applied. Total rules applied 28 place count 59 transition count 83
Applied a total of 28 rules in 10 ms. Remains 59 /94 variables (removed 35) and now considering 83/119 (removed 36) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 10 ms. Remains : 59/94 places, 83/119 transitions.
[2023-03-14 20:59:04] [INFO ] Flatten gal took : 4 ms
[2023-03-14 20:59:04] [INFO ] Flatten gal took : 4 ms
[2023-03-14 20:59:04] [INFO ] Input system was already deterministic with 83 transitions.
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 119/119 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 82 transition count 106
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 82 transition count 106
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 25 place count 82 transition count 105
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 28 place count 79 transition count 99
Iterating global reduction 1 with 3 rules applied. Total rules applied 31 place count 79 transition count 99
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 1 with 3 rules applied. Total rules applied 34 place count 79 transition count 96
Applied a total of 34 rules in 4 ms. Remains 79 /94 variables (removed 15) and now considering 96/119 (removed 23) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 79/94 places, 96/119 transitions.
[2023-03-14 20:59:04] [INFO ] Flatten gal took : 4 ms
[2023-03-14 20:59:04] [INFO ] Flatten gal took : 4 ms
[2023-03-14 20:59:04] [INFO ] Input system was already deterministic with 96 transitions.
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 119/119 transitions.
Discarding 11 places :
Symmetric choice reduction at 0 with 11 rule applications. Total rules 11 place count 83 transition count 107
Iterating global reduction 0 with 11 rules applied. Total rules applied 22 place count 83 transition count 107
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 23 place count 83 transition count 106
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 26 place count 80 transition count 100
Iterating global reduction 1 with 3 rules applied. Total rules applied 29 place count 80 transition count 100
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 1 with 3 rules applied. Total rules applied 32 place count 80 transition count 97
Applied a total of 32 rules in 4 ms. Remains 80 /94 variables (removed 14) and now considering 97/119 (removed 22) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 80/94 places, 97/119 transitions.
[2023-03-14 20:59:04] [INFO ] Flatten gal took : 4 ms
[2023-03-14 20:59:04] [INFO ] Flatten gal took : 5 ms
[2023-03-14 20:59:04] [INFO ] Input system was already deterministic with 97 transitions.
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 119/119 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 82 transition count 106
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 82 transition count 106
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 25 place count 82 transition count 105
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 28 place count 79 transition count 99
Iterating global reduction 1 with 3 rules applied. Total rules applied 31 place count 79 transition count 99
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 1 with 3 rules applied. Total rules applied 34 place count 79 transition count 96
Applied a total of 34 rules in 3 ms. Remains 79 /94 variables (removed 15) and now considering 96/119 (removed 23) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 79/94 places, 96/119 transitions.
[2023-03-14 20:59:04] [INFO ] Flatten gal took : 4 ms
[2023-03-14 20:59:04] [INFO ] Flatten gal took : 10 ms
[2023-03-14 20:59:04] [INFO ] Input system was already deterministic with 96 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 94/94 places, 119/119 transitions.
Graph (trivial) has 25 edges and 94 vertex of which 22 / 94 are part of one of the 11 SCC in 0 ms
Free SCC test removed 11 places
Ensure Unique test removed 11 transitions
Reduce isomorphic transitions removed 11 transitions.
Graph (complete) has 444 edges and 83 vertex of which 72 are kept as prefixes of interest. Removing 11 places using SCC suffix rule.0 ms
Discarding 11 places :
Also discarding 11 output transitions
Drop transitions removed 11 transitions
Reduce places removed 11 places and 0 transitions.
Ensure Unique test removed 10 transitions
Reduce isomorphic transitions removed 10 transitions.
Iterating post reduction 0 with 10 rules applied. Total rules applied 12 place count 61 transition count 87
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 15 place count 58 transition count 81
Iterating global reduction 1 with 3 rules applied. Total rules applied 18 place count 58 transition count 81
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 1 with 3 rules applied. Total rules applied 21 place count 58 transition count 78
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 2 with 9 rules applied. Total rules applied 30 place count 52 transition count 75
Applied a total of 30 rules in 8 ms. Remains 52 /94 variables (removed 42) and now considering 75/119 (removed 44) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 8 ms. Remains : 52/94 places, 75/119 transitions.
[2023-03-14 20:59:04] [INFO ] Flatten gal took : 3 ms
[2023-03-14 20:59:04] [INFO ] Flatten gal took : 3 ms
[2023-03-14 20:59:04] [INFO ] Input system was already deterministic with 75 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 94/94 places, 119/119 transitions.
Graph (trivial) has 33 edges and 94 vertex of which 28 / 94 are part of one of the 14 SCC in 1 ms
Free SCC test removed 14 places
Ensure Unique test removed 14 transitions
Reduce isomorphic transitions removed 14 transitions.
Graph (complete) has 440 edges and 80 vertex of which 68 are kept as prefixes of interest. Removing 12 places using SCC suffix rule.1 ms
Discarding 12 places :
Also discarding 12 output transitions
Drop transitions removed 12 transitions
Reduce places removed 14 places and 0 transitions.
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 0 with 13 rules applied. Total rules applied 15 place count 54 transition count 80
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 20 place count 49 transition count 56
Iterating global reduction 1 with 5 rules applied. Total rules applied 25 place count 49 transition count 56
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 1 with 5 rules applied. Total rules applied 30 place count 49 transition count 51
Performed 5 Post agglomeration using F-continuation condition.Transition count delta: 5
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 2 with 15 rules applied. Total rules applied 45 place count 39 transition count 46
Applied a total of 45 rules in 7 ms. Remains 39 /94 variables (removed 55) and now considering 46/119 (removed 73) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 7 ms. Remains : 39/94 places, 46/119 transitions.
[2023-03-14 20:59:04] [INFO ] Flatten gal took : 2 ms
[2023-03-14 20:59:04] [INFO ] Flatten gal took : 2 ms
[2023-03-14 20:59:04] [INFO ] Input system was already deterministic with 46 transitions.
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 119/119 transitions.
Discarding 11 places :
Symmetric choice reduction at 0 with 11 rule applications. Total rules 11 place count 83 transition count 108
Iterating global reduction 0 with 11 rules applied. Total rules applied 22 place count 83 transition count 108
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 25 place count 80 transition count 88
Iterating global reduction 0 with 3 rules applied. Total rules applied 28 place count 80 transition count 88
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 31 place count 80 transition count 85
Applied a total of 31 rules in 3 ms. Remains 80 /94 variables (removed 14) and now considering 85/119 (removed 34) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 80/94 places, 85/119 transitions.
[2023-03-14 20:59:04] [INFO ] Flatten gal took : 3 ms
[2023-03-14 20:59:04] [INFO ] Flatten gal took : 3 ms
[2023-03-14 20:59:04] [INFO ] Input system was already deterministic with 85 transitions.
Starting structural reductions in LTL mode, iteration 0 : 94/94 places, 119/119 transitions.
Discarding 9 places :
Symmetric choice reduction at 0 with 9 rule applications. Total rules 9 place count 85 transition count 109
Iterating global reduction 0 with 9 rules applied. Total rules applied 18 place count 85 transition count 109
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 19 place count 85 transition count 108
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 22 place count 82 transition count 102
Iterating global reduction 1 with 3 rules applied. Total rules applied 25 place count 82 transition count 102
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 1 with 3 rules applied. Total rules applied 28 place count 82 transition count 99
Applied a total of 28 rules in 2 ms. Remains 82 /94 variables (removed 12) and now considering 99/119 (removed 20) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 82/94 places, 99/119 transitions.
[2023-03-14 20:59:04] [INFO ] Flatten gal took : 4 ms
[2023-03-14 20:59:04] [INFO ] Flatten gal took : 3 ms
[2023-03-14 20:59:04] [INFO ] Input system was already deterministic with 99 transitions.
[2023-03-14 20:59:04] [INFO ] Flatten gal took : 6 ms
[2023-03-14 20:59:04] [INFO ] Flatten gal took : 6 ms
[2023-03-14 20:59:04] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-14 20:59:04] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 94 places, 119 transitions and 548 arcs took 1 ms.
Total runtime 1876 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT Planning-PT-none
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/372
CTLFireability

FORMULA Planning-PT-none-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678827975184

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/372/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/372/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/372/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 10 (type EXCL) for 9 Planning-PT-none-CTLFireability-03
lola: time limit : 171 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 53 (type FNDP) for 36 Planning-PT-none-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 54 (type EQUN) for 36 Planning-PT-none-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 56 (type SRCH) for 36 Planning-PT-none-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 56 (type SRCH) for Planning-PT-none-CTLFireability-12
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 53 (type FNDP) for Planning-PT-none-CTLFireability-12
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 54 (type EQUN) for Planning-PT-none-CTLFireability-12 (obsolete)
lola: FINISHED task # 54 (type EQUN) for Planning-PT-none-CTLFireability-12
lola: result : unknown
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/225 15/32 Planning-PT-none-CTLFireability-03 3523258 m, 704651 m/sec, 4697679 t fired, .

Time elapsed: 5 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 10/225 28/32 Planning-PT-none-CTLFireability-03 6943979 m, 684144 m/sec, 9258641 t fired, .

Time elapsed: 10 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 10 (type EXCL) for Planning-PT-none-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 15 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 50 (type EXCL) for 45 Planning-PT-none-CTLFireability-15
lola: time limit : 239 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-15: DISJ 0 1 1 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 5/239 7/32 Planning-PT-none-CTLFireability-15 1534770 m, 306954 m/sec, 3069540 t fired, .

Time elapsed: 20 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-15: DISJ 0 1 1 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 10/239 12/32 Planning-PT-none-CTLFireability-15 2960022 m, 285050 m/sec, 5920043 t fired, .

Time elapsed: 25 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-15: DISJ 0 1 1 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 15/239 18/32 Planning-PT-none-CTLFireability-15 4371710 m, 282337 m/sec, 8743420 t fired, .

Time elapsed: 30 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-15: DISJ 0 1 1 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 20/239 24/32 Planning-PT-none-CTLFireability-15 5779933 m, 281644 m/sec, 11559866 t fired, .

Time elapsed: 35 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-15: DISJ 0 1 1 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 25/239 29/32 Planning-PT-none-CTLFireability-15 7180152 m, 280043 m/sec, 14360303 t fired, .

Time elapsed: 40 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 50 (type EXCL) for Planning-PT-none-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-15: DISJ 0 1 0 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 45 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 48 (type EXCL) for 45 Planning-PT-none-CTLFireability-15
lola: time limit : 253 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 1 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 5/253 16/32 Planning-PT-none-CTLFireability-15 3902119 m, 780423 m/sec, 5202826 t fired, .

Time elapsed: 50 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 1 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 10/253 30/32 Planning-PT-none-CTLFireability-15 7441888 m, 707953 m/sec, 9922518 t fired, .

Time elapsed: 55 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 48 (type EXCL) for Planning-PT-none-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 60 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 43 (type EXCL) for 42 Planning-PT-none-CTLFireability-14
lola: time limit : 272 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 5/272 16/32 Planning-PT-none-CTLFireability-14 3820173 m, 764034 m/sec, 5093564 t fired, .

Time elapsed: 65 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 10/272 30/32 Planning-PT-none-CTLFireability-14 7317186 m, 699402 m/sec, 9756247 t fired, .

Time elapsed: 70 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 43 (type EXCL) for Planning-PT-none-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 75 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 34 (type EXCL) for 33 Planning-PT-none-CTLFireability-11
lola: time limit : 293 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 5/293 16/32 Planning-PT-none-CTLFireability-11 3790020 m, 758004 m/sec, 5053358 t fired, .

Time elapsed: 80 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 10/293 30/32 Planning-PT-none-CTLFireability-11 7278583 m, 697712 m/sec, 9704776 t fired, .

Time elapsed: 85 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 34 (type EXCL) for Planning-PT-none-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 90 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 31 (type EXCL) for 30 Planning-PT-none-CTLFireability-10
lola: time limit : 319 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 5/319 16/32 Planning-PT-none-CTLFireability-10 3834207 m, 766841 m/sec, 5112275 t fired, .

Time elapsed: 95 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 10/319 30/32 Planning-PT-none-CTLFireability-10 7371179 m, 707394 m/sec, 9828238 t fired, .

Time elapsed: 100 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 31 (type EXCL) for Planning-PT-none-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 105 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 28 (type EXCL) for 27 Planning-PT-none-CTLFireability-09
lola: time limit : 349 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 5/349 10/32 Planning-PT-none-CTLFireability-09 2478560 m, 495712 m/sec, 5783303 t fired, .

Time elapsed: 110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 10/349 19/32 Planning-PT-none-CTLFireability-09 4732357 m, 450759 m/sec, 11042164 t fired, .

Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 15/349 28/32 Planning-PT-none-CTLFireability-09 6959557 m, 445440 m/sec, 16238963 t fired, .

Time elapsed: 120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 28 (type EXCL) for Planning-PT-none-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 22 (type EXCL) for 21 Planning-PT-none-CTLFireability-07
lola: time limit : 386 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 5/386 3/32 Planning-PT-none-CTLFireability-07 583439 m, 116687 m/sec, 1750316 t fired, .

Time elapsed: 130 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 10/386 5/32 Planning-PT-none-CTLFireability-07 1129900 m, 109292 m/sec, 3389699 t fired, .

Time elapsed: 135 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 15/386 7/32 Planning-PT-none-CTLFireability-07 1672978 m, 108615 m/sec, 5018933 t fired, .

Time elapsed: 140 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 20/386 9/32 Planning-PT-none-CTLFireability-07 2214072 m, 108218 m/sec, 6642215 t fired, .

Time elapsed: 145 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 25/386 12/32 Planning-PT-none-CTLFireability-07 2754290 m, 108043 m/sec, 8262869 t fired, .

Time elapsed: 150 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 30/386 14/32 Planning-PT-none-CTLFireability-07 3292465 m, 107635 m/sec, 9877394 t fired, .

Time elapsed: 155 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 35/386 16/32 Planning-PT-none-CTLFireability-07 3829546 m, 107416 m/sec, 11488638 t fired, .

Time elapsed: 160 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 40/386 18/32 Planning-PT-none-CTLFireability-07 4366082 m, 107307 m/sec, 13098245 t fired, .

Time elapsed: 165 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 45/386 20/32 Planning-PT-none-CTLFireability-07 4903899 m, 107563 m/sec, 14711695 t fired, .

Time elapsed: 170 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 50/386 22/32 Planning-PT-none-CTLFireability-07 5440037 m, 107227 m/sec, 16320111 t fired, .

Time elapsed: 175 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 55/386 24/32 Planning-PT-none-CTLFireability-07 5974093 m, 106811 m/sec, 17922278 t fired, .

Time elapsed: 180 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 60/386 27/32 Planning-PT-none-CTLFireability-07 6508071 m, 106795 m/sec, 19524212 t fired, .

Time elapsed: 185 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 65/386 29/32 Planning-PT-none-CTLFireability-07 7042531 m, 106892 m/sec, 21127592 t fired, .

Time elapsed: 190 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 70/386 31/32 Planning-PT-none-CTLFireability-07 7575591 m, 106612 m/sec, 22726772 t fired, .

Time elapsed: 195 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 22 (type EXCL) for Planning-PT-none-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 200 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 19 (type EXCL) for 18 Planning-PT-none-CTLFireability-06
lola: time limit : 425 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 5/425 16/32 Planning-PT-none-CTLFireability-06 3856749 m, 771349 m/sec, 5142331 t fired, .

Time elapsed: 205 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 10/425 30/32 Planning-PT-none-CTLFireability-06 7371403 m, 702930 m/sec, 9828536 t fired, .

Time elapsed: 210 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 19 (type EXCL) for Planning-PT-none-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 215 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 16 (type EXCL) for 15 Planning-PT-none-CTLFireability-05
lola: time limit : 483 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 5/483 16/32 Planning-PT-none-CTLFireability-05 3748328 m, 749665 m/sec, 4997771 t fired, .

Time elapsed: 220 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 10/483 29/32 Planning-PT-none-CTLFireability-05 7199956 m, 690325 m/sec, 9599942 t fired, .

Time elapsed: 225 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 16 (type EXCL) for Planning-PT-none-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 230 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 13 (type EXCL) for 12 Planning-PT-none-CTLFireability-04
lola: time limit : 561 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/561 16/32 Planning-PT-none-CTLFireability-04 3830331 m, 766066 m/sec, 5107106 t fired, .

Time elapsed: 235 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 10/561 30/32 Planning-PT-none-CTLFireability-04 7361103 m, 706154 m/sec, 9814801 t fired, .

Time elapsed: 240 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 13 (type EXCL) for Planning-PT-none-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 245 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 7 (type EXCL) for 6 Planning-PT-none-CTLFireability-02
lola: time limit : 671 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/671 4/32 Planning-PT-none-CTLFireability-02 849091 m, 169818 m/sec, 1698184 t fired, .

Time elapsed: 250 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/671 7/32 Planning-PT-none-CTLFireability-02 1645215 m, 159224 m/sec, 3290432 t fired, .

Time elapsed: 255 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/671 10/32 Planning-PT-none-CTLFireability-02 2435992 m, 158155 m/sec, 4871986 t fired, .

Time elapsed: 260 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/671 13/32 Planning-PT-none-CTLFireability-02 3222688 m, 157339 m/sec, 6445378 t fired, .

Time elapsed: 265 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 25/671 17/32 Planning-PT-none-CTLFireability-02 4007768 m, 157016 m/sec, 8015537 t fired, .

Time elapsed: 270 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 30/671 20/32 Planning-PT-none-CTLFireability-02 4793811 m, 157208 m/sec, 9587624 t fired, .

Time elapsed: 275 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 35/671 23/32 Planning-PT-none-CTLFireability-02 5577766 m, 156791 m/sec, 11155534 t fired, .

Time elapsed: 280 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 40/671 26/32 Planning-PT-none-CTLFireability-02 6358469 m, 156140 m/sec, 12716940 t fired, .

Time elapsed: 285 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 45/671 29/32 Planning-PT-none-CTLFireability-02 7140509 m, 156408 m/sec, 14281020 t fired, .

Time elapsed: 290 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 50/671 32/32 Planning-PT-none-CTLFireability-02 7919610 m, 155820 m/sec, 15839222 t fired, .

Time elapsed: 295 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 7 (type EXCL) for Planning-PT-none-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 300 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 4 (type EXCL) for 3 Planning-PT-none-CTLFireability-01
lola: time limit : 825 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/825 5/32 Planning-PT-none-CTLFireability-01 1209015 m, 241803 m/sec, 5239065 t fired, .

Time elapsed: 305 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/825 10/32 Planning-PT-none-CTLFireability-01 2367196 m, 231636 m/sec, 10257845 t fired, .

Time elapsed: 310 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/825 14/32 Planning-PT-none-CTLFireability-01 3492566 m, 225074 m/sec, 15134453 t fired, .

Time elapsed: 315 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 20/825 19/32 Planning-PT-none-CTLFireability-01 4602869 m, 222060 m/sec, 19945759 t fired, .

Time elapsed: 320 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 25/825 23/32 Planning-PT-none-CTLFireability-01 5700702 m, 219566 m/sec, 24703037 t fired, .

Time elapsed: 325 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 30/825 28/32 Planning-PT-none-CTLFireability-01 6790882 m, 218036 m/sec, 29427151 t fired, .

Time elapsed: 330 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 35/825 32/32 Planning-PT-none-CTLFireability-01 7866211 m, 215065 m/sec, 34086914 t fired, .

Time elapsed: 335 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 4 (type EXCL) for Planning-PT-none-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 340 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 52 (type EXCL) for 39 Planning-PT-none-CTLFireability-13
lola: time limit : 1086 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 AGEF EXCL 5/1086 17/32 Planning-PT-none-CTLFireability-13 4376979 m, 875395 m/sec, 4376979 t fired, .

Time elapsed: 345 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 AGEF EXCL 12/1086 28/32 Planning-PT-none-CTLFireability-13 7340018 m, 592607 m/sec, 7340018 t fired, .

Time elapsed: 352 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 52 (type EXCL) for Planning-PT-none-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 357 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 1 (type EXCL) for 0 Planning-PT-none-CTLFireability-00
lola: time limit : 1621 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/1621 6/32 Planning-PT-none-CTLFireability-00 1289532 m, 257906 m/sec, 6447656 t fired, .

Time elapsed: 362 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 11/1621 11/32 Planning-PT-none-CTLFireability-00 2571100 m, 256313 m/sec, 12855499 t fired, .

Time elapsed: 368 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 17/1621 17/32 Planning-PT-none-CTLFireability-00 3833942 m, 252568 m/sec, 19169706 t fired, .

Time elapsed: 374 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 22/1621 22/32 Planning-PT-none-CTLFireability-00 5077468 m, 248705 m/sec, 25387340 t fired, .

Time elapsed: 379 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 27/1621 23/32 Planning-PT-none-CTLFireability-00 5258286 m, 36163 m/sec, 26291426 t fired, .

Time elapsed: 384 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 32/1621 26/32 Planning-PT-none-CTLFireability-00 6143371 m, 177017 m/sec, 30716854 t fired, .

Time elapsed: 389 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 37/1621 31/32 Planning-PT-none-CTLFireability-00 7239330 m, 219191 m/sec, 36196648 t fired, .

Time elapsed: 394 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 1 (type EXCL) for Planning-PT-none-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 399 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 25 (type EXCL) for 24 Planning-PT-none-CTLFireability-08
lola: time limit : 3201 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 5/3201 9/32 Planning-PT-none-CTLFireability-08 1803711 m, 360742 m/sec, 7214841 t fired, .

Time elapsed: 404 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 10/3201 16/32 Planning-PT-none-CTLFireability-08 3443870 m, 328031 m/sec, 13775479 t fired, .

Time elapsed: 409 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 15/3201 23/32 Planning-PT-none-CTLFireability-08 5009006 m, 313027 m/sec, 20036021 t fired, .

Time elapsed: 414 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 20/3201 26/32 Planning-PT-none-CTLFireability-08 5639123 m, 126023 m/sec, 22556491 t fired, .

Time elapsed: 419 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 25/3201 32/32 Planning-PT-none-CTLFireability-08 6967989 m, 265773 m/sec, 27871955 t fired, .

Time elapsed: 424 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 25 (type EXCL) for Planning-PT-none-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-12: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-13: EFAG 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-15: DISJ 0 0 0 0 2 0 2 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 429 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-00: CTL unknown AGGR
Planning-PT-none-CTLFireability-01: CTL unknown AGGR
Planning-PT-none-CTLFireability-02: CTL unknown AGGR
Planning-PT-none-CTLFireability-03: CTL unknown AGGR
Planning-PT-none-CTLFireability-04: CTL unknown AGGR
Planning-PT-none-CTLFireability-05: CTL unknown AGGR
Planning-PT-none-CTLFireability-06: CTL unknown AGGR
Planning-PT-none-CTLFireability-07: CTL unknown AGGR
Planning-PT-none-CTLFireability-08: CTL unknown AGGR
Planning-PT-none-CTLFireability-09: CTL unknown AGGR
Planning-PT-none-CTLFireability-10: CTL unknown AGGR
Planning-PT-none-CTLFireability-11: CTL unknown AGGR
Planning-PT-none-CTLFireability-12: EF true findpath
Planning-PT-none-CTLFireability-13: EFAG unknown AGGR
Planning-PT-none-CTLFireability-14: CTL unknown AGGR
Planning-PT-none-CTLFireability-15: DISJ unknown DISJ


Time elapsed: 429 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Planning-PT-none"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is Planning-PT-none, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r295-tall-167873947700338"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/Planning-PT-none.tgz
mv Planning-PT-none execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;