Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r295-tall-167873947400066.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..........................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is PhaseVariation-PT-D30CS010, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r295-tall-167873947400066
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 31M
-rw-r--r-- 1 mcc users 8.2K Feb 26 15:27 CTLCardinality.txt
-rw-r--r-- 1 mcc users 72K Feb 26 15:27 CTLCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 26 15:13 CTLFireability.txt
-rw-r--r-- 1 mcc users 66K Feb 26 15:13 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.1K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 5.0K Feb 25 16:32 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K Feb 25 16:32 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 16:32 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 16:32 LTLFireability.xml
-rw-r--r-- 1 mcc users 17K Feb 26 15:48 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 144K Feb 26 15:48 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 18K Feb 26 15:33 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 95K Feb 26 15:33 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 25 16:32 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Feb 25 16:32 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 9 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 30M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME PhaseVariation-PT-D30CS010-CTLFireability-00
FORMULA_NAME PhaseVariation-PT-D30CS010-CTLFireability-01
FORMULA_NAME PhaseVariation-PT-D30CS010-CTLFireability-02
FORMULA_NAME PhaseVariation-PT-D30CS010-CTLFireability-03
FORMULA_NAME PhaseVariation-PT-D30CS010-CTLFireability-04
FORMULA_NAME PhaseVariation-PT-D30CS010-CTLFireability-05
FORMULA_NAME PhaseVariation-PT-D30CS010-CTLFireability-06
FORMULA_NAME PhaseVariation-PT-D30CS010-CTLFireability-07
FORMULA_NAME PhaseVariation-PT-D30CS010-CTLFireability-08
FORMULA_NAME PhaseVariation-PT-D30CS010-CTLFireability-09
FORMULA_NAME PhaseVariation-PT-D30CS010-CTLFireability-10
FORMULA_NAME PhaseVariation-PT-D30CS010-CTLFireability-11
FORMULA_NAME PhaseVariation-PT-D30CS010-CTLFireability-12
FORMULA_NAME PhaseVariation-PT-D30CS010-CTLFireability-13
FORMULA_NAME PhaseVariation-PT-D30CS010-CTLFireability-14
FORMULA_NAME PhaseVariation-PT-D30CS010-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678779733303

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=PhaseVariation-PT-D30CS010
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-14 07:42:14] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-14 07:42:14] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-14 07:42:15] [INFO ] Load time of PNML (sax parser for PT used): 932 ms
[2023-03-14 07:42:15] [INFO ] Transformed 2702 places.
[2023-03-14 07:42:15] [INFO ] Transformed 30977 transitions.
[2023-03-14 07:42:15] [INFO ] Parsed PT model containing 2702 places and 30977 transitions and 215035 arcs in 1226 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 16 ms.
Deduced a syphon composed of 2 places in 44 ms
Reduce places removed 2 places and 52 transitions.
Reduce places removed 1 places and 0 transitions.
Support contains 270 out of 2699 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 2699/2699 places, 30925/30925 transitions.
Applied a total of 0 rules in 865 ms. Remains 2699 /2699 variables (removed 0) and now considering 30925/30925 (removed 0) transitions.
[2023-03-14 07:42:17] [INFO ] Flow matrix only has 1799 transitions (discarded 29126 similar events)
// Phase 1: matrix 1799 rows 2699 cols
[2023-03-14 07:42:17] [INFO ] Computed 900 place invariants in 98 ms
[2023-03-14 07:42:30] [INFO ] Dead Transitions using invariants and state equation in 13643 ms found 3596 transitions.
Found 3596 dead transitions using SMT.
Drop transitions removed 3596 transitions
Dead transitions reduction (with SMT) triggered by suspicious arc values removed 3596 transitions.
[2023-03-14 07:42:30] [INFO ] Flow matrix only has 1799 transitions (discarded 25530 similar events)
[2023-03-14 07:42:30] [INFO ] Invariant cache hit.
[2023-03-14 07:42:33] [INFO ] Implicit Places using invariants in 2763 ms returned []
Implicit Place search using SMT only with invariants took 2767 ms to find 0 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 2699/2699 places, 27329/30925 transitions.
Discarding 764 places :
Symmetric choice reduction at 0 with 764 rule applications. Total rules 764 place count 1935 transition count 15745
Iterating global reduction 0 with 764 rules applied. Total rules applied 1528 place count 1935 transition count 15745
Ensure Unique test removed 6684 transitions
Reduce isomorphic transitions removed 6684 transitions.
Iterating post reduction 0 with 6684 rules applied. Total rules applied 8212 place count 1935 transition count 9061
Drop transitions removed 84 transitions
Redundant transition composition rules discarded 84 transitions
Iterating global reduction 1 with 84 rules applied. Total rules applied 8296 place count 1935 transition count 8977
Applied a total of 8296 rules in 1057 ms. Remains 1935 /2699 variables (removed 764) and now considering 8977/27329 (removed 18352) transitions.
[2023-03-14 07:42:34] [INFO ] Flow matrix only has 1035 transitions (discarded 7942 similar events)
// Phase 1: matrix 1035 rows 1935 cols
[2023-03-14 07:42:34] [INFO ] Computed 900 place invariants in 22 ms
[2023-03-14 07:42:36] [INFO ] Implicit Places using invariants in 1678 ms returned []
[2023-03-14 07:42:36] [INFO ] Flow matrix only has 1035 transitions (discarded 7942 similar events)
[2023-03-14 07:42:36] [INFO ] Invariant cache hit.
[2023-03-14 07:42:37] [INFO ] State equation strengthened by 1025 read => feed constraints.
[2023-03-14 07:42:45] [INFO ] Implicit Places using invariants and state equation in 9214 ms returned []
Implicit Place search using SMT with State Equation took 10897 ms to find 0 implicit places.
Starting structural reductions in LTL mode, iteration 2 : 1935/2699 places, 8977/30925 transitions.
Finished structural reductions in LTL mode , in 2 iterations and 29339 ms. Remains : 1935/2699 places, 8977/30925 transitions.
Support contains 270 out of 1935 places after structural reductions.
[2023-03-14 07:42:46] [INFO ] Flatten gal took : 520 ms
[2023-03-14 07:42:46] [INFO ] Flatten gal took : 417 ms
[2023-03-14 07:42:47] [INFO ] Input system was already deterministic with 8977 transitions.
Support contains 265 out of 1935 places (down from 270) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 110 resets, run finished after 822 ms. (steps per millisecond=12 ) properties (out of 101) seen :62
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 39 ms. (steps per millisecond=25 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 39) seen :0
Running SMT prover for 39 properties.
[2023-03-14 07:42:49] [INFO ] Flow matrix only has 1035 transitions (discarded 7942 similar events)
[2023-03-14 07:42:49] [INFO ] Invariant cache hit.
[2023-03-14 07:42:50] [INFO ] [Real]Absence check using 900 positive place invariants in 137 ms returned sat
[2023-03-14 07:42:53] [INFO ] After 2049ms SMT Verify possible using state equation in real domain returned unsat :10 sat :13 real:16
[2023-03-14 07:42:53] [INFO ] State equation strengthened by 1025 read => feed constraints.
[2023-03-14 07:42:54] [INFO ] After 1324ms SMT Verify possible using 1025 Read/Feed constraints in real domain returned unsat :10 sat :12 real:17
[2023-03-14 07:42:56] [INFO ] After 2449ms SMT Verify possible using trap constraints in real domain returned unsat :10 sat :12 real:17
Attempting to minimize the solution found.
Minimization took 653 ms.
[2023-03-14 07:42:56] [INFO ] After 7668ms SMT Verify possible using all constraints in real domain returned unsat :10 sat :12 real:17
[2023-03-14 07:42:57] [INFO ] [Nat]Absence check using 900 positive place invariants in 150 ms returned sat
[2023-03-14 07:43:00] [INFO ] After 1948ms SMT Verify possible using state equation in natural domain returned unsat :10 sat :29
[2023-03-14 07:43:02] [INFO ] After 2187ms SMT Verify possible using 1025 Read/Feed constraints in natural domain returned unsat :10 sat :29
[2023-03-14 07:43:05] [INFO ] After 4987ms SMT Verify possible using trap constraints in natural domain returned unsat :10 sat :29
Attempting to minimize the solution found.
Minimization took 1596 ms.
[2023-03-14 07:43:07] [INFO ] After 10559ms SMT Verify possible using all constraints in natural domain returned unsat :10 sat :29
Fused 39 Parikh solutions to 11 different solutions.
Parikh walk visited 0 properties in 110 ms.
Support contains 71 out of 1935 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1935/1935 places, 8977/8977 transitions.
Discarding 101 places :
Symmetric choice reduction at 0 with 101 rule applications. Total rules 101 place count 1834 transition count 8083
Iterating global reduction 0 with 101 rules applied. Total rules applied 202 place count 1834 transition count 8083
Ensure Unique test removed 798 transitions
Reduce isomorphic transitions removed 798 transitions.
Iterating post reduction 0 with 798 rules applied. Total rules applied 1000 place count 1834 transition count 7285
Applied a total of 1000 rules in 3872 ms. Remains 1834 /1935 variables (removed 101) and now considering 7285/8977 (removed 1692) transitions.
[2023-03-14 07:43:11] [INFO ] Flow matrix only has 934 transitions (discarded 6351 similar events)
// Phase 1: matrix 934 rows 1834 cols
[2023-03-14 07:43:11] [INFO ] Computed 900 place invariants in 21 ms
[2023-03-14 07:43:14] [INFO ] Dead Transitions using invariants and state equation in 2935 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 6809 ms. Remains : 1834/1935 places, 7285/8977 transitions.
Incomplete random walk after 10000 steps, including 122 resets, run finished after 540 ms. (steps per millisecond=18 ) properties (out of 29) seen :15
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 127 ms. (steps per millisecond=78 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 123 ms. (steps per millisecond=81 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 127 ms. (steps per millisecond=78 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 123 ms. (steps per millisecond=81 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 124 ms. (steps per millisecond=80 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 125 ms. (steps per millisecond=80 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 122 ms. (steps per millisecond=81 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 122 ms. (steps per millisecond=81 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 123 ms. (steps per millisecond=81 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 137 ms. (steps per millisecond=73 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 124 ms. (steps per millisecond=80 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 123 ms. (steps per millisecond=81 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 122 ms. (steps per millisecond=81 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 122 ms. (steps per millisecond=81 ) properties (out of 14) seen :0
Running SMT prover for 14 properties.
[2023-03-14 07:43:16] [INFO ] Flow matrix only has 934 transitions (discarded 6351 similar events)
[2023-03-14 07:43:16] [INFO ] Invariant cache hit.
[2023-03-14 07:43:17] [INFO ] [Real]Absence check using 900 positive place invariants in 140 ms returned sat
[2023-03-14 07:43:18] [INFO ] After 1188ms SMT Verify possible using state equation in real domain returned unsat :0 sat :4 real:10
[2023-03-14 07:43:18] [INFO ] State equation strengthened by 925 read => feed constraints.
[2023-03-14 07:43:19] [INFO ] After 744ms SMT Verify possible using 925 Read/Feed constraints in real domain returned unsat :0 sat :3 real:11
[2023-03-14 07:43:19] [INFO ] After 1002ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :3 real:11
Attempting to minimize the solution found.
Minimization took 152 ms.
[2023-03-14 07:43:19] [INFO ] After 3442ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :3 real:11
[2023-03-14 07:43:20] [INFO ] [Nat]Absence check using 900 positive place invariants in 139 ms returned sat
[2023-03-14 07:43:22] [INFO ] After 1149ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :14
[2023-03-14 07:43:23] [INFO ] After 1224ms SMT Verify possible using 925 Read/Feed constraints in natural domain returned unsat :0 sat :14
[2023-03-14 07:43:24] [INFO ] After 2507ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :14
Attempting to minimize the solution found.
Minimization took 705 ms.
[2023-03-14 07:43:25] [INFO ] After 5398ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :14
Fused 14 Parikh solutions to 2 different solutions.
Parikh walk visited 0 properties in 2 ms.
Support contains 41 out of 1834 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1834/1834 places, 7285/7285 transitions.
Discarding 15 places :
Symmetric choice reduction at 0 with 15 rule applications. Total rules 15 place count 1819 transition count 7165
Iterating global reduction 0 with 15 rules applied. Total rules applied 30 place count 1819 transition count 7165
Ensure Unique test removed 120 transitions
Reduce isomorphic transitions removed 120 transitions.
Iterating post reduction 0 with 120 rules applied. Total rules applied 150 place count 1819 transition count 7045
Applied a total of 150 rules in 3459 ms. Remains 1819 /1834 variables (removed 15) and now considering 7045/7285 (removed 240) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 3459 ms. Remains : 1819/1834 places, 7045/7285 transitions.
Incomplete random walk after 10000 steps, including 92 resets, run finished after 561 ms. (steps per millisecond=17 ) properties (out of 14) seen :7
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 122 ms. (steps per millisecond=81 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 122 ms. (steps per millisecond=81 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 123 ms. (steps per millisecond=81 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 134 ms. (steps per millisecond=74 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 122 ms. (steps per millisecond=81 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 123 ms. (steps per millisecond=81 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 122 ms. (steps per millisecond=81 ) properties (out of 7) seen :0
Running SMT prover for 7 properties.
[2023-03-14 07:43:30] [INFO ] Flow matrix only has 919 transitions (discarded 6126 similar events)
// Phase 1: matrix 919 rows 1819 cols
[2023-03-14 07:43:30] [INFO ] Computed 900 place invariants in 26 ms
[2023-03-14 07:43:30] [INFO ] [Real]Absence check using 900 positive place invariants in 139 ms returned sat
[2023-03-14 07:43:31] [INFO ] After 838ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1 real:6
[2023-03-14 07:43:31] [INFO ] State equation strengthened by 910 read => feed constraints.
[2023-03-14 07:43:32] [INFO ] After 383ms SMT Verify possible using 910 Read/Feed constraints in real domain returned unsat :0 sat :0 real:7
[2023-03-14 07:43:32] [INFO ] After 1931ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:7
[2023-03-14 07:43:32] [INFO ] [Nat]Absence check using 900 positive place invariants in 155 ms returned sat
[2023-03-14 07:43:33] [INFO ] After 833ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :7
[2023-03-14 07:43:34] [INFO ] After 679ms SMT Verify possible using 910 Read/Feed constraints in natural domain returned unsat :0 sat :7
[2023-03-14 07:43:35] [INFO ] After 1295ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :7
Attempting to minimize the solution found.
Minimization took 348 ms.
[2023-03-14 07:43:35] [INFO ] After 3153ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :7
Fused 7 Parikh solutions to 2 different solutions.
Parikh walk visited 0 properties in 2 ms.
Support contains 27 out of 1819 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1819/1819 places, 7045/7045 transitions.
Discarding 7 places :
Symmetric choice reduction at 0 with 7 rule applications. Total rules 7 place count 1812 transition count 6994
Iterating global reduction 0 with 7 rules applied. Total rules applied 14 place count 1812 transition count 6994
Ensure Unique test removed 51 transitions
Reduce isomorphic transitions removed 51 transitions.
Iterating post reduction 0 with 51 rules applied. Total rules applied 65 place count 1812 transition count 6943
Applied a total of 65 rules in 3411 ms. Remains 1812 /1819 variables (removed 7) and now considering 6943/7045 (removed 102) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 3411 ms. Remains : 1812/1819 places, 6943/7045 transitions.
Incomplete random walk after 10000 steps, including 128 resets, run finished after 455 ms. (steps per millisecond=21 ) properties (out of 7) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 122 ms. (steps per millisecond=81 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 122 ms. (steps per millisecond=81 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 122 ms. (steps per millisecond=81 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 122 ms. (steps per millisecond=81 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 123 ms. (steps per millisecond=81 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 122 ms. (steps per millisecond=81 ) properties (out of 6) seen :0
Running SMT prover for 6 properties.
[2023-03-14 07:43:39] [INFO ] Flow matrix only has 912 transitions (discarded 6031 similar events)
// Phase 1: matrix 912 rows 1812 cols
[2023-03-14 07:43:40] [INFO ] Computed 900 place invariants in 23 ms
[2023-03-14 07:43:40] [INFO ] [Real]Absence check using 900 positive place invariants in 137 ms returned sat
[2023-03-14 07:43:41] [INFO ] After 1375ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:6
[2023-03-14 07:43:41] [INFO ] [Nat]Absence check using 900 positive place invariants in 141 ms returned sat
[2023-03-14 07:43:42] [INFO ] After 791ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :6
[2023-03-14 07:43:42] [INFO ] State equation strengthened by 903 read => feed constraints.
[2023-03-14 07:43:43] [INFO ] After 428ms SMT Verify possible using 903 Read/Feed constraints in natural domain returned unsat :0 sat :6
[2023-03-14 07:43:43] [INFO ] After 949ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :6
Attempting to minimize the solution found.
Minimization took 303 ms.
[2023-03-14 07:43:44] [INFO ] After 2676ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :6
Fused 6 Parikh solutions to 4 different solutions.
Parikh walk visited 0 properties in 2 ms.
Support contains 25 out of 1812 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1812/1812 places, 6943/6943 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 1811 transition count 6935
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 1811 transition count 6935
Ensure Unique test removed 8 transitions
Reduce isomorphic transitions removed 8 transitions.
Iterating post reduction 0 with 8 rules applied. Total rules applied 10 place count 1811 transition count 6927
Applied a total of 10 rules in 3474 ms. Remains 1811 /1812 variables (removed 1) and now considering 6927/6943 (removed 16) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 3477 ms. Remains : 1811/1812 places, 6927/6943 transitions.
Incomplete random walk after 10000 steps, including 88 resets, run finished after 481 ms. (steps per millisecond=20 ) properties (out of 6) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 124 ms. (steps per millisecond=80 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 122 ms. (steps per millisecond=81 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 122 ms. (steps per millisecond=81 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 122 ms. (steps per millisecond=81 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 121 ms. (steps per millisecond=82 ) properties (out of 5) seen :0
Running SMT prover for 5 properties.
[2023-03-14 07:43:48] [INFO ] Flow matrix only has 911 transitions (discarded 6016 similar events)
// Phase 1: matrix 911 rows 1811 cols
[2023-03-14 07:43:48] [INFO ] Computed 900 place invariants in 21 ms
[2023-03-14 07:43:49] [INFO ] [Real]Absence check using 900 positive place invariants in 138 ms returned sat
[2023-03-14 07:43:49] [INFO ] After 1296ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:5
[2023-03-14 07:43:50] [INFO ] [Nat]Absence check using 900 positive place invariants in 139 ms returned sat
[2023-03-14 07:43:51] [INFO ] After 735ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :5
[2023-03-14 07:43:51] [INFO ] State equation strengthened by 902 read => feed constraints.
[2023-03-14 07:43:51] [INFO ] After 455ms SMT Verify possible using 902 Read/Feed constraints in natural domain returned unsat :0 sat :5
[2023-03-14 07:43:52] [INFO ] After 895ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :5
Attempting to minimize the solution found.
Minimization took 248 ms.
[2023-03-14 07:43:52] [INFO ] After 2466ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :5
Fused 5 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 23 out of 1811 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1811/1811 places, 6927/6927 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 1810 transition count 6919
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 1810 transition count 6919
Ensure Unique test removed 8 transitions
Reduce isomorphic transitions removed 8 transitions.
Iterating post reduction 0 with 8 rules applied. Total rules applied 10 place count 1810 transition count 6911
Applied a total of 10 rules in 3445 ms. Remains 1810 /1811 variables (removed 1) and now considering 6911/6927 (removed 16) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 3445 ms. Remains : 1810/1811 places, 6911/6927 transitions.
Incomplete random walk after 10000 steps, including 81 resets, run finished after 468 ms. (steps per millisecond=21 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 122 ms. (steps per millisecond=81 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 122 ms. (steps per millisecond=81 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 122 ms. (steps per millisecond=81 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 123 ms. (steps per millisecond=81 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 122 ms. (steps per millisecond=81 ) properties (out of 5) seen :0
Interrupted probabilistic random walk after 65667 steps, run timeout after 3001 ms. (steps per millisecond=21 ) properties seen :{}
Probabilistic random walk after 65667 steps, saw 61153 distinct states, run finished after 3003 ms. (steps per millisecond=21 ) properties seen :0
Running SMT prover for 5 properties.
[2023-03-14 07:43:59] [INFO ] Flow matrix only has 910 transitions (discarded 6001 similar events)
// Phase 1: matrix 910 rows 1810 cols
[2023-03-14 07:44:00] [INFO ] Computed 900 place invariants in 27 ms
[2023-03-14 07:44:00] [INFO ] [Real]Absence check using 900 positive place invariants in 140 ms returned sat
[2023-03-14 07:44:01] [INFO ] After 1305ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:5
[2023-03-14 07:44:01] [INFO ] [Nat]Absence check using 900 positive place invariants in 143 ms returned sat
[2023-03-14 07:44:02] [INFO ] After 743ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :5
[2023-03-14 07:44:02] [INFO ] State equation strengthened by 901 read => feed constraints.
[2023-03-14 07:44:03] [INFO ] After 351ms SMT Verify possible using 901 Read/Feed constraints in natural domain returned unsat :0 sat :5
[2023-03-14 07:44:03] [INFO ] After 797ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :5
Attempting to minimize the solution found.
Minimization took 248 ms.
[2023-03-14 07:44:03] [INFO ] After 2390ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :5
Fused 5 Parikh solutions to 3 different solutions.
Parikh walk visited 0 properties in 1 ms.
Support contains 23 out of 1810 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1810/1810 places, 6911/6911 transitions.
Applied a total of 0 rules in 3224 ms. Remains 1810 /1810 variables (removed 0) and now considering 6911/6911 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 3226 ms. Remains : 1810/1810 places, 6911/6911 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1810/1810 places, 6911/6911 transitions.
Applied a total of 0 rules in 3238 ms. Remains 1810 /1810 variables (removed 0) and now considering 6911/6911 (removed 0) transitions.
[2023-03-14 07:44:10] [INFO ] Flow matrix only has 910 transitions (discarded 6001 similar events)
[2023-03-14 07:44:10] [INFO ] Invariant cache hit.
[2023-03-14 07:44:11] [INFO ] Implicit Places using invariants in 1734 ms returned []
[2023-03-14 07:44:11] [INFO ] Flow matrix only has 910 transitions (discarded 6001 similar events)
[2023-03-14 07:44:11] [INFO ] Invariant cache hit.
[2023-03-14 07:44:12] [INFO ] State equation strengthened by 901 read => feed constraints.
[2023-03-14 07:44:20] [INFO ] Implicit Places using invariants and state equation in 8549 ms returned []
Implicit Place search using SMT with State Equation took 10289 ms to find 0 implicit places.
[2023-03-14 07:44:21] [INFO ] Redundant transitions in 728 ms returned []
[2023-03-14 07:44:21] [INFO ] Flow matrix only has 910 transitions (discarded 6001 similar events)
[2023-03-14 07:44:21] [INFO ] Invariant cache hit.
[2023-03-14 07:44:23] [INFO ] Dead Transitions using invariants and state equation in 2783 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 17046 ms. Remains : 1810/1810 places, 6911/6911 transitions.
Graph (complete) has 1808 edges and 1810 vertex of which 33 are kept as prefixes of interest. Removing 1777 places using SCC suffix rule.1 ms
Discarding 1777 places :
Also discarding 6689 output transitions
Drop transitions removed 6689 transitions
Drop transitions removed 59 transitions
Ensure Unique test removed 140 transitions
Reduce isomorphic transitions removed 199 transitions.
Iterating post reduction 0 with 199 rules applied. Total rules applied 200 place count 33 transition count 23
Applied a total of 200 rules in 11 ms. Remains 33 /1810 variables (removed 1777) and now considering 23/6911 (removed 6888) transitions.
Running SMT prover for 5 properties.
// Phase 1: matrix 23 rows 33 cols
[2023-03-14 07:44:24] [INFO ] Computed 10 place invariants in 0 ms
[2023-03-14 07:44:24] [INFO ] [Real]Absence check using 10 positive place invariants in 1 ms returned sat
[2023-03-14 07:44:24] [INFO ] After 13ms SMT Verify possible using state equation in real domain returned unsat :0 sat :5
[2023-03-14 07:44:24] [INFO ] After 24ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :5
Attempting to minimize the solution found.
Minimization took 7 ms.
[2023-03-14 07:44:24] [INFO ] After 64ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :5
Successfully simplified 10 atomic propositions for a total of 16 simplifications.
[2023-03-14 07:44:24] [INFO ] Flatten gal took : 282 ms
[2023-03-14 07:44:24] [INFO ] Flatten gal took : 286 ms
[2023-03-14 07:44:25] [INFO ] Input system was already deterministic with 8977 transitions.
Computed a total of 1935 stabilizing places and 8977 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 1935 transition count 8977
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 1 formulas.
Starting structural reductions in LTL mode, iteration 0 : 1935/1935 places, 8977/8977 transitions.
Discarding 127 places :
Symmetric choice reduction at 0 with 127 rule applications. Total rules 127 place count 1808 transition count 7871
Iterating global reduction 0 with 127 rules applied. Total rules applied 254 place count 1808 transition count 7871
Ensure Unique test removed 968 transitions
Reduce isomorphic transitions removed 968 transitions.
Iterating post reduction 0 with 968 rules applied. Total rules applied 1222 place count 1808 transition count 6903
Applied a total of 1222 rules in 315 ms. Remains 1808 /1935 variables (removed 127) and now considering 6903/8977 (removed 2074) transitions.
[2023-03-14 07:44:25] [INFO ] Flow matrix only has 908 transitions (discarded 5995 similar events)
// Phase 1: matrix 908 rows 1808 cols
[2023-03-14 07:44:25] [INFO ] Computed 900 place invariants in 18 ms
[2023-03-14 07:44:28] [INFO ] Dead Transitions using invariants and state equation in 2933 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3249 ms. Remains : 1808/1935 places, 6903/8977 transitions.
[2023-03-14 07:44:28] [INFO ] Flatten gal took : 192 ms
[2023-03-14 07:44:28] [INFO ] Flatten gal took : 211 ms
[2023-03-14 07:44:29] [INFO ] Input system was already deterministic with 6903 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1935/1935 places, 8977/8977 transitions.
Discarding 131 places :
Symmetric choice reduction at 0 with 131 rule applications. Total rules 131 place count 1804 transition count 7842
Iterating global reduction 0 with 131 rules applied. Total rules applied 262 place count 1804 transition count 7842
Ensure Unique test removed 997 transitions
Reduce isomorphic transitions removed 997 transitions.
Iterating post reduction 0 with 997 rules applied. Total rules applied 1259 place count 1804 transition count 6845
Applied a total of 1259 rules in 333 ms. Remains 1804 /1935 variables (removed 131) and now considering 6845/8977 (removed 2132) transitions.
[2023-03-14 07:44:29] [INFO ] Flow matrix only has 904 transitions (discarded 5941 similar events)
// Phase 1: matrix 904 rows 1804 cols
[2023-03-14 07:44:29] [INFO ] Computed 900 place invariants in 22 ms
[2023-03-14 07:44:32] [INFO ] Dead Transitions using invariants and state equation in 2853 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3187 ms. Remains : 1804/1935 places, 6845/8977 transitions.
[2023-03-14 07:44:32] [INFO ] Flatten gal took : 186 ms
[2023-03-14 07:44:32] [INFO ] Flatten gal took : 206 ms
[2023-03-14 07:44:33] [INFO ] Input system was already deterministic with 6845 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1935/1935 places, 8977/8977 transitions.
Discarding 126 places :
Symmetric choice reduction at 0 with 126 rule applications. Total rules 126 place count 1809 transition count 7881
Iterating global reduction 0 with 126 rules applied. Total rules applied 252 place count 1809 transition count 7881
Ensure Unique test removed 966 transitions
Reduce isomorphic transitions removed 966 transitions.
Iterating post reduction 0 with 966 rules applied. Total rules applied 1218 place count 1809 transition count 6915
Applied a total of 1218 rules in 357 ms. Remains 1809 /1935 variables (removed 126) and now considering 6915/8977 (removed 2062) transitions.
[2023-03-14 07:44:33] [INFO ] Flow matrix only has 909 transitions (discarded 6006 similar events)
// Phase 1: matrix 909 rows 1809 cols
[2023-03-14 07:44:33] [INFO ] Computed 900 place invariants in 25 ms
[2023-03-14 07:44:36] [INFO ] Dead Transitions using invariants and state equation in 2897 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3256 ms. Remains : 1809/1935 places, 6915/8977 transitions.
[2023-03-14 07:44:36] [INFO ] Flatten gal took : 187 ms
[2023-03-14 07:44:36] [INFO ] Flatten gal took : 208 ms
[2023-03-14 07:44:37] [INFO ] Input system was already deterministic with 6915 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1935/1935 places, 8977/8977 transitions.
Discarding 128 places :
Symmetric choice reduction at 0 with 128 rule applications. Total rules 128 place count 1807 transition count 7869
Iterating global reduction 0 with 128 rules applied. Total rules applied 256 place count 1807 transition count 7869
Ensure Unique test removed 976 transitions
Reduce isomorphic transitions removed 976 transitions.
Iterating post reduction 0 with 976 rules applied. Total rules applied 1232 place count 1807 transition count 6893
Applied a total of 1232 rules in 322 ms. Remains 1807 /1935 variables (removed 128) and now considering 6893/8977 (removed 2084) transitions.
[2023-03-14 07:44:37] [INFO ] Flow matrix only has 907 transitions (discarded 5986 similar events)
// Phase 1: matrix 907 rows 1807 cols
[2023-03-14 07:44:37] [INFO ] Computed 900 place invariants in 19 ms
[2023-03-14 07:44:40] [INFO ] Dead Transitions using invariants and state equation in 2972 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3297 ms. Remains : 1807/1935 places, 6893/8977 transitions.
[2023-03-14 07:44:40] [INFO ] Flatten gal took : 188 ms
[2023-03-14 07:44:40] [INFO ] Flatten gal took : 204 ms
[2023-03-14 07:44:41] [INFO ] Input system was already deterministic with 6893 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1935/1935 places, 8977/8977 transitions.
Discarding 132 places :
Symmetric choice reduction at 0 with 132 rule applications. Total rules 132 place count 1803 transition count 7831
Iterating global reduction 0 with 132 rules applied. Total rules applied 264 place count 1803 transition count 7831
Ensure Unique test removed 1000 transitions
Reduce isomorphic transitions removed 1000 transitions.
Iterating post reduction 0 with 1000 rules applied. Total rules applied 1264 place count 1803 transition count 6831
Applied a total of 1264 rules in 335 ms. Remains 1803 /1935 variables (removed 132) and now considering 6831/8977 (removed 2146) transitions.
[2023-03-14 07:44:41] [INFO ] Flow matrix only has 903 transitions (discarded 5928 similar events)
// Phase 1: matrix 903 rows 1803 cols
[2023-03-14 07:44:41] [INFO ] Computed 900 place invariants in 24 ms
[2023-03-14 07:44:44] [INFO ] Dead Transitions using invariants and state equation in 2865 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3201 ms. Remains : 1803/1935 places, 6831/8977 transitions.
[2023-03-14 07:44:44] [INFO ] Flatten gal took : 175 ms
[2023-03-14 07:44:44] [INFO ] Flatten gal took : 198 ms
[2023-03-14 07:44:45] [INFO ] Input system was already deterministic with 6831 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1935/1935 places, 8977/8977 transitions.
Discarding 134 places :
Symmetric choice reduction at 0 with 134 rule applications. Total rules 134 place count 1801 transition count 7812
Iterating global reduction 0 with 134 rules applied. Total rules applied 268 place count 1801 transition count 7812
Ensure Unique test removed 1021 transitions
Reduce isomorphic transitions removed 1021 transitions.
Iterating post reduction 0 with 1021 rules applied. Total rules applied 1289 place count 1801 transition count 6791
Applied a total of 1289 rules in 346 ms. Remains 1801 /1935 variables (removed 134) and now considering 6791/8977 (removed 2186) transitions.
[2023-03-14 07:44:45] [INFO ] Flow matrix only has 901 transitions (discarded 5890 similar events)
// Phase 1: matrix 901 rows 1801 cols
[2023-03-14 07:44:45] [INFO ] Computed 900 place invariants in 29 ms
[2023-03-14 07:44:48] [INFO ] Dead Transitions using invariants and state equation in 2822 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3168 ms. Remains : 1801/1935 places, 6791/8977 transitions.
[2023-03-14 07:44:48] [INFO ] Flatten gal took : 176 ms
[2023-03-14 07:44:48] [INFO ] Flatten gal took : 201 ms
[2023-03-14 07:44:49] [INFO ] Input system was already deterministic with 6791 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1935/1935 places, 8977/8977 transitions.
Discarding 119 places :
Symmetric choice reduction at 0 with 119 rule applications. Total rules 119 place count 1816 transition count 7954
Iterating global reduction 0 with 119 rules applied. Total rules applied 238 place count 1816 transition count 7954
Ensure Unique test removed 915 transitions
Reduce isomorphic transitions removed 915 transitions.
Iterating post reduction 0 with 915 rules applied. Total rules applied 1153 place count 1816 transition count 7039
Applied a total of 1153 rules in 292 ms. Remains 1816 /1935 variables (removed 119) and now considering 7039/8977 (removed 1938) transitions.
[2023-03-14 07:44:49] [INFO ] Flow matrix only has 916 transitions (discarded 6123 similar events)
// Phase 1: matrix 916 rows 1816 cols
[2023-03-14 07:44:49] [INFO ] Computed 900 place invariants in 22 ms
[2023-03-14 07:44:52] [INFO ] Dead Transitions using invariants and state equation in 3130 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3422 ms. Remains : 1816/1935 places, 7039/8977 transitions.
[2023-03-14 07:44:52] [INFO ] Flatten gal took : 186 ms
[2023-03-14 07:44:52] [INFO ] Flatten gal took : 207 ms
[2023-03-14 07:44:53] [INFO ] Input system was already deterministic with 7039 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1935/1935 places, 8977/8977 transitions.
Discarding 129 places :
Symmetric choice reduction at 0 with 129 rule applications. Total rules 129 place count 1806 transition count 7861
Iterating global reduction 0 with 129 rules applied. Total rules applied 258 place count 1806 transition count 7861
Ensure Unique test removed 984 transitions
Reduce isomorphic transitions removed 984 transitions.
Iterating post reduction 0 with 984 rules applied. Total rules applied 1242 place count 1806 transition count 6877
Applied a total of 1242 rules in 389 ms. Remains 1806 /1935 variables (removed 129) and now considering 6877/8977 (removed 2100) transitions.
[2023-03-14 07:44:53] [INFO ] Flow matrix only has 906 transitions (discarded 5971 similar events)
// Phase 1: matrix 906 rows 1806 cols
[2023-03-14 07:44:53] [INFO ] Computed 900 place invariants in 26 ms
[2023-03-14 07:44:56] [INFO ] Dead Transitions using invariants and state equation in 2802 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3193 ms. Remains : 1806/1935 places, 6877/8977 transitions.
[2023-03-14 07:44:56] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-14 07:44:56] [INFO ] Flatten gal took : 174 ms
FORMULA PhaseVariation-PT-D30CS010-CTLFireability-07 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-14 07:44:56] [INFO ] Flatten gal took : 190 ms
[2023-03-14 07:44:57] [INFO ] Input system was already deterministic with 6877 transitions.
Support contains 0 out of 1806 places (down from 13) after GAL structural reductions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1935/1935 places, 8977/8977 transitions.
Discarding 128 places :
Symmetric choice reduction at 0 with 128 rule applications. Total rules 128 place count 1807 transition count 7868
Iterating global reduction 0 with 128 rules applied. Total rules applied 256 place count 1807 transition count 7868
Ensure Unique test removed 979 transitions
Reduce isomorphic transitions removed 979 transitions.
Iterating post reduction 0 with 979 rules applied. Total rules applied 1235 place count 1807 transition count 6889
Applied a total of 1235 rules in 3920 ms. Remains 1807 /1935 variables (removed 128) and now considering 6889/8977 (removed 2088) transitions.
[2023-03-14 07:45:01] [INFO ] Flow matrix only has 907 transitions (discarded 5982 similar events)
// Phase 1: matrix 907 rows 1807 cols
[2023-03-14 07:45:01] [INFO ] Computed 900 place invariants in 28 ms
[2023-03-14 07:45:04] [INFO ] Dead Transitions using invariants and state equation in 3048 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6969 ms. Remains : 1807/1935 places, 6889/8977 transitions.
[2023-03-14 07:45:04] [INFO ] Flatten gal took : 196 ms
[2023-03-14 07:45:04] [INFO ] Flatten gal took : 222 ms
[2023-03-14 07:45:05] [INFO ] Input system was already deterministic with 6889 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1935/1935 places, 8977/8977 transitions.
Discarding 130 places :
Symmetric choice reduction at 0 with 130 rule applications. Total rules 130 place count 1805 transition count 7853
Iterating global reduction 0 with 130 rules applied. Total rules applied 260 place count 1805 transition count 7853
Ensure Unique test removed 992 transitions
Reduce isomorphic transitions removed 992 transitions.
Iterating post reduction 0 with 992 rules applied. Total rules applied 1252 place count 1805 transition count 6861
Applied a total of 1252 rules in 3469 ms. Remains 1805 /1935 variables (removed 130) and now considering 6861/8977 (removed 2116) transitions.
[2023-03-14 07:45:08] [INFO ] Flow matrix only has 905 transitions (discarded 5956 similar events)
// Phase 1: matrix 905 rows 1805 cols
[2023-03-14 07:45:08] [INFO ] Computed 900 place invariants in 19 ms
[2023-03-14 07:45:11] [INFO ] Dead Transitions using invariants and state equation in 3026 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6496 ms. Remains : 1805/1935 places, 6861/8977 transitions.
[2023-03-14 07:45:11] [INFO ] Flatten gal took : 171 ms
[2023-03-14 07:45:12] [INFO ] Flatten gal took : 241 ms
[2023-03-14 07:45:12] [INFO ] Input system was already deterministic with 6861 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1935/1935 places, 8977/8977 transitions.
Discarding 121 places :
Symmetric choice reduction at 0 with 121 rule applications. Total rules 121 place count 1814 transition count 7921
Iterating global reduction 0 with 121 rules applied. Total rules applied 242 place count 1814 transition count 7921
Ensure Unique test removed 928 transitions
Reduce isomorphic transitions removed 928 transitions.
Iterating post reduction 0 with 928 rules applied. Total rules applied 1170 place count 1814 transition count 6993
Applied a total of 1170 rules in 3733 ms. Remains 1814 /1935 variables (removed 121) and now considering 6993/8977 (removed 1984) transitions.
[2023-03-14 07:45:16] [INFO ] Flow matrix only has 914 transitions (discarded 6079 similar events)
// Phase 1: matrix 914 rows 1814 cols
[2023-03-14 07:45:16] [INFO ] Computed 900 place invariants in 23 ms
[2023-03-14 07:45:18] [INFO ] Dead Transitions using invariants and state equation in 2826 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6559 ms. Remains : 1814/1935 places, 6993/8977 transitions.
[2023-03-14 07:45:19] [INFO ] Flatten gal took : 176 ms
[2023-03-14 07:45:19] [INFO ] Flatten gal took : 195 ms
[2023-03-14 07:45:19] [INFO ] Input system was already deterministic with 6993 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1935/1935 places, 8977/8977 transitions.
Discarding 134 places :
Symmetric choice reduction at 0 with 134 rule applications. Total rules 134 place count 1801 transition count 7814
Iterating global reduction 0 with 134 rules applied. Total rules applied 268 place count 1801 transition count 7814
Ensure Unique test removed 1017 transitions
Reduce isomorphic transitions removed 1017 transitions.
Iterating post reduction 0 with 1017 rules applied. Total rules applied 1285 place count 1801 transition count 6797
Applied a total of 1285 rules in 3361 ms. Remains 1801 /1935 variables (removed 134) and now considering 6797/8977 (removed 2180) transitions.
[2023-03-14 07:45:22] [INFO ] Flow matrix only has 901 transitions (discarded 5896 similar events)
// Phase 1: matrix 901 rows 1801 cols
[2023-03-14 07:45:22] [INFO ] Computed 900 place invariants in 24 ms
[2023-03-14 07:45:25] [INFO ] Dead Transitions using invariants and state equation in 2717 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6079 ms. Remains : 1801/1935 places, 6797/8977 transitions.
[2023-03-14 07:45:25] [INFO ] Flatten gal took : 171 ms
[2023-03-14 07:45:26] [INFO ] Flatten gal took : 189 ms
[2023-03-14 07:45:26] [INFO ] Input system was already deterministic with 6797 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1935/1935 places, 8977/8977 transitions.
Discarding 134 places :
Symmetric choice reduction at 0 with 134 rule applications. Total rules 134 place count 1801 transition count 7815
Iterating global reduction 0 with 134 rules applied. Total rules applied 268 place count 1801 transition count 7815
Ensure Unique test removed 1018 transitions
Reduce isomorphic transitions removed 1018 transitions.
Iterating post reduction 0 with 1018 rules applied. Total rules applied 1286 place count 1801 transition count 6797
Applied a total of 1286 rules in 340 ms. Remains 1801 /1935 variables (removed 134) and now considering 6797/8977 (removed 2180) transitions.
[2023-03-14 07:45:26] [INFO ] Flow matrix only has 901 transitions (discarded 5896 similar events)
// Phase 1: matrix 901 rows 1801 cols
[2023-03-14 07:45:26] [INFO ] Computed 900 place invariants in 23 ms
[2023-03-14 07:45:29] [INFO ] Dead Transitions using invariants and state equation in 2742 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3085 ms. Remains : 1801/1935 places, 6797/8977 transitions.
[2023-03-14 07:45:29] [INFO ] Flatten gal took : 170 ms
[2023-03-14 07:45:29] [INFO ] Flatten gal took : 187 ms
[2023-03-14 07:45:30] [INFO ] Input system was already deterministic with 6797 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1935/1935 places, 8977/8977 transitions.
Discarding 134 places :
Symmetric choice reduction at 0 with 134 rule applications. Total rules 134 place count 1801 transition count 7813
Iterating global reduction 0 with 134 rules applied. Total rules applied 268 place count 1801 transition count 7813
Ensure Unique test removed 1016 transitions
Reduce isomorphic transitions removed 1016 transitions.
Iterating post reduction 0 with 1016 rules applied. Total rules applied 1284 place count 1801 transition count 6797
Applied a total of 1284 rules in 3320 ms. Remains 1801 /1935 variables (removed 134) and now considering 6797/8977 (removed 2180) transitions.
[2023-03-14 07:45:33] [INFO ] Flow matrix only has 901 transitions (discarded 5896 similar events)
// Phase 1: matrix 901 rows 1801 cols
[2023-03-14 07:45:33] [INFO ] Computed 900 place invariants in 25 ms
[2023-03-14 07:45:36] [INFO ] Dead Transitions using invariants and state equation in 2787 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6110 ms. Remains : 1801/1935 places, 6797/8977 transitions.
[2023-03-14 07:45:36] [INFO ] Flatten gal took : 172 ms
[2023-03-14 07:45:36] [INFO ] Flatten gal took : 188 ms
[2023-03-14 07:45:37] [INFO ] Input system was already deterministic with 6797 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1935/1935 places, 8977/8977 transitions.
Discarding 120 places :
Symmetric choice reduction at 0 with 120 rule applications. Total rules 120 place count 1815 transition count 7929
Iterating global reduction 0 with 120 rules applied. Total rules applied 240 place count 1815 transition count 7929
Ensure Unique test removed 930 transitions
Reduce isomorphic transitions removed 930 transitions.
Iterating post reduction 0 with 930 rules applied. Total rules applied 1170 place count 1815 transition count 6999
Applied a total of 1170 rules in 289 ms. Remains 1815 /1935 variables (removed 120) and now considering 6999/8977 (removed 1978) transitions.
[2023-03-14 07:45:37] [INFO ] Flow matrix only has 915 transitions (discarded 6084 similar events)
// Phase 1: matrix 915 rows 1815 cols
[2023-03-14 07:45:37] [INFO ] Computed 900 place invariants in 24 ms
[2023-03-14 07:45:40] [INFO ] Dead Transitions using invariants and state equation in 2808 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3097 ms. Remains : 1815/1935 places, 6999/8977 transitions.
[2023-03-14 07:45:40] [INFO ] Flatten gal took : 173 ms
[2023-03-14 07:45:40] [INFO ] Flatten gal took : 194 ms
[2023-03-14 07:45:40] [INFO ] Input system was already deterministic with 6999 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1935/1935 places, 8977/8977 transitions.
Discarding 119 places :
Symmetric choice reduction at 0 with 119 rule applications. Total rules 119 place count 1816 transition count 7931
Iterating global reduction 0 with 119 rules applied. Total rules applied 238 place count 1816 transition count 7931
Ensure Unique test removed 924 transitions
Reduce isomorphic transitions removed 924 transitions.
Iterating post reduction 0 with 924 rules applied. Total rules applied 1162 place count 1816 transition count 7007
Applied a total of 1162 rules in 289 ms. Remains 1816 /1935 variables (removed 119) and now considering 7007/8977 (removed 1970) transitions.
[2023-03-14 07:45:41] [INFO ] Flow matrix only has 916 transitions (discarded 6091 similar events)
// Phase 1: matrix 916 rows 1816 cols
[2023-03-14 07:45:41] [INFO ] Computed 900 place invariants in 51 ms
[2023-03-14 07:45:43] [INFO ] Dead Transitions using invariants and state equation in 2821 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3114 ms. Remains : 1816/1935 places, 7007/8977 transitions.
[2023-03-14 07:45:44] [INFO ] Flatten gal took : 195 ms
[2023-03-14 07:45:44] [INFO ] Flatten gal took : 225 ms
[2023-03-14 07:45:44] [INFO ] Input system was already deterministic with 7007 transitions.
[2023-03-14 07:45:45] [INFO ] Flatten gal took : 241 ms
[2023-03-14 07:45:45] [INFO ] Flatten gal took : 247 ms
[2023-03-14 07:45:45] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 10 ms.
[2023-03-14 07:45:45] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 1935 places, 8977 transitions and 62815 arcs took 63 ms.
Total runtime 210691 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT PhaseVariation-PT-D30CS010
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA PhaseVariation-PT-D30CS010-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PhaseVariation-PT-D30CS010-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PhaseVariation-PT-D30CS010-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PhaseVariation-PT-D30CS010-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678780180957

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
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lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
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lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: Created skeleton in 1.000000 secs.
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lola: Rule S: 0 transitions removed,0 places removed
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PhaseVariation-PT-D30CS010-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
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PhaseVariation-PT-D30CS010-CTLFireability-12: EU 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-13: F 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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PhaseVariation-PT-D30CS010-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-11: AG 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-12: EU 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-13: F 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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PhaseVariation-PT-D30CS010-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
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PhaseVariation-PT-D30CS010-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-06: DISJ 0 0 0 0 4 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-11: AG 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-12: EU 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-13: F 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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PhaseVariation-PT-D30CS010-CTLFireability-12: EU 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-13: F 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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PhaseVariation-PT-D30CS010-CTLFireability-11: AG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-12: EU 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-13: F 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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PhaseVariation-PT-D30CS010-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
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PhaseVariation-PT-D30CS010-CTLFireability-11: AG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-12: EU 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-13: F 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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PhaseVariation-PT-D30CS010-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
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PhaseVariation-PT-D30CS010-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
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PhaseVariation-PT-D30CS010-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-11: AG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-12: EU 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-13: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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PhaseVariation-PT-D30CS010-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
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PhaseVariation-PT-D30CS010-CTLFireability-12: EU 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-13: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
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PhaseVariation-PT-D30CS010-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-06: DISJ 0 0 0 0 4 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-12: EU 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-13: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
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PhaseVariation-PT-D30CS010-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
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PhaseVariation-PT-D30CS010-CTLFireability-12: EU 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-13: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS010-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
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64 CTL EXCL 0/317 1/32 PhaseVariation-PT-D30CS010-CTLFireability-14 2566 m, 513 m/sec, 11169 t fired, .

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64 CTL EXCL 5/317 2/32 PhaseVariation-PT-D30CS010-CTLFireability-14 56206 m, 10728 m/sec, 691632 t fired, .

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64 CTL EXCL 10/317 3/32 PhaseVariation-PT-D30CS010-CTLFireability-14 104954 m, 9749 m/sec, 1388798 t fired, .

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/home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin//../BenchKit_head.sh: line 63: 612 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PhaseVariation-PT-D30CS010"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is PhaseVariation-PT-D30CS010, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r295-tall-167873947400066"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/PhaseVariation-PT-D30CS010.tgz
mv PhaseVariation-PT-D30CS010 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;