fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r294-tall-167873947200826
Last Updated
May 14, 2023

About the Execution of LoLA for QuasiCertifProtocol-COL-18

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
5499.439 462412.00 457482.00 1267.80 TF?TTT?FTTF??T?? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r294-tall-167873947200826.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is QuasiCertifProtocol-COL-18, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r294-tall-167873947200826
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 508K
-rw-r--r-- 1 mcc users 6.8K Feb 26 01:27 CTLCardinality.txt
-rw-r--r-- 1 mcc users 68K Feb 26 01:27 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.8K Feb 26 01:23 CTLFireability.txt
-rw-r--r-- 1 mcc users 63K Feb 26 01:23 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.8K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:37 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:37 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 16:37 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 16:37 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 26 01:32 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 109K Feb 26 01:32 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 5.9K Feb 26 01:28 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 41K Feb 26 01:28 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 16:37 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:37 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_pt
-rw-r--r-- 1 mcc users 3 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 93K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-00
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-01
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-02
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-03
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-04
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-05
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-06
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-07
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-08
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-09
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-10
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-11
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-12
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-13
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-14
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678981822953

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=QuasiCertifProtocol-COL-18
Not applying reductions.
Model is COL
CTLFireability PT
[2023-03-16 15:50:24] [INFO ] Running its-tools with arguments : [-pnfolder, ., -examination, CTLFireability, --reduce-single, STATESPACE]
[2023-03-16 15:50:24] [INFO ] Parsing pnml file : /home/mcc/execution/./model.pnml
[2023-03-16 15:50:24] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-16 15:50:24] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-16 15:50:25] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 663 ms
[2023-03-16 15:50:25] [INFO ] Imported 30 HL places and 26 HL transitions for a total of 1398 PT places and 296.0 transition bindings in 17 ms.
Parsed 16 properties from file ./CTLFireability.xml in 14 ms.
[2023-03-16 15:50:25] [INFO ] Unfolded HLPN to a Petri net with 1398 places and 296 transitions 3119 arcs in 29 ms.
[2023-03-16 15:50:25] [INFO ] Unfolded 16 HLPN properties in 1 ms.
[2023-03-16 15:50:25] [INFO ] Export to MCC of 16 properties in file ./CTLFireability.STATESPACE.xml took 28 ms.
[2023-03-16 15:50:25] [INFO ] Export to PNML in file ./model.STATESPACE.pnml of net with 1398 places, 296 transitions and 3119 arcs took 7 ms.
Total runtime 886 ms.
starting LoLA
BK_INPUT QuasiCertifProtocol-COL-18
BK_EXAMINATION: CTLCardinality
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution/unfCTLFireability

FORMULA QuasiCertifProtocol-COL-18-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-COL-18-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-COL-18-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-COL-18-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-COL-18-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-COL-18-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-COL-18-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-COL-18-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-COL-18-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-COL-18-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678982285365

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/unfCTLFireability/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/unfCTLFireability/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/unfCTLFireability/CTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 70 (type SKEL/FNDP) for 19 QuasiCertifProtocol-COL-18-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 71 (type SKEL/EQUN) for 19 QuasiCertifProtocol-COL-18-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 72 (type SKEL/SRCH) for 19 QuasiCertifProtocol-COL-18-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 73 (type SKEL/SRCH) for 19 QuasiCertifProtocol-COL-18-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 72 (type SKEL/SRCH) for QuasiCertifProtocol-COL-18-CTLFireability-01
lola: result : true
lola: markings : 22
lola: fired transitions : 21
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 70 (type FNDP) for QuasiCertifProtocol-COL-18-CTLFireability-01 (obsolete)
lola: CANCELED task # 71 (type EQUN) for QuasiCertifProtocol-COL-18-CTLFireability-01 (obsolete)
lola: CANCELED task # 73 (type SRCH) for QuasiCertifProtocol-COL-18-CTLFireability-01 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 70 (type SKEL/FNDP) for QuasiCertifProtocol-COL-18-CTLFireability-01
lola: result : true
lola: fired transitions : 20
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
sara: try reading problem file /home/mcc/execution/unfCTLFireability/CTLCardinality-71.sara.

lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 71 (type SKEL/EQUN) for QuasiCertifProtocol-COL-18-CTLFireability-01
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 77 (type EXCL) for 19 QuasiCertifProtocol-COL-18-CTLFireability-01
lola: time limit : 137 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 75 (type FNDP) for 19 QuasiCertifProtocol-COL-18-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 76 (type EQUN) for 19 QuasiCertifProtocol-COL-18-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 80 (type SRCH) for 19 QuasiCertifProtocol-COL-18-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 80 (type SRCH) for QuasiCertifProtocol-COL-18-CTLFireability-01
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 77 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-01
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 75 (type FNDP) for QuasiCertifProtocol-COL-18-CTLFireability-01 (obsolete)
lola: CANCELED task # 76 (type EQUN) for QuasiCertifProtocol-COL-18-CTLFireability-01 (obsolete)
lola: FINISHED task # 75 (type FNDP) for QuasiCertifProtocol-COL-18-CTLFireability-01
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: LAUNCH task # 36 (type EXCL) for 35 QuasiCertifProtocol-COL-18-CTLFireability-05
lola: time limit : 148 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 79 (type FNDP) for 0 QuasiCertifProtocol-COL-18-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 81 (type EQUN) for 0 QuasiCertifProtocol-COL-18-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 83 (type SRCH) for 0 QuasiCertifProtocol-COL-18-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 79 (type FNDP) for QuasiCertifProtocol-COL-18-CTLFireability-00
lola: result : true
lola: fired transitions : 19
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 81 (type EQUN) for QuasiCertifProtocol-COL-18-CTLFireability-00 (obsolete)
lola: CANCELED task # 83 (type SRCH) for QuasiCertifProtocol-COL-18-CTLFireability-00 (obsolete)
lola: FINISHED task # 83 (type SRCH) for QuasiCertifProtocol-COL-18-CTLFireability-00
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 36 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-05
lola: result : true
lola: markings : 2482
lola: fired transitions : 2707
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 27 (type EXCL) for 26 QuasiCertifProtocol-COL-18-CTLFireability-02
lola: time limit : 178 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
sara: try reading problem file /home/mcc/execution/unfCTLFireability/CTLCardinality-76.sara.

lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 76 (type EQUN) for QuasiCertifProtocol-COL-18-CTLFireability-01
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
sara: try reading problem file /home/mcc/execution/unfCTLFireability/CTLCardinality-81.sara.
sara: place or transition ordering is non-deterministic

lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 81 (type EQUN) for QuasiCertifProtocol-COL-18-CTLFireability-00
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 4/222 2/32 QuasiCertifProtocol-COL-18-CTLFireability-02 286783 m, 57356 m/sec, 2117685 t fired, .

Time elapsed: 38 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 9/222 4/32 QuasiCertifProtocol-COL-18-CTLFireability-02 582461 m, 59135 m/sec, 4601866 t fired, .

Time elapsed: 43 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 14/222 6/32 QuasiCertifProtocol-COL-18-CTLFireability-02 874792 m, 58466 m/sec, 7077289 t fired, .

Time elapsed: 48 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 19/222 8/32 QuasiCertifProtocol-COL-18-CTLFireability-02 1157685 m, 56578 m/sec, 9528758 t fired, .

Time elapsed: 53 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 24/222 10/32 QuasiCertifProtocol-COL-18-CTLFireability-02 1423443 m, 53151 m/sec, 12002120 t fired, .

Time elapsed: 58 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 29/222 12/32 QuasiCertifProtocol-COL-18-CTLFireability-02 1684043 m, 52120 m/sec, 14465340 t fired, .

Time elapsed: 63 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 34/222 14/32 QuasiCertifProtocol-COL-18-CTLFireability-02 1970227 m, 57236 m/sec, 16917846 t fired, .

Time elapsed: 68 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 39/222 15/32 QuasiCertifProtocol-COL-18-CTLFireability-02 2254050 m, 56764 m/sec, 19383616 t fired, .

Time elapsed: 73 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 44/222 17/32 QuasiCertifProtocol-COL-18-CTLFireability-02 2514672 m, 52124 m/sec, 21853694 t fired, .

Time elapsed: 78 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 49/222 19/32 QuasiCertifProtocol-COL-18-CTLFireability-02 2775340 m, 52133 m/sec, 24320611 t fired, .

Time elapsed: 83 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 54/222 21/32 QuasiCertifProtocol-COL-18-CTLFireability-02 3046313 m, 54194 m/sec, 26789348 t fired, .

Time elapsed: 88 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 59/222 22/32 QuasiCertifProtocol-COL-18-CTLFireability-02 3301235 m, 50984 m/sec, 29257866 t fired, .

Time elapsed: 93 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 64/222 24/32 QuasiCertifProtocol-COL-18-CTLFireability-02 3560288 m, 51810 m/sec, 31726554 t fired, .

Time elapsed: 98 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 69/222 26/32 QuasiCertifProtocol-COL-18-CTLFireability-02 3807498 m, 49442 m/sec, 34189201 t fired, .

Time elapsed: 103 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 74/222 27/32 QuasiCertifProtocol-COL-18-CTLFireability-02 4057818 m, 50064 m/sec, 36656965 t fired, .

Time elapsed: 108 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 79/222 29/32 QuasiCertifProtocol-COL-18-CTLFireability-02 4296518 m, 47740 m/sec, 39119426 t fired, .

Time elapsed: 113 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 84/222 30/32 QuasiCertifProtocol-COL-18-CTLFireability-02 4524363 m, 45569 m/sec, 41579705 t fired, .

Time elapsed: 118 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 89/222 32/32 QuasiCertifProtocol-COL-18-CTLFireability-02 4737829 m, 42693 m/sec, 44035604 t fired, .

Time elapsed: 123 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 27 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 128 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 66 (type EXCL) for 65 QuasiCertifProtocol-COL-18-CTLFireability-15
lola: time limit : 231 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 CTL EXCL 5/231 5/32 QuasiCertifProtocol-COL-18-CTLFireability-15 648616 m, 129723 m/sec, 2263517 t fired, .

Time elapsed: 133 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 CTL EXCL 10/231 8/32 QuasiCertifProtocol-COL-18-CTLFireability-15 1163996 m, 103076 m/sec, 4584684 t fired, .

Time elapsed: 138 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 CTL EXCL 15/231 11/32 QuasiCertifProtocol-COL-18-CTLFireability-15 1558315 m, 78863 m/sec, 6929624 t fired, .

Time elapsed: 143 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 CTL EXCL 20/231 13/32 QuasiCertifProtocol-COL-18-CTLFireability-15 1874172 m, 63171 m/sec, 9347820 t fired, .

Time elapsed: 148 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 CTL EXCL 25/231 14/32 QuasiCertifProtocol-COL-18-CTLFireability-15 2158496 m, 56864 m/sec, 11757146 t fired, .

Time elapsed: 153 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 CTL EXCL 30/231 16/32 QuasiCertifProtocol-COL-18-CTLFireability-15 2426947 m, 53690 m/sec, 14164073 t fired, .

Time elapsed: 158 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 CTL EXCL 35/231 18/32 QuasiCertifProtocol-COL-18-CTLFireability-15 2729079 m, 60426 m/sec, 16538162 t fired, .

Time elapsed: 163 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 CTL EXCL 40/231 21/32 QuasiCertifProtocol-COL-18-CTLFireability-15 3310112 m, 116206 m/sec, 18758357 t fired, .

Time elapsed: 168 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 CTL EXCL 45/231 25/32 QuasiCertifProtocol-COL-18-CTLFireability-15 3871938 m, 112365 m/sec, 20969329 t fired, .

Time elapsed: 173 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 CTL EXCL 50/231 27/32 QuasiCertifProtocol-COL-18-CTLFireability-15 4360726 m, 97757 m/sec, 23175137 t fired, .

Time elapsed: 178 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 CTL EXCL 55/231 30/32 QuasiCertifProtocol-COL-18-CTLFireability-15 4774145 m, 82683 m/sec, 25527858 t fired, .

Time elapsed: 183 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 CTL EXCL 60/231 32/32 QuasiCertifProtocol-COL-18-CTLFireability-15 5112842 m, 67739 m/sec, 27919829 t fired, .

Time elapsed: 188 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 66 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 193 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 63 (type EXCL) for 62 QuasiCertifProtocol-COL-18-CTLFireability-14
lola: time limit : 243 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 5/243 3/32 QuasiCertifProtocol-COL-18-CTLFireability-14 324007 m, 64801 m/sec, 2581879 t fired, .

Time elapsed: 198 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 10/243 5/32 QuasiCertifProtocol-COL-18-CTLFireability-14 614196 m, 58037 m/sec, 5112566 t fired, .

Time elapsed: 203 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 15/243 7/32 QuasiCertifProtocol-COL-18-CTLFireability-14 907561 m, 58673 m/sec, 7611998 t fired, .

Time elapsed: 208 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 20/243 8/32 QuasiCertifProtocol-COL-18-CTLFireability-14 1181980 m, 54883 m/sec, 10066220 t fired, .

Time elapsed: 213 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 25/243 10/32 QuasiCertifProtocol-COL-18-CTLFireability-14 1463606 m, 56325 m/sec, 12554576 t fired, .

Time elapsed: 218 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 30/243 12/32 QuasiCertifProtocol-COL-18-CTLFireability-14 1736015 m, 54481 m/sec, 15018950 t fired, .

Time elapsed: 223 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 35/243 14/32 QuasiCertifProtocol-COL-18-CTLFireability-14 1995247 m, 51846 m/sec, 17413948 t fired, .

Time elapsed: 228 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 40/243 15/32 QuasiCertifProtocol-COL-18-CTLFireability-14 2244775 m, 49905 m/sec, 19768620 t fired, .

Time elapsed: 233 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 45/243 17/32 QuasiCertifProtocol-COL-18-CTLFireability-14 2472694 m, 45583 m/sec, 22079653 t fired, .

Time elapsed: 238 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 50/243 18/32 QuasiCertifProtocol-COL-18-CTLFireability-14 2758976 m, 57256 m/sec, 24537562 t fired, .

Time elapsed: 243 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 55/243 20/32 QuasiCertifProtocol-COL-18-CTLFireability-14 3026065 m, 53417 m/sec, 26942061 t fired, .

Time elapsed: 248 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 60/243 22/32 QuasiCertifProtocol-COL-18-CTLFireability-14 3281701 m, 51127 m/sec, 29320419 t fired, .

Time elapsed: 253 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 65/243 23/32 QuasiCertifProtocol-COL-18-CTLFireability-14 3528296 m, 49319 m/sec, 31634269 t fired, .

Time elapsed: 258 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 70/243 24/32 QuasiCertifProtocol-COL-18-CTLFireability-14 3756464 m, 45633 m/sec, 33933532 t fired, .

Time elapsed: 263 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 75/243 26/32 QuasiCertifProtocol-COL-18-CTLFireability-14 4010457 m, 50798 m/sec, 36274202 t fired, .

Time elapsed: 268 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 80/243 27/32 QuasiCertifProtocol-COL-18-CTLFireability-14 4251951 m, 48298 m/sec, 38574826 t fired, .

Time elapsed: 273 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 85/243 29/32 QuasiCertifProtocol-COL-18-CTLFireability-14 4481120 m, 45833 m/sec, 40828568 t fired, .

Time elapsed: 278 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 90/243 30/32 QuasiCertifProtocol-COL-18-CTLFireability-14 4703037 m, 44383 m/sec, 43062558 t fired, .

Time elapsed: 283 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 95/243 31/32 QuasiCertifProtocol-COL-18-CTLFireability-14 4916517 m, 42696 m/sec, 45262110 t fired, .

Time elapsed: 288 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 63 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 293 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 54 (type EXCL) for 53 QuasiCertifProtocol-COL-18-CTLFireability-11
lola: time limit : 254 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 5/254 2/32 QuasiCertifProtocol-COL-18-CTLFireability-11 239994 m, 47998 m/sec, 2568864 t fired, .

Time elapsed: 298 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 11/254 5/32 QuasiCertifProtocol-COL-18-CTLFireability-11 500654 m, 52132 m/sec, 5088799 t fired, .

Time elapsed: 304 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 16/254 7/32 QuasiCertifProtocol-COL-18-CTLFireability-11 804632 m, 60795 m/sec, 7523230 t fired, .

Time elapsed: 309 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 21/254 9/32 QuasiCertifProtocol-COL-18-CTLFireability-11 1082912 m, 55656 m/sec, 9965922 t fired, .

Time elapsed: 314 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 26/254 10/32 QuasiCertifProtocol-COL-18-CTLFireability-11 1313271 m, 46071 m/sec, 12491058 t fired, .

Time elapsed: 319 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 31/254 12/32 QuasiCertifProtocol-COL-18-CTLFireability-11 1519848 m, 41315 m/sec, 15031232 t fired, .

Time elapsed: 324 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 36/254 13/32 QuasiCertifProtocol-COL-18-CTLFireability-11 1710470 m, 38124 m/sec, 17593259 t fired, .

Time elapsed: 329 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 41/254 15/32 QuasiCertifProtocol-COL-18-CTLFireability-11 1921059 m, 42117 m/sec, 20090584 t fired, .

Time elapsed: 334 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 46/254 16/32 QuasiCertifProtocol-COL-18-CTLFireability-11 2041652 m, 24118 m/sec, 22201611 t fired, .

Time elapsed: 339 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 51/254 17/32 QuasiCertifProtocol-COL-18-CTLFireability-11 2168900 m, 25449 m/sec, 24351977 t fired, .

Time elapsed: 344 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 56/254 21/32 QuasiCertifProtocol-COL-18-CTLFireability-11 2713006 m, 108821 m/sec, 26481649 t fired, .

Time elapsed: 349 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 61/254 28/32 QuasiCertifProtocol-COL-18-CTLFireability-11 3650601 m, 187519 m/sec, 28151339 t fired, .

Time elapsed: 354 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 54 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 359 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 48 (type EXCL) for 47 QuasiCertifProtocol-COL-18-CTLFireability-09
lola: time limit : 270 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 5/270 4/32 QuasiCertifProtocol-COL-18-CTLFireability-09 560715 m, 112143 m/sec, 2476341 t fired, .

Time elapsed: 364 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 48 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-09
lola: result : true
lola: markings : 709629
lola: fired transitions : 3308056
lola: time used : 6.000000
lola: memory pages used : 5
lola: LAUNCH task # 45 (type EXCL) for 44 QuasiCertifProtocol-COL-18-CTLFireability-08
lola: time limit : 294 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 4/294 3/32 QuasiCertifProtocol-COL-18-CTLFireability-08 330741 m, 66148 m/sec, 1401295 t fired, .

Time elapsed: 369 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 45 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-08
lola: result : true
lola: markings : 709228
lola: fired transitions : 3306968
lola: time used : 8.000000
lola: memory pages used : 5
lola: LAUNCH task # 42 (type EXCL) for 41 QuasiCertifProtocol-COL-18-CTLFireability-07
lola: time limit : 322 sec
lola: memory limit: 32 pages
lola: FINISHED task # 42 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-07
lola: result : false
lola: markings : 3997
lola: fired transitions : 5712
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 39 (type EXCL) for 38 QuasiCertifProtocol-COL-18-CTLFireability-06
lola: time limit : 358 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL false CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 1/358 1/32 QuasiCertifProtocol-COL-18-CTLFireability-06 79954 m, 15990 m/sec, 267286 t fired, .

Time elapsed: 374 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL false CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 6/358 5/32 QuasiCertifProtocol-COL-18-CTLFireability-06 675242 m, 119057 m/sec, 2587290 t fired, .

Time elapsed: 379 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL false CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 11/358 9/32 QuasiCertifProtocol-COL-18-CTLFireability-06 1236574 m, 112266 m/sec, 4876073 t fired, .

Time elapsed: 384 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL false CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 16/358 12/32 QuasiCertifProtocol-COL-18-CTLFireability-06 1771543 m, 106993 m/sec, 7150189 t fired, .

Time elapsed: 389 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL false CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 21/358 15/32 QuasiCertifProtocol-COL-18-CTLFireability-06 2271188 m, 99929 m/sec, 9401898 t fired, .

Time elapsed: 394 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL false CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 26/358 19/32 QuasiCertifProtocol-COL-18-CTLFireability-06 2851835 m, 116129 m/sec, 11694480 t fired, .

Time elapsed: 399 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL false CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 31/358 22/32 QuasiCertifProtocol-COL-18-CTLFireability-06 3379860 m, 105605 m/sec, 13966547 t fired, .

Time elapsed: 404 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL false CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 36/358 25/32 QuasiCertifProtocol-COL-18-CTLFireability-06 3814288 m, 86885 m/sec, 16176546 t fired, .

Time elapsed: 409 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL false CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 41/358 27/32 QuasiCertifProtocol-COL-18-CTLFireability-06 4228047 m, 82751 m/sec, 18375361 t fired, .

Time elapsed: 414 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL false CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 46/358 29/32 QuasiCertifProtocol-COL-18-CTLFireability-06 4591191 m, 72628 m/sec, 20591819 t fired, .

Time elapsed: 419 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL false CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 51/358 30/32 QuasiCertifProtocol-COL-18-CTLFireability-06 4871429 m, 56047 m/sec, 22850730 t fired, .

Time elapsed: 424 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL false CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 56/358 32/32 QuasiCertifProtocol-COL-18-CTLFireability-06 5144914 m, 54697 m/sec, 25103600 t fired, .

Time elapsed: 429 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 39 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL false CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ 0 2 0 0 8 0 0 6
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ 0 1 0 0 8 0 0 1
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-13: EG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 434 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 33 (type EXCL) for 32 QuasiCertifProtocol-COL-18-CTLFireability-04
lola: time limit : 395 sec
lola: memory limit: 32 pages
lola: FINISHED task # 33 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-04
lola: result : true
lola: markings : 33
lola: fired transitions : 141
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 30 (type EXCL) for 29 QuasiCertifProtocol-COL-18-CTLFireability-03
lola: time limit : 452 sec
lola: memory limit: 32 pages
lola: FINISHED task # 30 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-03
lola: result : true
lola: markings : 53
lola: fired transitions : 106
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 24 (type EXCL) for 19 QuasiCertifProtocol-COL-18-CTLFireability-01
lola: time limit : 527 sec
lola: memory limit: 32 pages
lola: FINISHED task # 24 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-01
lola: result : false
lola: markings : 20
lola: fired transitions : 19
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 17 (type EXCL) for 0 QuasiCertifProtocol-COL-18-CTLFireability-00
lola: time limit : 633 sec
lola: memory limit: 32 pages
lola: FINISHED task # 17 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-00
lola: result : true
lola: markings : 341
lola: fired transitions : 620
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 60 (type EXCL) for 59 QuasiCertifProtocol-COL-18-CTLFireability-13
lola: time limit : 1055 sec
lola: memory limit: 32 pages
lola: FINISHED task # 60 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-13
lola: result : true
lola: markings : 32
lola: fired transitions : 31
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 51 (type EXCL) for 50 QuasiCertifProtocol-COL-18-CTLFireability-10
lola: time limit : 1583 sec
lola: memory limit: 32 pages
lola: FINISHED task # 51 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-10
lola: result : false
lola: markings : 105
lola: fired transitions : 168
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 57 (type EXCL) for 56 QuasiCertifProtocol-COL-18-CTLFireability-12
lola: time limit : 3166 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ false DISJ
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL false CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL false CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-13: EG true state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 CTL EXCL 5/3166 4/32 QuasiCertifProtocol-COL-18-CTLFireability-12 475520 m, 95104 m/sec, 2294015 t fired, .

Time elapsed: 439 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ false DISJ
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL false CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL false CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-13: EG true state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 CTL EXCL 10/3166 12/32 QuasiCertifProtocol-COL-18-CTLFireability-12 1596563 m, 224208 m/sec, 4358101 t fired, .

Time elapsed: 444 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ false DISJ
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL false CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL false CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-13: EG true state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 CTL EXCL 15/3166 21/32 QuasiCertifProtocol-COL-18-CTLFireability-12 2828168 m, 246321 m/sec, 6333754 t fired, .

Time elapsed: 449 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ false DISJ
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL false CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL false CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-13: EG true state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 CTL EXCL 20/3166 30/32 QuasiCertifProtocol-COL-18-CTLFireability-12 4021580 m, 238682 m/sec, 8296775 t fired, .

Time elapsed: 454 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 57 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ false DISJ
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL false CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL false CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-13: EG true state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 459 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-COL-18-CTLFireability-00: DISJ true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-01: DISJ false DISJ
QuasiCertifProtocol-COL-18-CTLFireability-02: CTL unknown AGGR
QuasiCertifProtocol-COL-18-CTLFireability-03: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-04: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-06: CTL unknown AGGR
QuasiCertifProtocol-COL-18-CTLFireability-07: CTL false CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-08: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-09: CTL true CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-10: CTL false CTL model checker
QuasiCertifProtocol-COL-18-CTLFireability-11: CTL unknown AGGR
QuasiCertifProtocol-COL-18-CTLFireability-12: CTL unknown AGGR
QuasiCertifProtocol-COL-18-CTLFireability-13: EG true state space / EG
QuasiCertifProtocol-COL-18-CTLFireability-14: CTL unknown AGGR
QuasiCertifProtocol-COL-18-CTLFireability-15: CTL unknown AGGR


Time elapsed: 459 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="QuasiCertifProtocol-COL-18"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is QuasiCertifProtocol-COL-18, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r294-tall-167873947200826"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/QuasiCertifProtocol-COL-18.tgz
mv QuasiCertifProtocol-COL-18 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;