Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r263-smll-167863538300506.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is PermAdmissibility-PT-01, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r263-smll-167863538300506
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.8M
-rw-r--r-- 1 mcc users 8.7K Feb 26 01:21 CTLCardinality.txt
-rw-r--r-- 1 mcc users 81K Feb 26 01:21 CTLCardinality.xml
-rw-r--r-- 1 mcc users 30K Feb 26 01:19 CTLFireability.txt
-rw-r--r-- 1 mcc users 150K Feb 26 01:19 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 5.0K Feb 25 16:30 LTLCardinality.txt
-rw-r--r-- 1 mcc users 31K Feb 25 16:30 LTLCardinality.xml
-rw-r--r-- 1 mcc users 19K Feb 25 16:30 LTLFireability.txt
-rw-r--r-- 1 mcc users 79K Feb 25 16:30 LTLFireability.xml
-rw-r--r-- 1 mcc users 16K Feb 26 01:29 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 130K Feb 26 01:29 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 110K Feb 26 01:28 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 550K Feb 26 01:28 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 25 16:30 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.4K Feb 25 16:30 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 484K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-00
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-01
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-02
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-03
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-04
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-05
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-06
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-07
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-08
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-09
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-10
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-11
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-12
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-13
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-14
FORMULA_NAME PermAdmissibility-PT-01-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678805808805

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=PermAdmissibility-PT-01
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-14 14:56:52] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-14 14:56:52] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-14 14:56:52] [INFO ] Load time of PNML (sax parser for PT used): 220 ms
[2023-03-14 14:56:52] [INFO ] Transformed 168 places.
[2023-03-14 14:56:52] [INFO ] Transformed 592 transitions.
[2023-03-14 14:56:52] [INFO ] Parsed PT model containing 168 places and 592 transitions and 3456 arcs in 391 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 38 ms.
Support contains 104 out of 168 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 168/168 places, 592/592 transitions.
Reduce places removed 64 places and 0 transitions.
Iterating post reduction 0 with 64 rules applied. Total rules applied 64 place count 104 transition count 592
Applied a total of 64 rules in 45 ms. Remains 104 /168 variables (removed 64) and now considering 592/592 (removed 0) transitions.
// Phase 1: matrix 592 rows 104 cols
[2023-03-14 14:56:53] [INFO ] Computed 16 place invariants in 56 ms
[2023-03-14 14:56:53] [INFO ] Implicit Places using invariants in 386 ms returned []
[2023-03-14 14:56:53] [INFO ] Invariant cache hit.
[2023-03-14 14:56:54] [INFO ] Implicit Places using invariants and state equation in 457 ms returned []
Implicit Place search using SMT with State Equation took 904 ms to find 0 implicit places.
[2023-03-14 14:56:54] [INFO ] Invariant cache hit.
[2023-03-14 14:56:54] [INFO ] Dead Transitions using invariants and state equation in 678 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 104/168 places, 592/592 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1633 ms. Remains : 104/168 places, 592/592 transitions.
Support contains 104 out of 104 places after structural reductions.
[2023-03-14 14:56:55] [INFO ] Flatten gal took : 225 ms
[2023-03-14 14:56:55] [INFO ] Flatten gal took : 120 ms
[2023-03-14 14:56:56] [INFO ] Input system was already deterministic with 592 transitions.
Incomplete random walk after 10000 steps, including 588 resets, run finished after 918 ms. (steps per millisecond=10 ) properties (out of 56) seen :45
Incomplete Best-First random walk after 10001 steps, including 204 resets, run finished after 341 ms. (steps per millisecond=29 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 204 resets, run finished after 306 ms. (steps per millisecond=32 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 204 resets, run finished after 348 ms. (steps per millisecond=28 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 204 resets, run finished after 183 ms. (steps per millisecond=54 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 204 resets, run finished after 151 ms. (steps per millisecond=66 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 204 resets, run finished after 165 ms. (steps per millisecond=60 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 204 resets, run finished after 169 ms. (steps per millisecond=59 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 204 resets, run finished after 240 ms. (steps per millisecond=41 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 204 resets, run finished after 243 ms. (steps per millisecond=41 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 204 resets, run finished after 212 ms. (steps per millisecond=47 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 204 resets, run finished after 204 ms. (steps per millisecond=49 ) properties (out of 11) seen :0
Running SMT prover for 11 properties.
[2023-03-14 14:56:59] [INFO ] Invariant cache hit.
[2023-03-14 14:57:00] [INFO ] [Real]Absence check using 0 positive and 16 generalized place invariants in 8 ms returned sat
[2023-03-14 14:57:00] [INFO ] After 175ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:11
[2023-03-14 14:57:00] [INFO ] [Nat]Absence check using 0 positive and 16 generalized place invariants in 14 ms returned sat
[2023-03-14 14:57:03] [INFO ] After 2956ms SMT Verify possible using all constraints in natural domain returned unsat :11 sat :0
Fused 11 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 11 atomic propositions for a total of 16 simplifications.
[2023-03-14 14:57:03] [INFO ] Flatten gal took : 59 ms
[2023-03-14 14:57:03] [INFO ] Initial state reduction rules for CTL removed 2 formulas.
FORMULA PermAdmissibility-PT-01-CTLFireability-10 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA PermAdmissibility-PT-01-CTLFireability-03 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-14 14:57:03] [INFO ] Flatten gal took : 93 ms
[2023-03-14 14:57:04] [INFO ] Input system was already deterministic with 592 transitions.
FORMULA PermAdmissibility-PT-01-CTLFireability-07 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Computed a total of 104 stabilizing places and 592 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 104 transition count 592
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 91 transition count 468
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 91 transition count 468
Applied a total of 26 rules in 20 ms. Remains 91 /104 variables (removed 13) and now considering 468/592 (removed 124) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 21 ms. Remains : 91/104 places, 468/592 transitions.
[2023-03-14 14:57:04] [INFO ] Flatten gal took : 53 ms
[2023-03-14 14:57:04] [INFO ] Flatten gal took : 50 ms
[2023-03-14 14:57:04] [INFO ] Input system was already deterministic with 468 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Graph (complete) has 975 edges and 104 vertex of which 86 are kept as prefixes of interest. Removing 18 places using SCC suffix rule.7 ms
Discarding 18 places :
Also discarding 128 output transitions
Drop transitions removed 128 transitions
Applied a total of 1 rules in 42 ms. Remains 86 /104 variables (removed 18) and now considering 464/592 (removed 128) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 44 ms. Remains : 86/104 places, 464/592 transitions.
[2023-03-14 14:57:04] [INFO ] Flatten gal took : 27 ms
[2023-03-14 14:57:04] [INFO ] Flatten gal took : 31 ms
[2023-03-14 14:57:04] [INFO ] Input system was already deterministic with 464 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 26 places :
Symmetric choice reduction at 0 with 26 rule applications. Total rules 26 place count 78 transition count 344
Iterating global reduction 0 with 26 rules applied. Total rules applied 52 place count 78 transition count 344
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 76 place count 54 transition count 108
Iterating global reduction 0 with 24 rules applied. Total rules applied 100 place count 54 transition count 108
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 103 place count 51 transition count 84
Iterating global reduction 0 with 3 rules applied. Total rules applied 106 place count 51 transition count 84
Applied a total of 106 rules in 20 ms. Remains 51 /104 variables (removed 53) and now considering 84/592 (removed 508) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 22 ms. Remains : 51/104 places, 84/592 transitions.
[2023-03-14 14:57:04] [INFO ] Flatten gal took : 5 ms
[2023-03-14 14:57:04] [INFO ] Flatten gal took : 6 ms
[2023-03-14 14:57:04] [INFO ] Input system was already deterministic with 84 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 91 transition count 468
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 91 transition count 468
Applied a total of 26 rules in 17 ms. Remains 91 /104 variables (removed 13) and now considering 468/592 (removed 124) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 17 ms. Remains : 91/104 places, 468/592 transitions.
[2023-03-14 14:57:04] [INFO ] Flatten gal took : 23 ms
[2023-03-14 14:57:04] [INFO ] Flatten gal took : 26 ms
[2023-03-14 14:57:04] [INFO ] Input system was already deterministic with 468 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 91 transition count 468
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 91 transition count 468
Applied a total of 26 rules in 8 ms. Remains 91 /104 variables (removed 13) and now considering 468/592 (removed 124) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 91/104 places, 468/592 transitions.
[2023-03-14 14:57:04] [INFO ] Flatten gal took : 24 ms
[2023-03-14 14:57:04] [INFO ] Flatten gal took : 27 ms
[2023-03-14 14:57:04] [INFO ] Input system was already deterministic with 468 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 91 transition count 468
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 91 transition count 468
Applied a total of 26 rules in 7 ms. Remains 91 /104 variables (removed 13) and now considering 468/592 (removed 124) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 91/104 places, 468/592 transitions.
[2023-03-14 14:57:05] [INFO ] Flatten gal took : 19 ms
[2023-03-14 14:57:05] [INFO ] Flatten gal took : 22 ms
[2023-03-14 14:57:05] [INFO ] Input system was already deterministic with 468 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 18 places :
Symmetric choice reduction at 0 with 18 rule applications. Total rules 18 place count 86 transition count 384
Iterating global reduction 0 with 18 rules applied. Total rules applied 36 place count 86 transition count 384
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 48 place count 74 transition count 232
Iterating global reduction 0 with 12 rules applied. Total rules applied 60 place count 74 transition count 232
Applied a total of 60 rules in 7 ms. Remains 74 /104 variables (removed 30) and now considering 232/592 (removed 360) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 74/104 places, 232/592 transitions.
[2023-03-14 14:57:05] [INFO ] Flatten gal took : 10 ms
[2023-03-14 14:57:05] [INFO ] Flatten gal took : 10 ms
[2023-03-14 14:57:05] [INFO ] Input system was already deterministic with 232 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 80 transition count 352
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 80 transition count 352
Discarding 18 places :
Symmetric choice reduction at 0 with 18 rule applications. Total rules 66 place count 62 transition count 146
Iterating global reduction 0 with 18 rules applied. Total rules applied 84 place count 62 transition count 146
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 85 place count 61 transition count 138
Iterating global reduction 0 with 1 rules applied. Total rules applied 86 place count 61 transition count 138
Applied a total of 86 rules in 25 ms. Remains 61 /104 variables (removed 43) and now considering 138/592 (removed 454) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 25 ms. Remains : 61/104 places, 138/592 transitions.
[2023-03-14 14:57:05] [INFO ] Flatten gal took : 6 ms
[2023-03-14 14:57:05] [INFO ] Flatten gal took : 7 ms
[2023-03-14 14:57:05] [INFO ] Input system was already deterministic with 138 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 80 transition count 352
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 80 transition count 352
Discarding 20 places :
Symmetric choice reduction at 0 with 20 rule applications. Total rules 68 place count 60 transition count 136
Iterating global reduction 0 with 20 rules applied. Total rules applied 88 place count 60 transition count 136
Applied a total of 88 rules in 8 ms. Remains 60 /104 variables (removed 44) and now considering 136/592 (removed 456) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 60/104 places, 136/592 transitions.
[2023-03-14 14:57:05] [INFO ] Flatten gal took : 6 ms
[2023-03-14 14:57:05] [INFO ] Flatten gal took : 8 ms
[2023-03-14 14:57:05] [INFO ] Input system was already deterministic with 136 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 80 transition count 352
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 80 transition count 352
Discarding 19 places :
Symmetric choice reduction at 0 with 19 rule applications. Total rules 67 place count 61 transition count 144
Iterating global reduction 0 with 19 rules applied. Total rules applied 86 place count 61 transition count 144
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 87 place count 60 transition count 136
Iterating global reduction 0 with 1 rules applied. Total rules applied 88 place count 60 transition count 136
Applied a total of 88 rules in 23 ms. Remains 60 /104 variables (removed 44) and now considering 136/592 (removed 456) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 24 ms. Remains : 60/104 places, 136/592 transitions.
[2023-03-14 14:57:05] [INFO ] Flatten gal took : 7 ms
[2023-03-14 14:57:05] [INFO ] Flatten gal took : 6 ms
[2023-03-14 14:57:05] [INFO ] Input system was already deterministic with 136 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 23 places :
Symmetric choice reduction at 0 with 23 rule applications. Total rules 23 place count 81 transition count 356
Iterating global reduction 0 with 23 rules applied. Total rules applied 46 place count 81 transition count 356
Discarding 15 places :
Symmetric choice reduction at 0 with 15 rule applications. Total rules 61 place count 66 transition count 178
Iterating global reduction 0 with 15 rules applied. Total rules applied 76 place count 66 transition count 178
Applied a total of 76 rules in 7 ms. Remains 66 /104 variables (removed 38) and now considering 178/592 (removed 414) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 66/104 places, 178/592 transitions.
[2023-03-14 14:57:05] [INFO ] Flatten gal took : 8 ms
[2023-03-14 14:57:05] [INFO ] Flatten gal took : 8 ms
[2023-03-14 14:57:05] [INFO ] Input system was already deterministic with 178 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 20 places :
Symmetric choice reduction at 0 with 20 rule applications. Total rules 20 place count 84 transition count 372
Iterating global reduction 0 with 20 rules applied. Total rules applied 40 place count 84 transition count 372
Discarding 10 places :
Symmetric choice reduction at 0 with 10 rule applications. Total rules 50 place count 74 transition count 246
Iterating global reduction 0 with 10 rules applied. Total rules applied 60 place count 74 transition count 246
Applied a total of 60 rules in 23 ms. Remains 74 /104 variables (removed 30) and now considering 246/592 (removed 346) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 24 ms. Remains : 74/104 places, 246/592 transitions.
[2023-03-14 14:57:05] [INFO ] Flatten gal took : 10 ms
[2023-03-14 14:57:05] [INFO ] Flatten gal took : 12 ms
[2023-03-14 14:57:05] [INFO ] Input system was already deterministic with 246 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 26 places :
Symmetric choice reduction at 0 with 26 rule applications. Total rules 26 place count 78 transition count 344
Iterating global reduction 0 with 26 rules applied. Total rules applied 52 place count 78 transition count 344
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 76 place count 54 transition count 108
Iterating global reduction 0 with 24 rules applied. Total rules applied 100 place count 54 transition count 108
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 103 place count 51 transition count 84
Iterating global reduction 0 with 3 rules applied. Total rules applied 106 place count 51 transition count 84
Applied a total of 106 rules in 8 ms. Remains 51 /104 variables (removed 53) and now considering 84/592 (removed 508) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 51/104 places, 84/592 transitions.
[2023-03-14 14:57:05] [INFO ] Flatten gal took : 4 ms
[2023-03-14 14:57:05] [INFO ] Flatten gal took : 5 ms
[2023-03-14 14:57:05] [INFO ] Input system was already deterministic with 84 transitions.
[2023-03-14 14:57:05] [INFO ] Flatten gal took : 34 ms
[2023-03-14 14:57:05] [INFO ] Flatten gal took : 34 ms
[2023-03-14 14:57:05] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 12 ms.
[2023-03-14 14:57:05] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 104 places, 592 transitions and 2944 arcs took 4 ms.
Total runtime 13177 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT PermAdmissibility-PT-01
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability

FORMULA PermAdmissibility-PT-01-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-PT-01-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-PT-01-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-PT-01-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-PT-01-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-PT-01-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-PT-01-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-PT-01-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-PT-01-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-PT-01-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-PT-01-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-PT-01-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-PT-01-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678805830911

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 21 (type EXCL) for 20 PermAdmissibility-PT-01-CTLFireability-05
lola: time limit : 156 sec
lola: memory limit: 32 pages
lola: FINISHED task # 21 (type EXCL) for PermAdmissibility-PT-01-CTLFireability-05
lola: result : true
lola: markings : 16
lola: fired transitions : 33
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: LAUNCH task # 24 (type EXCL) for 23 PermAdmissibility-PT-01-CTLFireability-06
lola: time limit : 199 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 24 (type EXCL) for PermAdmissibility-PT-01-CTLFireability-06
lola: result : false
lola: markings : 14
lola: fired transitions : 13
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 15 (type EXCL) for 14 PermAdmissibility-PT-01-CTLFireability-02
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 15 (type EXCL) for PermAdmissibility-PT-01-CTLFireability-02
lola: result : false
lola: markings : 1782
lola: fired transitions : 3241
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 27 (type EXCL) for 26 PermAdmissibility-PT-01-CTLFireability-08
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 51 (type FNDP) for 35 PermAdmissibility-PT-01-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 52 (type EQUN) for 35 PermAdmissibility-PT-01-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 54 (type SRCH) for 35 PermAdmissibility-PT-01-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 54 (type SRCH) for PermAdmissibility-PT-01-CTLFireability-12
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: FINISHED task # 51 (type FNDP) for PermAdmissibility-PT-01-CTLFireability-12
lola: result : true
lola: fired transitions : 912
lola: tried executions : 115
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 52 (type EQUN) for PermAdmissibility-PT-01-CTLFireability-12 (obsolete)
lola: FINISHED task # 52 (type EQUN) for PermAdmissibility-PT-01-CTLFireability-12
lola: result : unknown
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 56 (type FNDP) for 0 PermAdmissibility-PT-01-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 57 (type EQUN) for 0 PermAdmissibility-PT-01-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 59 (type SRCH) for 0 PermAdmissibility-PT-01-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 59 (type SRCH) for PermAdmissibility-PT-01-CTLFireability-00
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 56 (type FNDP) for PermAdmissibility-PT-01-CTLFireability-00
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 57 (type EQUN) for PermAdmissibility-PT-01-CTLFireability-00 (obsolete)
lola: FINISHED task # 27 (type EXCL) for PermAdmissibility-PT-01-CTLFireability-08
lola: result : false
lola: markings : 9862
lola: fired transitions : 18131
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 49 (type EXCL) for 48 PermAdmissibility-PT-01-CTLFireability-15
lola: time limit : 359 sec
lola: memory limit: 32 pages
lola: FINISHED task # 49 (type EXCL) for PermAdmissibility-PT-01-CTLFireability-15
lola: result : false
lola: markings : 5421
lola: fired transitions : 9867
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 43 (type EXCL) for 42 PermAdmissibility-PT-01-CTLFireability-13
lola: time limit : 399 sec
lola: memory limit: 32 pages
lola: FINISHED task # 43 (type EXCL) for PermAdmissibility-PT-01-CTLFireability-13
lola: result : true
lola: markings : 58
lola: fired transitions : 60
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 33 (type EXCL) for 32 PermAdmissibility-PT-01-CTLFireability-11
lola: time limit : 449 sec
lola: memory limit: 32 pages
lola: FINISHED task # 33 (type EXCL) for PermAdmissibility-PT-01-CTLFireability-11
lola: result : true
lola: markings : 81
lola: fired transitions : 87
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 18 (type EXCL) for 17 PermAdmissibility-PT-01-CTLFireability-04
lola: time limit : 513 sec
lola: memory limit: 32 pages
lola: FINISHED task # 18 (type EXCL) for PermAdmissibility-PT-01-CTLFireability-04
lola: result : true
lola: markings : 56
lola: fired transitions : 56
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 0 PermAdmissibility-PT-01-CTLFireability-00
lola: time limit : 599 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for PermAdmissibility-PT-01-CTLFireability-00
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 55 (type EXCL) for 35 PermAdmissibility-PT-01-CTLFireability-12
lola: time limit : 719 sec
lola: memory limit: 32 pages
lola: FINISHED task # 55 (type EXCL) for PermAdmissibility-PT-01-CTLFireability-12
lola: result : true
lola: markings : 17
lola: fired transitions : 16
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 9 (type EXCL) for 0 PermAdmissibility-PT-01-CTLFireability-00
lola: time limit : 899 sec
lola: memory limit: 32 pages
lola: FINISHED task # 9 (type EXCL) for PermAdmissibility-PT-01-CTLFireability-00
lola: result : false
lola: markings : 5817
lola: fired transitions : 11720
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 46 (type EXCL) for 45 PermAdmissibility-PT-01-CTLFireability-14
lola: time limit : 1198 sec
lola: memory limit: 32 pages
lola: FINISHED task # 46 (type EXCL) for PermAdmissibility-PT-01-CTLFireability-14
lola: result : false
lola: markings : 17
lola: fired transitions : 16
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 30 (type EXCL) for 29 PermAdmissibility-PT-01-CTLFireability-09
lola: time limit : 1798 sec
lola: memory limit: 32 pages
lola: FINISHED task # 30 (type EXCL) for PermAdmissibility-PT-01-CTLFireability-09
lola: result : false
lola: markings : 9862
lola: fired transitions : 27769
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 12 (type EXCL) for 11 PermAdmissibility-PT-01-CTLFireability-01
lola: time limit : 3596 sec
lola: memory limit: 32 pages
lola: FINISHED task # 12 (type EXCL) for PermAdmissibility-PT-01-CTLFireability-01
lola: result : true
lola: markings : 9391
lola: fired transitions : 12604
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-01-CTLFireability-00: CONJ false state space /EFEG
PermAdmissibility-PT-01-CTLFireability-01: CTL true CTL model checker
PermAdmissibility-PT-01-CTLFireability-02: CTL false CTL model checker
PermAdmissibility-PT-01-CTLFireability-04: CTL true CTL model checker
PermAdmissibility-PT-01-CTLFireability-05: CTL true CTL model checker
PermAdmissibility-PT-01-CTLFireability-06: CTL false CTL model checker
PermAdmissibility-PT-01-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-01-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-01-CTLFireability-11: CTL true CTL model checker
PermAdmissibility-PT-01-CTLFireability-12: CONJ false state space / EG
PermAdmissibility-PT-01-CTLFireability-13: CTL true CTL model checker
PermAdmissibility-PT-01-CTLFireability-14: CTL false CTL model checker
PermAdmissibility-PT-01-CTLFireability-15: CTL false CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PermAdmissibility-PT-01"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is PermAdmissibility-PT-01, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r263-smll-167863538300506"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/PermAdmissibility-PT-01.tgz
mv PermAdmissibility-PT-01 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;