About the Execution of LoLa+red for ParamProductionCell-PT-4
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
916.943 | 98981.00 | 113539.00 | 868.00 | FFTTFFTFFTFTFTTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r263-smll-167863538200394.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is ParamProductionCell-PT-4, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r263-smll-167863538200394
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 652K
-rw-r--r-- 1 mcc users 9.3K Feb 26 17:17 CTLCardinality.txt
-rw-r--r-- 1 mcc users 86K Feb 26 17:17 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.0K Feb 26 17:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 58K Feb 26 17:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.2K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.8K Feb 25 16:30 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K Feb 25 16:30 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Feb 25 16:30 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:30 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 26 17:19 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 117K Feb 26 17:19 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.1K Feb 26 17:18 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 58K Feb 26 17:18 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 25 16:30 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:30 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 174K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-00
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-01
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-02
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-03
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-04
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-05
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-06
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-07
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-08
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-09
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-10
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-11
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-12
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-13
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-14
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678781231088
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ParamProductionCell-PT-4
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-14 08:07:14] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-14 08:07:14] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-14 08:07:14] [INFO ] Load time of PNML (sax parser for PT used): 147 ms
[2023-03-14 08:07:14] [INFO ] Transformed 231 places.
[2023-03-14 08:07:14] [INFO ] Transformed 202 transitions.
[2023-03-14 08:07:14] [INFO ] Found NUPN structural information;
[2023-03-14 08:07:14] [INFO ] Parsed PT model containing 231 places and 202 transitions and 846 arcs in 317 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 20 ms.
Support contains 142 out of 231 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 231/231 places, 202/202 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 230 transition count 201
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 230 transition count 201
Applied a total of 2 rules in 60 ms. Remains 230 /231 variables (removed 1) and now considering 201/202 (removed 1) transitions.
// Phase 1: matrix 201 rows 230 cols
[2023-03-14 08:07:15] [INFO ] Computed 59 place invariants in 29 ms
[2023-03-14 08:07:15] [INFO ] Implicit Places using invariants in 555 ms returned [35, 73, 120, 196]
Discarding 4 places :
Implicit Place search using SMT only with invariants took 614 ms to find 4 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 226/231 places, 201/202 transitions.
Applied a total of 0 rules in 14 ms. Remains 226 /226 variables (removed 0) and now considering 201/201 (removed 0) transitions.
Finished structural reductions in LTL mode , in 2 iterations and 689 ms. Remains : 226/231 places, 201/202 transitions.
Support contains 142 out of 226 places after structural reductions.
[2023-03-14 08:07:16] [INFO ] Flatten gal took : 66 ms
[2023-03-14 08:07:16] [INFO ] Flatten gal took : 64 ms
[2023-03-14 08:07:16] [INFO ] Input system was already deterministic with 201 transitions.
Support contains 140 out of 226 places (down from 142) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 781 ms. (steps per millisecond=12 ) properties (out of 90) seen :84
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 139 ms. (steps per millisecond=71 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 120 ms. (steps per millisecond=83 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 101 ms. (steps per millisecond=99 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 105 ms. (steps per millisecond=95 ) properties (out of 6) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 120 ms. (steps per millisecond=83 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 186 ms. (steps per millisecond=53 ) properties (out of 5) seen :0
Running SMT prover for 5 properties.
// Phase 1: matrix 201 rows 226 cols
[2023-03-14 08:07:17] [INFO ] Computed 55 place invariants in 12 ms
[2023-03-14 08:07:18] [INFO ] [Real]Absence check using 32 positive place invariants in 19 ms returned sat
[2023-03-14 08:07:18] [INFO ] [Real]Absence check using 32 positive and 23 generalized place invariants in 15 ms returned sat
[2023-03-14 08:07:18] [INFO ] After 240ms SMT Verify possible using state equation in real domain returned unsat :3 sat :1 real:1
[2023-03-14 08:07:18] [INFO ] State equation strengthened by 68 read => feed constraints.
[2023-03-14 08:07:18] [INFO ] After 47ms SMT Verify possible using 68 Read/Feed constraints in real domain returned unsat :3 sat :0 real:2
[2023-03-14 08:07:18] [INFO ] After 553ms SMT Verify possible using all constraints in real domain returned unsat :3 sat :0 real:2
[2023-03-14 08:07:18] [INFO ] [Nat]Absence check using 32 positive place invariants in 17 ms returned sat
[2023-03-14 08:07:18] [INFO ] [Nat]Absence check using 32 positive and 23 generalized place invariants in 13 ms returned sat
[2023-03-14 08:07:18] [INFO ] After 138ms SMT Verify possible using state equation in natural domain returned unsat :3 sat :2
[2023-03-14 08:07:18] [INFO ] After 65ms SMT Verify possible using 68 Read/Feed constraints in natural domain returned unsat :3 sat :2
[2023-03-14 08:07:19] [INFO ] Deduced a trap composed of 7 places in 99 ms of which 8 ms to minimize.
[2023-03-14 08:07:19] [INFO ] Deduced a trap composed of 8 places in 80 ms of which 1 ms to minimize.
[2023-03-14 08:07:19] [INFO ] Deduced a trap composed of 10 places in 65 ms of which 1 ms to minimize.
[2023-03-14 08:07:19] [INFO ] Deduced a trap composed of 8 places in 97 ms of which 2 ms to minimize.
[2023-03-14 08:07:19] [INFO ] Deduced a trap composed of 41 places in 102 ms of which 2 ms to minimize.
[2023-03-14 08:07:19] [INFO ] Deduced a trap composed of 7 places in 95 ms of which 2 ms to minimize.
[2023-03-14 08:07:19] [INFO ] Deduced a trap composed of 10 places in 133 ms of which 1 ms to minimize.
[2023-03-14 08:07:19] [INFO ] Trap strengthening (SAT) tested/added 8/7 trap constraints in 860 ms
[2023-03-14 08:07:19] [INFO ] Deduced a trap composed of 5 places in 94 ms of which 1 ms to minimize.
[2023-03-14 08:07:20] [INFO ] Deduced a trap composed of 15 places in 91 ms of which 1 ms to minimize.
[2023-03-14 08:07:20] [INFO ] Deduced a trap composed of 41 places in 91 ms of which 1 ms to minimize.
[2023-03-14 08:07:20] [INFO ] Deduced a trap composed of 29 places in 90 ms of which 0 ms to minimize.
[2023-03-14 08:07:20] [INFO ] Trap strengthening procedure managed to obtain unsat after adding 4 trap constraints in 458 ms
[2023-03-14 08:07:20] [INFO ] After 1438ms SMT Verify possible using trap constraints in natural domain returned unsat :4 sat :1
Attempting to minimize the solution found.
Minimization took 37 ms.
[2023-03-14 08:07:20] [INFO ] After 1777ms SMT Verify possible using all constraints in natural domain returned unsat :4 sat :1
Fused 5 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 4 ms.
Support contains 4 out of 226 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 226/226 places, 201/201 transitions.
Performed 18 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 18 Pre rules applied. Total rules applied 0 place count 226 transition count 183
Deduced a syphon composed of 18 places in 1 ms
Reduce places removed 18 places and 0 transitions.
Iterating global reduction 0 with 36 rules applied. Total rules applied 36 place count 208 transition count 183
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 41 place count 203 transition count 178
Iterating global reduction 0 with 5 rules applied. Total rules applied 46 place count 203 transition count 178
Performed 18 Post agglomeration using F-continuation condition.Transition count delta: 18
Deduced a syphon composed of 18 places in 0 ms
Reduce places removed 18 places and 0 transitions.
Iterating global reduction 0 with 36 rules applied. Total rules applied 82 place count 185 transition count 160
Free-agglomeration rule (complex) applied 4 times.
Iterating global reduction 0 with 4 rules applied. Total rules applied 86 place count 185 transition count 156
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 0 with 4 rules applied. Total rules applied 90 place count 181 transition count 156
Applied a total of 90 rules in 79 ms. Remains 181 /226 variables (removed 45) and now considering 156/201 (removed 45) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 79 ms. Remains : 181/226 places, 156/201 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=322 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=625 ) properties (out of 1) seen :0
Finished probabilistic random walk after 62145 steps, run visited all 1 properties in 292 ms. (steps per millisecond=212 )
Probabilistic random walk after 62145 steps, saw 26923 distinct states, run finished after 293 ms. (steps per millisecond=212 ) properties seen :1
Successfully simplified 4 atomic propositions for a total of 16 simplifications.
[2023-03-14 08:07:20] [INFO ] Flatten gal took : 19 ms
[2023-03-14 08:07:20] [INFO ] Flatten gal took : 19 ms
[2023-03-14 08:07:20] [INFO ] Input system was already deterministic with 201 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 226/226 places, 201/201 transitions.
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 5 place count 221 transition count 196
Iterating global reduction 0 with 5 rules applied. Total rules applied 10 place count 221 transition count 196
Applied a total of 10 rules in 16 ms. Remains 221 /226 variables (removed 5) and now considering 196/201 (removed 5) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 16 ms. Remains : 221/226 places, 196/201 transitions.
[2023-03-14 08:07:20] [INFO ] Flatten gal took : 15 ms
[2023-03-14 08:07:20] [INFO ] Flatten gal took : 16 ms
[2023-03-14 08:07:20] [INFO ] Input system was already deterministic with 196 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 226/226 places, 201/201 transitions.
Performed 18 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 18 Pre rules applied. Total rules applied 0 place count 226 transition count 183
Deduced a syphon composed of 18 places in 0 ms
Reduce places removed 18 places and 0 transitions.
Iterating global reduction 0 with 36 rules applied. Total rules applied 36 place count 208 transition count 183
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 40 place count 204 transition count 179
Iterating global reduction 0 with 4 rules applied. Total rules applied 44 place count 204 transition count 179
Performed 18 Post agglomeration using F-continuation condition.Transition count delta: 18
Deduced a syphon composed of 18 places in 0 ms
Reduce places removed 18 places and 0 transitions.
Iterating global reduction 0 with 36 rules applied. Total rules applied 80 place count 186 transition count 161
Applied a total of 80 rules in 29 ms. Remains 186 /226 variables (removed 40) and now considering 161/201 (removed 40) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 29 ms. Remains : 186/226 places, 161/201 transitions.
[2023-03-14 08:07:20] [INFO ] Flatten gal took : 12 ms
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 13 ms
[2023-03-14 08:07:21] [INFO ] Input system was already deterministic with 161 transitions.
Starting structural reductions in LTL mode, iteration 0 : 226/226 places, 201/201 transitions.
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 5 place count 221 transition count 196
Iterating global reduction 0 with 5 rules applied. Total rules applied 10 place count 221 transition count 196
Applied a total of 10 rules in 9 ms. Remains 221 /226 variables (removed 5) and now considering 196/201 (removed 5) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 221/226 places, 196/201 transitions.
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 17 ms
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 15 ms
[2023-03-14 08:07:21] [INFO ] Input system was already deterministic with 196 transitions.
Starting structural reductions in LTL mode, iteration 0 : 226/226 places, 201/201 transitions.
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 5 place count 221 transition count 196
Iterating global reduction 0 with 5 rules applied. Total rules applied 10 place count 221 transition count 196
Applied a total of 10 rules in 8 ms. Remains 221 /226 variables (removed 5) and now considering 196/201 (removed 5) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 221/226 places, 196/201 transitions.
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 12 ms
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 14 ms
[2023-03-14 08:07:21] [INFO ] Input system was already deterministic with 196 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 226/226 places, 201/201 transitions.
Performed 18 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 18 Pre rules applied. Total rules applied 0 place count 226 transition count 183
Deduced a syphon composed of 18 places in 1 ms
Reduce places removed 18 places and 0 transitions.
Iterating global reduction 0 with 36 rules applied. Total rules applied 36 place count 208 transition count 183
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 40 place count 204 transition count 179
Iterating global reduction 0 with 4 rules applied. Total rules applied 44 place count 204 transition count 179
Performed 18 Post agglomeration using F-continuation condition.Transition count delta: 18
Deduced a syphon composed of 18 places in 1 ms
Reduce places removed 18 places and 0 transitions.
Iterating global reduction 0 with 36 rules applied. Total rules applied 80 place count 186 transition count 161
Applied a total of 80 rules in 28 ms. Remains 186 /226 variables (removed 40) and now considering 161/201 (removed 40) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 30 ms. Remains : 186/226 places, 161/201 transitions.
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 11 ms
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 12 ms
[2023-03-14 08:07:21] [INFO ] Input system was already deterministic with 161 transitions.
Starting structural reductions in LTL mode, iteration 0 : 226/226 places, 201/201 transitions.
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 5 place count 221 transition count 196
Iterating global reduction 0 with 5 rules applied. Total rules applied 10 place count 221 transition count 196
Applied a total of 10 rules in 8 ms. Remains 221 /226 variables (removed 5) and now considering 196/201 (removed 5) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 221/226 places, 196/201 transitions.
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 13 ms
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 12 ms
[2023-03-14 08:07:21] [INFO ] Input system was already deterministic with 196 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 226/226 places, 201/201 transitions.
Performed 18 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 18 Pre rules applied. Total rules applied 0 place count 226 transition count 183
Deduced a syphon composed of 18 places in 1 ms
Reduce places removed 18 places and 0 transitions.
Iterating global reduction 0 with 36 rules applied. Total rules applied 36 place count 208 transition count 183
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 41 place count 203 transition count 178
Iterating global reduction 0 with 5 rules applied. Total rules applied 46 place count 203 transition count 178
Performed 18 Post agglomeration using F-continuation condition.Transition count delta: 18
Deduced a syphon composed of 18 places in 0 ms
Reduce places removed 18 places and 0 transitions.
Iterating global reduction 0 with 36 rules applied. Total rules applied 82 place count 185 transition count 160
Applied a total of 82 rules in 28 ms. Remains 185 /226 variables (removed 41) and now considering 160/201 (removed 41) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 28 ms. Remains : 185/226 places, 160/201 transitions.
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 10 ms
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 10 ms
[2023-03-14 08:07:21] [INFO ] Input system was already deterministic with 160 transitions.
Starting structural reductions in LTL mode, iteration 0 : 226/226 places, 201/201 transitions.
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 5 place count 221 transition count 196
Iterating global reduction 0 with 5 rules applied. Total rules applied 10 place count 221 transition count 196
Applied a total of 10 rules in 8 ms. Remains 221 /226 variables (removed 5) and now considering 196/201 (removed 5) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 221/226 places, 196/201 transitions.
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 10 ms
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 10 ms
[2023-03-14 08:07:21] [INFO ] Input system was already deterministic with 196 transitions.
Starting structural reductions in LTL mode, iteration 0 : 226/226 places, 201/201 transitions.
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 5 place count 221 transition count 196
Iterating global reduction 0 with 5 rules applied. Total rules applied 10 place count 221 transition count 196
Applied a total of 10 rules in 8 ms. Remains 221 /226 variables (removed 5) and now considering 196/201 (removed 5) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 221/226 places, 196/201 transitions.
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 10 ms
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 11 ms
[2023-03-14 08:07:21] [INFO ] Input system was already deterministic with 196 transitions.
Starting structural reductions in LTL mode, iteration 0 : 226/226 places, 201/201 transitions.
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 5 place count 221 transition count 196
Iterating global reduction 0 with 5 rules applied. Total rules applied 10 place count 221 transition count 196
Applied a total of 10 rules in 7 ms. Remains 221 /226 variables (removed 5) and now considering 196/201 (removed 5) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 221/226 places, 196/201 transitions.
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 10 ms
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 11 ms
[2023-03-14 08:07:21] [INFO ] Input system was already deterministic with 196 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 226/226 places, 201/201 transitions.
Performed 18 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 18 Pre rules applied. Total rules applied 0 place count 226 transition count 183
Deduced a syphon composed of 18 places in 0 ms
Reduce places removed 18 places and 0 transitions.
Iterating global reduction 0 with 36 rules applied. Total rules applied 36 place count 208 transition count 183
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 41 place count 203 transition count 178
Iterating global reduction 0 with 5 rules applied. Total rules applied 46 place count 203 transition count 178
Performed 18 Post agglomeration using F-continuation condition.Transition count delta: 18
Deduced a syphon composed of 18 places in 1 ms
Reduce places removed 18 places and 0 transitions.
Iterating global reduction 0 with 36 rules applied. Total rules applied 82 place count 185 transition count 160
Applied a total of 82 rules in 26 ms. Remains 185 /226 variables (removed 41) and now considering 160/201 (removed 41) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 26 ms. Remains : 185/226 places, 160/201 transitions.
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 8 ms
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 9 ms
[2023-03-14 08:07:21] [INFO ] Input system was already deterministic with 160 transitions.
Finished random walk after 107 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=53 )
FORMULA ParamProductionCell-PT-4-CTLFireability-10 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 226/226 places, 201/201 transitions.
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 4 place count 222 transition count 197
Iterating global reduction 0 with 4 rules applied. Total rules applied 8 place count 222 transition count 197
Applied a total of 8 rules in 7 ms. Remains 222 /226 variables (removed 4) and now considering 197/201 (removed 4) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 222/226 places, 197/201 transitions.
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 9 ms
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 11 ms
[2023-03-14 08:07:21] [INFO ] Input system was already deterministic with 197 transitions.
Starting structural reductions in LTL mode, iteration 0 : 226/226 places, 201/201 transitions.
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 5 place count 221 transition count 196
Iterating global reduction 0 with 5 rules applied. Total rules applied 10 place count 221 transition count 196
Applied a total of 10 rules in 7 ms. Remains 221 /226 variables (removed 5) and now considering 196/201 (removed 5) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 221/226 places, 196/201 transitions.
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 10 ms
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 11 ms
[2023-03-14 08:07:21] [INFO ] Input system was already deterministic with 196 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 226/226 places, 201/201 transitions.
Performed 18 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 18 Pre rules applied. Total rules applied 0 place count 226 transition count 183
Deduced a syphon composed of 18 places in 0 ms
Reduce places removed 18 places and 0 transitions.
Iterating global reduction 0 with 36 rules applied. Total rules applied 36 place count 208 transition count 183
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 41 place count 203 transition count 178
Iterating global reduction 0 with 5 rules applied. Total rules applied 46 place count 203 transition count 178
Performed 18 Post agglomeration using F-continuation condition.Transition count delta: 18
Deduced a syphon composed of 18 places in 0 ms
Reduce places removed 18 places and 0 transitions.
Iterating global reduction 0 with 36 rules applied. Total rules applied 82 place count 185 transition count 160
Applied a total of 82 rules in 25 ms. Remains 185 /226 variables (removed 41) and now considering 160/201 (removed 41) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 25 ms. Remains : 185/226 places, 160/201 transitions.
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 8 ms
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 9 ms
[2023-03-14 08:07:21] [INFO ] Input system was already deterministic with 160 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 226/226 places, 201/201 transitions.
Performed 18 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 18 Pre rules applied. Total rules applied 0 place count 226 transition count 183
Deduced a syphon composed of 18 places in 1 ms
Reduce places removed 18 places and 0 transitions.
Iterating global reduction 0 with 36 rules applied. Total rules applied 36 place count 208 transition count 183
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 41 place count 203 transition count 178
Iterating global reduction 0 with 5 rules applied. Total rules applied 46 place count 203 transition count 178
Performed 18 Post agglomeration using F-continuation condition.Transition count delta: 18
Deduced a syphon composed of 18 places in 1 ms
Reduce places removed 18 places and 0 transitions.
Iterating global reduction 0 with 36 rules applied. Total rules applied 82 place count 185 transition count 160
Applied a total of 82 rules in 24 ms. Remains 185 /226 variables (removed 41) and now considering 160/201 (removed 41) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 25 ms. Remains : 185/226 places, 160/201 transitions.
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 8 ms
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 9 ms
[2023-03-14 08:07:21] [INFO ] Input system was already deterministic with 160 transitions.
Finished random walk after 97 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=48 )
FORMULA ParamProductionCell-PT-4-CTLFireability-14 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 226/226 places, 201/201 transitions.
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 5 place count 221 transition count 196
Iterating global reduction 0 with 5 rules applied. Total rules applied 10 place count 221 transition count 196
Applied a total of 10 rules in 7 ms. Remains 221 /226 variables (removed 5) and now considering 196/201 (removed 5) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 221/226 places, 196/201 transitions.
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 9 ms
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 9 ms
[2023-03-14 08:07:21] [INFO ] Input system was already deterministic with 196 transitions.
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 11 ms
[2023-03-14 08:07:21] [INFO ] Flatten gal took : 11 ms
[2023-03-14 08:07:21] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 5 ms.
[2023-03-14 08:07:21] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 226 places, 201 transitions and 834 arcs took 2 ms.
Total runtime 7398 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT ParamProductionCell-PT-4
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/371
CTLFireability
FORMULA ParamProductionCell-PT-4-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-4-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-4-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-4-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-4-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-4-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-4-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-4-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-4-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-4-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-4-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-4-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-4-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-4-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678781330069
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/371/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/371/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/371/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 9 (type EXCL) for 6 ParamProductionCell-PT-4-CTLFireability-02
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-4-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
ParamProductionCell-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 4/239 4/32 ParamProductionCell-PT-4-CTLFireability-02 730369 m, 146073 m/sec, 2217087 t fired, .
Time elapsed: 5 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-4-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
ParamProductionCell-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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ParamProductionCell-PT-4-CTLFireability-02: DISJ true CTL model checker
ParamProductionCell-PT-4-CTLFireability-03: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-05: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-06: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-07: EFEG false state space /EFEG
ParamProductionCell-PT-4-CTLFireability-08: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-09: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-11: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-12: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-13: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-4-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 5/1762 2/32 ParamProductionCell-PT-4-CTLFireability-04 403642 m, 75629 m/sec, 3500543 t fired, .
Time elapsed: 80 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 17 (type EXCL) for ParamProductionCell-PT-4-CTLFireability-04
lola: result : false
lola: markings : 551256
lola: fired transitions : 5008004
lola: time used : 8.000000
lola: memory pages used : 3
lola: LAUNCH task # 4 (type EXCL) for 3 ParamProductionCell-PT-4-CTLFireability-01
lola: time limit : 3517 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-4-CTLFireability-00: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-02: DISJ true CTL model checker
ParamProductionCell-PT-4-CTLFireability-03: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-04: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-05: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-06: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-07: EFEG false state space /EFEG
ParamProductionCell-PT-4-CTLFireability-08: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-09: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-11: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-12: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-13: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-4-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 2/3517 2/32 ParamProductionCell-PT-4-CTLFireability-01 435621 m, 87124 m/sec, 1660548 t fired, .
Time elapsed: 85 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 4 (type EXCL) for ParamProductionCell-PT-4-CTLFireability-01
lola: result : false
lola: markings : 554200
lola: fired transitions : 2256746
lola: time used : 4.000000
lola: memory pages used : 3
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-4-CTLFireability-00: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-02: DISJ true CTL model checker
ParamProductionCell-PT-4-CTLFireability-03: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-04: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-05: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-06: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-07: EFEG false state space /EFEG
ParamProductionCell-PT-4-CTLFireability-08: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-09: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-11: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-12: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-13: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-15: CTL false CTL model checker
Time elapsed: 87 secs. Pages in use: 11
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ParamProductionCell-PT-4"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is ParamProductionCell-PT-4, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r263-smll-167863538200394"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ParamProductionCell-PT-4.tgz
mv ParamProductionCell-PT-4 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;