About the Execution of LoLa+red for ParamProductionCell-PT-3
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
1046.048 | 125924.00 | 138170.00 | 672.00 | FFFTFFFTTTTFTFTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r263-smll-167863538200386.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is ParamProductionCell-PT-3, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r263-smll-167863538200386
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 616K
-rw-r--r-- 1 mcc users 8.0K Feb 26 17:15 CTLCardinality.txt
-rw-r--r-- 1 mcc users 69K Feb 26 17:15 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.3K Feb 26 17:15 CTLFireability.txt
-rw-r--r-- 1 mcc users 57K Feb 26 17:15 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.2K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.8K Feb 25 16:29 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K Feb 25 16:29 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Feb 25 16:29 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:29 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.9K Feb 26 17:17 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 81K Feb 26 17:17 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Feb 26 17:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 84K Feb 26 17:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 25 16:29 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:29 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 174K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-00
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-01
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-02
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-03
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-04
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-05
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-06
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-07
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-08
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-09
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-10
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-11
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-12
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-13
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-14
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678780783358
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ParamProductionCell-PT-3
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-14 07:59:45] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-14 07:59:45] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-14 07:59:45] [INFO ] Load time of PNML (sax parser for PT used): 99 ms
[2023-03-14 07:59:45] [INFO ] Transformed 231 places.
[2023-03-14 07:59:45] [INFO ] Transformed 202 transitions.
[2023-03-14 07:59:45] [INFO ] Found NUPN structural information;
[2023-03-14 07:59:45] [INFO ] Parsed PT model containing 231 places and 202 transitions and 846 arcs in 201 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 14 ms.
Support contains 148 out of 231 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 231/231 places, 202/202 transitions.
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 3 place count 228 transition count 199
Iterating global reduction 0 with 3 rules applied. Total rules applied 6 place count 228 transition count 199
Applied a total of 6 rules in 41 ms. Remains 228 /231 variables (removed 3) and now considering 199/202 (removed 3) transitions.
// Phase 1: matrix 199 rows 228 cols
[2023-03-14 07:59:46] [INFO ] Computed 59 place invariants in 19 ms
[2023-03-14 07:59:46] [INFO ] Implicit Places using invariants in 396 ms returned [15, 35, 36, 42, 118, 193]
Discarding 6 places :
Implicit Place search using SMT only with invariants took 435 ms to find 6 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 222/231 places, 199/202 transitions.
Applied a total of 0 rules in 6 ms. Remains 222 /222 variables (removed 0) and now considering 199/199 (removed 0) transitions.
Finished structural reductions in LTL mode , in 2 iterations and 483 ms. Remains : 222/231 places, 199/202 transitions.
Support contains 148 out of 222 places after structural reductions.
[2023-03-14 07:59:46] [INFO ] Flatten gal took : 64 ms
[2023-03-14 07:59:46] [INFO ] Flatten gal took : 29 ms
[2023-03-14 07:59:46] [INFO ] Input system was already deterministic with 199 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 648 ms. (steps per millisecond=15 ) properties (out of 87) seen :79
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 162 ms. (steps per millisecond=61 ) properties (out of 8) seen :2
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 123 ms. (steps per millisecond=81 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 122 ms. (steps per millisecond=81 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 145 ms. (steps per millisecond=68 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 81 ms. (steps per millisecond=123 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 101 ms. (steps per millisecond=99 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 74 ms. (steps per millisecond=135 ) properties (out of 6) seen :1
Running SMT prover for 5 properties.
// Phase 1: matrix 199 rows 222 cols
[2023-03-14 07:59:48] [INFO ] Computed 53 place invariants in 10 ms
[2023-03-14 07:59:48] [INFO ] After 168ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:5
[2023-03-14 07:59:48] [INFO ] [Nat]Absence check using 31 positive place invariants in 15 ms returned sat
[2023-03-14 07:59:48] [INFO ] [Nat]Absence check using 31 positive and 22 generalized place invariants in 41 ms returned sat
[2023-03-14 07:59:48] [INFO ] After 229ms SMT Verify possible using all constraints in natural domain returned unsat :5 sat :0
Fused 5 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 5 atomic propositions for a total of 16 simplifications.
[2023-03-14 07:59:48] [INFO ] Flatten gal took : 21 ms
[2023-03-14 07:59:49] [INFO ] Flatten gal took : 19 ms
[2023-03-14 07:59:49] [INFO ] Input system was already deterministic with 199 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 222/222 places, 199/199 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 222 transition count 197
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 4 place count 220 transition count 197
Performed 15 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 15 Pre rules applied. Total rules applied 4 place count 220 transition count 182
Deduced a syphon composed of 15 places in 1 ms
Reduce places removed 15 places and 0 transitions.
Iterating global reduction 2 with 30 rules applied. Total rules applied 34 place count 205 transition count 182
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 37 place count 202 transition count 179
Iterating global reduction 2 with 3 rules applied. Total rules applied 40 place count 202 transition count 179
Performed 18 Post agglomeration using F-continuation condition.Transition count delta: 18
Deduced a syphon composed of 18 places in 1 ms
Reduce places removed 18 places and 0 transitions.
Iterating global reduction 2 with 36 rules applied. Total rules applied 76 place count 184 transition count 161
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 78 place count 183 transition count 160
Applied a total of 78 rules in 110 ms. Remains 183 /222 variables (removed 39) and now considering 160/199 (removed 39) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 110 ms. Remains : 183/222 places, 160/199 transitions.
[2023-03-14 07:59:49] [INFO ] Flatten gal took : 13 ms
[2023-03-14 07:59:49] [INFO ] Flatten gal took : 27 ms
[2023-03-14 07:59:49] [INFO ] Input system was already deterministic with 160 transitions.
Starting structural reductions in LTL mode, iteration 0 : 222/222 places, 199/199 transitions.
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 3 place count 219 transition count 196
Iterating global reduction 0 with 3 rules applied. Total rules applied 6 place count 219 transition count 196
Applied a total of 6 rules in 21 ms. Remains 219 /222 variables (removed 3) and now considering 196/199 (removed 3) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 21 ms. Remains : 219/222 places, 196/199 transitions.
[2023-03-14 07:59:49] [INFO ] Flatten gal took : 27 ms
[2023-03-14 07:59:49] [INFO ] Flatten gal took : 20 ms
[2023-03-14 07:59:49] [INFO ] Input system was already deterministic with 196 transitions.
Starting structural reductions in LTL mode, iteration 0 : 222/222 places, 199/199 transitions.
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 3 place count 219 transition count 196
Iterating global reduction 0 with 3 rules applied. Total rules applied 6 place count 219 transition count 196
Applied a total of 6 rules in 10 ms. Remains 219 /222 variables (removed 3) and now considering 196/199 (removed 3) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10 ms. Remains : 219/222 places, 196/199 transitions.
[2023-03-14 07:59:49] [INFO ] Flatten gal took : 12 ms
[2023-03-14 07:59:49] [INFO ] Flatten gal took : 13 ms
[2023-03-14 07:59:49] [INFO ] Input system was already deterministic with 196 transitions.
Starting structural reductions in LTL mode, iteration 0 : 222/222 places, 199/199 transitions.
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 3 place count 219 transition count 196
Iterating global reduction 0 with 3 rules applied. Total rules applied 6 place count 219 transition count 196
Applied a total of 6 rules in 9 ms. Remains 219 /222 variables (removed 3) and now considering 196/199 (removed 3) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 219/222 places, 196/199 transitions.
[2023-03-14 07:59:49] [INFO ] Flatten gal took : 11 ms
[2023-03-14 07:59:49] [INFO ] Flatten gal took : 12 ms
[2023-03-14 07:59:49] [INFO ] Input system was already deterministic with 196 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 222/222 places, 199/199 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 222 transition count 197
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 4 place count 220 transition count 197
Performed 13 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 13 Pre rules applied. Total rules applied 4 place count 220 transition count 184
Deduced a syphon composed of 13 places in 0 ms
Reduce places removed 13 places and 0 transitions.
Iterating global reduction 2 with 26 rules applied. Total rules applied 30 place count 207 transition count 184
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 33 place count 204 transition count 181
Iterating global reduction 2 with 3 rules applied. Total rules applied 36 place count 204 transition count 181
Performed 9 Post agglomeration using F-continuation condition.Transition count delta: 9
Deduced a syphon composed of 9 places in 1 ms
Reduce places removed 9 places and 0 transitions.
Iterating global reduction 2 with 18 rules applied. Total rules applied 54 place count 195 transition count 172
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 56 place count 194 transition count 171
Applied a total of 56 rules in 38 ms. Remains 194 /222 variables (removed 28) and now considering 171/199 (removed 28) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 39 ms. Remains : 194/222 places, 171/199 transitions.
[2023-03-14 07:59:49] [INFO ] Flatten gal took : 10 ms
[2023-03-14 07:59:49] [INFO ] Flatten gal took : 11 ms
[2023-03-14 07:59:49] [INFO ] Input system was already deterministic with 171 transitions.
Starting structural reductions in LTL mode, iteration 0 : 222/222 places, 199/199 transitions.
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 3 place count 219 transition count 196
Iterating global reduction 0 with 3 rules applied. Total rules applied 6 place count 219 transition count 196
Applied a total of 6 rules in 8 ms. Remains 219 /222 variables (removed 3) and now considering 196/199 (removed 3) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 219/222 places, 196/199 transitions.
[2023-03-14 07:59:49] [INFO ] Flatten gal took : 10 ms
[2023-03-14 07:59:49] [INFO ] Flatten gal took : 12 ms
[2023-03-14 07:59:49] [INFO ] Input system was already deterministic with 196 transitions.
Starting structural reductions in LTL mode, iteration 0 : 222/222 places, 199/199 transitions.
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 2 place count 220 transition count 197
Iterating global reduction 0 with 2 rules applied. Total rules applied 4 place count 220 transition count 197
Applied a total of 4 rules in 8 ms. Remains 220 /222 variables (removed 2) and now considering 197/199 (removed 2) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 220/222 places, 197/199 transitions.
[2023-03-14 07:59:49] [INFO ] Flatten gal took : 9 ms
[2023-03-14 07:59:49] [INFO ] Flatten gal took : 10 ms
[2023-03-14 07:59:49] [INFO ] Input system was already deterministic with 197 transitions.
Starting structural reductions in LTL mode, iteration 0 : 222/222 places, 199/199 transitions.
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 3 place count 219 transition count 196
Iterating global reduction 0 with 3 rules applied. Total rules applied 6 place count 219 transition count 196
Applied a total of 6 rules in 8 ms. Remains 219 /222 variables (removed 3) and now considering 196/199 (removed 3) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 219/222 places, 196/199 transitions.
[2023-03-14 07:59:49] [INFO ] Flatten gal took : 9 ms
[2023-03-14 07:59:49] [INFO ] Flatten gal took : 9 ms
[2023-03-14 07:59:49] [INFO ] Input system was already deterministic with 196 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 222/222 places, 199/199 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 222 transition count 197
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 4 place count 220 transition count 197
Performed 14 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 14 Pre rules applied. Total rules applied 4 place count 220 transition count 183
Deduced a syphon composed of 14 places in 1 ms
Reduce places removed 14 places and 0 transitions.
Iterating global reduction 2 with 28 rules applied. Total rules applied 32 place count 206 transition count 183
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 35 place count 203 transition count 180
Iterating global reduction 2 with 3 rules applied. Total rules applied 38 place count 203 transition count 180
Performed 15 Post agglomeration using F-continuation condition.Transition count delta: 15
Deduced a syphon composed of 15 places in 1 ms
Reduce places removed 15 places and 0 transitions.
Iterating global reduction 2 with 30 rules applied. Total rules applied 68 place count 188 transition count 165
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 70 place count 187 transition count 164
Applied a total of 70 rules in 42 ms. Remains 187 /222 variables (removed 35) and now considering 164/199 (removed 35) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 42 ms. Remains : 187/222 places, 164/199 transitions.
[2023-03-14 07:59:49] [INFO ] Flatten gal took : 7 ms
[2023-03-14 07:59:49] [INFO ] Flatten gal took : 8 ms
[2023-03-14 07:59:49] [INFO ] Input system was already deterministic with 164 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 222/222 places, 199/199 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 222 transition count 197
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 4 place count 220 transition count 197
Performed 16 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 16 Pre rules applied. Total rules applied 4 place count 220 transition count 181
Deduced a syphon composed of 16 places in 1 ms
Reduce places removed 16 places and 0 transitions.
Iterating global reduction 2 with 32 rules applied. Total rules applied 36 place count 204 transition count 181
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 39 place count 201 transition count 178
Iterating global reduction 2 with 3 rules applied. Total rules applied 42 place count 201 transition count 178
Performed 19 Post agglomeration using F-continuation condition.Transition count delta: 19
Deduced a syphon composed of 19 places in 1 ms
Reduce places removed 19 places and 0 transitions.
Iterating global reduction 2 with 38 rules applied. Total rules applied 80 place count 182 transition count 159
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 82 place count 181 transition count 158
Applied a total of 82 rules in 35 ms. Remains 181 /222 variables (removed 41) and now considering 158/199 (removed 41) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 35 ms. Remains : 181/222 places, 158/199 transitions.
[2023-03-14 07:59:49] [INFO ] Flatten gal took : 7 ms
[2023-03-14 07:59:49] [INFO ] Flatten gal took : 8 ms
[2023-03-14 07:59:50] [INFO ] Input system was already deterministic with 158 transitions.
Finished random walk after 108 steps, including 0 resets, run visited all 1 properties in 4 ms. (steps per millisecond=27 )
FORMULA ParamProductionCell-PT-3-CTLFireability-09 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 222/222 places, 199/199 transitions.
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 3 place count 219 transition count 196
Iterating global reduction 0 with 3 rules applied. Total rules applied 6 place count 219 transition count 196
Applied a total of 6 rules in 25 ms. Remains 219 /222 variables (removed 3) and now considering 196/199 (removed 3) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 26 ms. Remains : 219/222 places, 196/199 transitions.
[2023-03-14 07:59:50] [INFO ] Flatten gal took : 12 ms
[2023-03-14 07:59:50] [INFO ] Flatten gal took : 11 ms
[2023-03-14 07:59:50] [INFO ] Input system was already deterministic with 196 transitions.
Starting structural reductions in LTL mode, iteration 0 : 222/222 places, 199/199 transitions.
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 3 place count 219 transition count 196
Iterating global reduction 0 with 3 rules applied. Total rules applied 6 place count 219 transition count 196
Applied a total of 6 rules in 8 ms. Remains 219 /222 variables (removed 3) and now considering 196/199 (removed 3) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 219/222 places, 196/199 transitions.
[2023-03-14 07:59:50] [INFO ] Flatten gal took : 20 ms
[2023-03-14 07:59:50] [INFO ] Flatten gal took : 27 ms
[2023-03-14 07:59:50] [INFO ] Input system was already deterministic with 196 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 222/222 places, 199/199 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 222 transition count 197
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 4 place count 220 transition count 197
Performed 16 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 16 Pre rules applied. Total rules applied 4 place count 220 transition count 181
Deduced a syphon composed of 16 places in 1 ms
Reduce places removed 16 places and 0 transitions.
Iterating global reduction 2 with 32 rules applied. Total rules applied 36 place count 204 transition count 181
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 39 place count 201 transition count 178
Iterating global reduction 2 with 3 rules applied. Total rules applied 42 place count 201 transition count 178
Performed 19 Post agglomeration using F-continuation condition.Transition count delta: 19
Deduced a syphon composed of 19 places in 1 ms
Reduce places removed 19 places and 0 transitions.
Iterating global reduction 2 with 38 rules applied. Total rules applied 80 place count 182 transition count 159
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 82 place count 181 transition count 158
Applied a total of 82 rules in 46 ms. Remains 181 /222 variables (removed 41) and now considering 158/199 (removed 41) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 46 ms. Remains : 181/222 places, 158/199 transitions.
[2023-03-14 07:59:50] [INFO ] Flatten gal took : 9 ms
[2023-03-14 07:59:50] [INFO ] Flatten gal took : 9 ms
[2023-03-14 07:59:50] [INFO ] Input system was already deterministic with 158 transitions.
Finished random walk after 161 steps, including 0 resets, run visited all 1 properties in 18 ms. (steps per millisecond=8 )
FORMULA ParamProductionCell-PT-3-CTLFireability-12 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 222/222 places, 199/199 transitions.
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 3 place count 219 transition count 196
Iterating global reduction 0 with 3 rules applied. Total rules applied 6 place count 219 transition count 196
Applied a total of 6 rules in 8 ms. Remains 219 /222 variables (removed 3) and now considering 196/199 (removed 3) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 219/222 places, 196/199 transitions.
[2023-03-14 07:59:50] [INFO ] Flatten gal took : 25 ms
[2023-03-14 07:59:50] [INFO ] Flatten gal took : 10 ms
[2023-03-14 07:59:50] [INFO ] Input system was already deterministic with 196 transitions.
Starting structural reductions in LTL mode, iteration 0 : 222/222 places, 199/199 transitions.
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 2 place count 220 transition count 197
Iterating global reduction 0 with 2 rules applied. Total rules applied 4 place count 220 transition count 197
Applied a total of 4 rules in 6 ms. Remains 220 /222 variables (removed 2) and now considering 197/199 (removed 2) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 220/222 places, 197/199 transitions.
[2023-03-14 07:59:50] [INFO ] Flatten gal took : 25 ms
[2023-03-14 07:59:50] [INFO ] Flatten gal took : 21 ms
[2023-03-14 07:59:50] [INFO ] Input system was already deterministic with 197 transitions.
Starting structural reductions in LTL mode, iteration 0 : 222/222 places, 199/199 transitions.
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 3 place count 219 transition count 196
Iterating global reduction 0 with 3 rules applied. Total rules applied 6 place count 219 transition count 196
Applied a total of 6 rules in 6 ms. Remains 219 /222 variables (removed 3) and now considering 196/199 (removed 3) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 219/222 places, 196/199 transitions.
[2023-03-14 07:59:50] [INFO ] Flatten gal took : 8 ms
[2023-03-14 07:59:50] [INFO ] Flatten gal took : 23 ms
[2023-03-14 07:59:50] [INFO ] Input system was already deterministic with 196 transitions.
[2023-03-14 07:59:50] [INFO ] Flatten gal took : 12 ms
[2023-03-14 07:59:50] [INFO ] Flatten gal took : 10 ms
[2023-03-14 07:59:50] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 17 ms.
[2023-03-14 07:59:50] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 222 places, 199 transitions and 820 arcs took 2 ms.
Total runtime 4972 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT ParamProductionCell-PT-3
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability
FORMULA ParamProductionCell-PT-3-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-3-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-3-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-3-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-3-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-3-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-3-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-3-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-3-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-3-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-3-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-3-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-3-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-3-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678780909282
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 10 (type EXCL) for 9 ParamProductionCell-PT-3-CTLFireability-03
lola: time limit : 149 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 10 (type EXCL) for ParamProductionCell-PT-3-CTLFireability-03
lola: result : true
lola: markings : 276
lola: fired transitions : 828
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 4 (type EXCL) for 3 ParamProductionCell-PT-3-CTLFireability-01
lola: time limit : 156 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 4 (type EXCL) for ParamProductionCell-PT-3-CTLFireability-01
lola: result : false
lola: markings : 89154
lola: fired transitions : 401740
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 56 (type EXCL) for 39 ParamProductionCell-PT-3-CTLFireability-15
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: FINISHED task # 56 (type EXCL) for ParamProductionCell-PT-3-CTLFireability-15
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 54 (type EXCL) for 39 ParamProductionCell-PT-3-CTLFireability-15
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: FINISHED task # 54 (type EXCL) for ParamProductionCell-PT-3-CTLFireability-15
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 52 (type EXCL) for 39 ParamProductionCell-PT-3-CTLFireability-15
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: FINISHED task # 52 (type EXCL) for ParamProductionCell-PT-3-CTLFireability-15
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 39 ParamProductionCell-PT-3-CTLFireability-15
lola: time limit : 299 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-3-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-03: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-15: CONJ 0 0 1 0 8 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 5/299 3/32 ParamProductionCell-PT-3-CTLFireability-15 484177 m, 96835 m/sec, 2186754 t fired, .
Time elapsed: 6 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-3-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-03: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-15: CONJ 0 0 1 0 8 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 10/299 5/32 ParamProductionCell-PT-3-CTLFireability-15 942069 m, 91578 m/sec, 4775458 t fired, .
Time elapsed: 11 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-3-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-03: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-15: CONJ 0 0 1 0 8 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 15/299 7/32 ParamProductionCell-PT-3-CTLFireability-15 1378401 m, 87266 m/sec, 7433028 t fired, .
Time elapsed: 16 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 42 (type EXCL) for ParamProductionCell-PT-3-CTLFireability-15
lola: result : true
lola: markings : 1459318
lola: fired transitions : 8719516
lola: time used : 17.000000
lola: memory pages used : 7
lola: LAUNCH task # 37 (type EXCL) for 36 ParamProductionCell-PT-3-CTLFireability-14
lola: time limit : 325 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for ParamProductionCell-PT-3-CTLFireability-14
lola: result : true
lola: markings : 142590
lola: fired transitions : 365924
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 33 ParamProductionCell-PT-3-CTLFireability-13
lola: time limit : 358 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-3-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-03: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-14: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 2/358 2/32 ParamProductionCell-PT-3-CTLFireability-13 255411 m, 51082 m/sec, 950315 t fired, .
Time elapsed: 21 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-3-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-03: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-14: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 7/358 4/32 ParamProductionCell-PT-3-CTLFireability-13 889910 m, 126899 m/sec, 3748085 t fired, .
Time elapsed: 26 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-3-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-03: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-14: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 12/358 7/32 ParamProductionCell-PT-3-CTLFireability-13 1439542 m, 109926 m/sec, 6548392 t fired, .
Time elapsed: 31 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 34 (type EXCL) for ParamProductionCell-PT-3-CTLFireability-13
lola: result : false
lola: markings : 1459318
lola: fired transitions : 7358786
lola: time used : 13.000000
lola: memory pages used : 7
lola: LAUNCH task # 31 (type EXCL) for 30 ParamProductionCell-PT-3-CTLFireability-11
lola: time limit : 396 sec
lola: memory limit: 32 pages
lola: FINISHED task # 31 (type EXCL) for ParamProductionCell-PT-3-CTLFireability-11
lola: result : false
lola: markings : 209
lola: fired transitions : 215
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 28 (type EXCL) for 27 ParamProductionCell-PT-3-CTLFireability-10
lola: time limit : 446 sec
lola: memory limit: 32 pages
lola: FINISHED task # 28 (type EXCL) for ParamProductionCell-PT-3-CTLFireability-10
lola: result : true
lola: markings : 696
lola: fired transitions : 1022
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 ParamProductionCell-PT-3-CTLFireability-07
lola: time limit : 509 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-3-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-03: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-10: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-11: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-13: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-14: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 4/509 2/32 ParamProductionCell-PT-3-CTLFireability-07 293694 m, 58738 m/sec, 1740435 t fired, .
Time elapsed: 36 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 22 (type EXCL) for ParamProductionCell-PT-3-CTLFireability-07
lola: result : true
lola: markings : 588454
lola: fired transitions : 3867707
lola: time used : 8.000000
lola: memory pages used : 3
lola: LAUNCH task # 19 (type EXCL) for 18 ParamProductionCell-PT-3-CTLFireability-06
lola: time limit : 593 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-3-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-03: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-07: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-10: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-11: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-13: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-14: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 1/593 1/32 ParamProductionCell-PT-3-CTLFireability-06 159801 m, 31960 m/sec, 501025 t fired, .
Time elapsed: 41 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-3-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-03: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-07: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-10: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-11: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-13: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-14: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 6/593 4/32 ParamProductionCell-PT-3-CTLFireability-06 800523 m, 128144 m/sec, 3465321 t fired, .
Time elapsed: 46 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-3-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-03: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-07: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-10: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-11: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-13: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-14: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 11/593 6/32 ParamProductionCell-PT-3-CTLFireability-06 1136357 m, 67166 m/sec, 6313839 t fired, .
Time elapsed: 51 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-3-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-03: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-07: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-10: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-11: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-13: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-14: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 16/593 7/32 ParamProductionCell-PT-3-CTLFireability-06 1385826 m, 49893 m/sec, 9164004 t fired, .
Time elapsed: 56 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-3-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-03: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-07: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-10: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-11: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-13: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-14: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 21/593 7/32 ParamProductionCell-PT-3-CTLFireability-06 1414193 m, 5673 m/sec, 11948047 t fired, .
Time elapsed: 61 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-3-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-03: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-07: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-10: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-11: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-13: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-14: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 26/593 7/32 ParamProductionCell-PT-3-CTLFireability-06 1428552 m, 2871 m/sec, 14771891 t fired, .
Time elapsed: 66 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-3-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-03: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-07: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-10: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-11: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-13: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-14: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 31/593 7/32 ParamProductionCell-PT-3-CTLFireability-06 1436472 m, 1584 m/sec, 17595355 t fired, .
Time elapsed: 71 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-3-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-03: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-07: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-10: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-11: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-13: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-14: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 36/593 7/32 ParamProductionCell-PT-3-CTLFireability-06 1458629 m, 4431 m/sec, 20427283 t fired, .
Time elapsed: 76 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 19 (type EXCL) for ParamProductionCell-PT-3-CTLFireability-06
lola: result : false
lola: markings : 1459318
lola: fired transitions : 21538404
lola: time used : 38.000000
lola: memory pages used : 7
lola: LAUNCH task # 16 (type EXCL) for 15 ParamProductionCell-PT-3-CTLFireability-05
lola: time limit : 704 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-3-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-03: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-06: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-07: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-10: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-11: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-13: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-14: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 3/704 1/32 ParamProductionCell-PT-3-CTLFireability-05 215035 m, 43007 m/sec, 1416262 t fired, .
Time elapsed: 81 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-3-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-03: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-06: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-07: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-10: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-11: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-13: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-14: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 8/704 3/32 ParamProductionCell-PT-3-CTLFireability-05 568510 m, 70695 m/sec, 3952867 t fired, .
Time elapsed: 86 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-3-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-03: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-06: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-07: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-10: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-11: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-13: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-14: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 13/704 5/32 ParamProductionCell-PT-3-CTLFireability-05 898617 m, 66021 m/sec, 6499413 t fired, .
Time elapsed: 91 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-3-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-03: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-06: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-07: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-10: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-11: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-13: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-14: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 18/704 6/32 ParamProductionCell-PT-3-CTLFireability-05 1222064 m, 64689 m/sec, 9033721 t fired, .
Time elapsed: 96 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-3-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-03: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-06: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-07: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-10: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-11: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-13: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-14: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 23/704 7/32 ParamProductionCell-PT-3-CTLFireability-05 1457626 m, 47112 m/sec, 11490377 t fired, .
Time elapsed: 101 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 16 (type EXCL) for ParamProductionCell-PT-3-CTLFireability-05
lola: result : false
lola: markings : 1459318
lola: fired transitions : 11786986
lola: time used : 23.000000
lola: memory pages used : 7
lola: LAUNCH task # 7 (type EXCL) for 6 ParamProductionCell-PT-3-CTLFireability-02
lola: time limit : 874 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-3-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-03: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-05: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-06: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-07: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-10: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-11: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-13: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-14: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/874 4/32 ParamProductionCell-PT-3-CTLFireability-02 723446 m, 144689 m/sec, 2621013 t fired, .
Time elapsed: 106 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 7 (type EXCL) for ParamProductionCell-PT-3-CTLFireability-02
lola: result : false
lola: markings : 921229
lola: fired transitions : 3828010
lola: time used : 7.000000
lola: memory pages used : 5
lola: LAUNCH task # 25 (type EXCL) for 24 ParamProductionCell-PT-3-CTLFireability-08
lola: time limit : 1164 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for ParamProductionCell-PT-3-CTLFireability-08
lola: result : true
lola: markings : 372189
lola: fired transitions : 1887071
lola: time used : 2.000000
lola: memory pages used : 2
lola: LAUNCH task # 1 (type EXCL) for 0 ParamProductionCell-PT-3-CTLFireability-00
lola: time limit : 1745 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-3-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-02: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-03: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-05: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-06: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-07: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-08: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-10: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-11: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-13: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-14: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-3-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ParamProductionCell-PT-3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 1/1745 1/32 ParamProductionCell-PT-3-CTLFireability-00 79824 m, 15964 m/sec, 210700 t fired, .
Time elapsed: 111 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 1 (type EXCL) for ParamProductionCell-PT-3-CTLFireability-00
lola: result : false
lola: markings : 305925
lola: fired transitions : 2399815
lola: time used : 4.000000
lola: memory pages used : 2
lola: LAUNCH task # 13 (type EXCL) for 12 ParamProductionCell-PT-3-CTLFireability-04
lola: time limit : 3486 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-3-CTLFireability-00: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-02: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-03: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-05: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-06: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-07: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-08: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-10: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-11: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-13: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-14: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-3-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 2/3486 2/32 ParamProductionCell-PT-3-CTLFireability-04 302897 m, 60579 m/sec, 1114371 t fired, .
Time elapsed: 116 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 13 (type EXCL) for ParamProductionCell-PT-3-CTLFireability-04
lola: result : false
lola: markings : 573475
lola: fired transitions : 2435244
lola: time used : 4.000000
lola: memory pages used : 3
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-3-CTLFireability-00: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-02: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-03: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-04: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-05: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-06: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-07: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-08: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-10: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-11: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-13: CTL false CTL model checker
ParamProductionCell-PT-3-CTLFireability-14: CTL true CTL model checker
ParamProductionCell-PT-3-CTLFireability-15: CONJ true CONJ
Time elapsed: 118 secs. Pages in use: 7
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ParamProductionCell-PT-3"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is ParamProductionCell-PT-3, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r263-smll-167863538200386"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ParamProductionCell-PT-3.tgz
mv ParamProductionCell-PT-3 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;