MCC'2023- Execution of r262-smll-167863537400495

About the Execution of LoLA for PermAdmissibility-COL-20

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
3319.647	457055.00	462882.00	1349.30	TFTFTTTTTTTFTTTT	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r262-smll-16786353
Waiting for the VM to be ready (probing ssh)
....................................................
==============================
Generated by BenchKit 2-5348
Executing tool lola
Input is PermAdmissibility-COL-20, examination
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r262-smll-167863537400495
====================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 544K
-rw-r--r-- 1 mcc users 8.8K Feb 26 01:22 CTLCardinal
-rw-r--r-- 1 mcc users 101K Feb 26 01:22 CTLCardinal
-rw-r--r-- 1 mcc users 5.0K Feb 26 01:20 CTLFireabil
-rw-r--r-- 1 mcc users 38K Feb 26 01:20 CTLFireabil
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericProp
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericProp
-rw-r--r-- 1 mcc users 3.3K Feb 25 16:31 LTLCardinal
-rw-r--r-- 1 mcc users 22K Feb 25 16:31 LTLCardinal
-rw-r--r-- 1 mcc users 2.5K Feb 25 16:31 LTLFireabil
-rw-r--r-- 1 mcc users 18K Feb 25 16:31 LTLFireabil
-rw-r--r-- 1 mcc users 13K Feb 26 01:27 Reachabilit
-rw-r--r-- 1 mcc users 141K Feb 26 01:27 Reachabilit
-rw-r--r-- 1 mcc users 8.1K Feb 26 01:26 Reachabilit
-rw-r--r-- 1 mcc users 62K Feb 26 01:26 Reachabilit
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:31 UpperBounds
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:31 UpperBounds
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_pt
-rw-r--r-- 1 mcc users 3 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 54K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result
FORMULA_NAME PermAdmissibility-COL-20-ReachabilityFi
FORMULA_NAME PermAdmissibility-COL-20-ReachabilityFi
FORMULA_NAME PermAdmissibility-COL-20-ReachabilityFi
FORMULA_NAME PermAdmissibility-COL-20-ReachabilityFi
FORMULA_NAME PermAdmissibility-COL-20-ReachabilityFi
FORMULA_NAME PermAdmissibility-COL-20-ReachabilityFi
FORMULA_NAME PermAdmissibility-COL-20-ReachabilityFi
FORMULA_NAME PermAdmissibility-COL-20-ReachabilityFi
FORMULA_NAME PermAdmissibility-COL-20-ReachabilityFi
FORMULA_NAME PermAdmissibility-COL-20-ReachabilityFi
FORMULA_NAME PermAdmissibility-COL-20-ReachabilityFi
FORMULA_NAME PermAdmissibility-COL-20-ReachabilityFi
FORMULA_NAME PermAdmissibility-COL-20-ReachabilityFi
FORMULA_NAME PermAdmissibility-COL-20-ReachabilityFi
FORMULA_NAME PermAdmissibility-COL-20-ReachabilityFi
FORMULA_NAME PermAdmissibility-COL-20-ReachabilityFi

=== Now, execution of the tool begins

BK_START 1678928494934

bash -c /home/mcc/BenchKit/BenchKit_head.sh
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=ReachabilityFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=PermAdmissibility-COL-20
Not applying reductions.
Model is COL
ReachabilityFireability COL
starting LoLA
BK_INPUT PermAdmissibility-COL-20
BK_EXAMINATION: ReachabilityFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
ReachabilityFireability

FORMULA PermAdmissibility-COL-20-ReachabilityFireability-01

FORMULA PermAdmissibility-COL-20-ReachabilityFireability-02

FORMULA PermAdmissibility-COL-20-ReachabilityFireability-05

FORMULA PermAdmissibility-COL-20-ReachabilityFireability-00

FORMULA PermAdmissibility-COL-20-ReachabilityFireability-03

FORMULA PermAdmissibility-COL-20-ReachabilityFireability-14

FORMULA PermAdmissibility-COL-20-ReachabilityFireability-13

FORMULA PermAdmissibility-COL-20-ReachabilityFireability-09

FORMULA PermAdmissibility-COL-20-ReachabilityFireability-10

FORMULA PermAdmissibility-COL-20-ReachabilityFireability-15

FORMULA PermAdmissibility-COL-20-ReachabilityFireability-08

FORMULA PermAdmissibility-COL-20-ReachabilityFireability-12

FORMULA PermAdmissibility-COL-20-ReachabilityFireability-11

FORMULA PermAdmissibility-COL-20-ReachabilityFireability-07

FORMULA PermAdmissibility-COL-20-ReachabilityFireability-04

FORMULA PermAdmissibility-COL-20-ReachabilityFireability-06

BK_STOP 1678928951989

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.p
lola: reading pnml
lola: PNML file contains High-Level net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pn
lola: Reading HL formula in XML format (--xmlformu
lola: reading formula from /home/mcc/execution/Rea
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:15
lola: rewrite Frontend/Parser/formula_rewrite.k:14
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:72
lola: rewrite Frontend/Parser/formula_rewrite.k:78
lola: LAUNCH INITIAL
lola: TR BINDINGS
lola: LAUNCH task # 5 (type SKEL/CNST) for
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:72
lola: rewrite Frontend/Parser/formula_rewrite.k:78
lola: rewrite Frontend/Parser/formula_rewrite.k:72
lola: rewrite Frontend/Parser/formula_rewrite.k:78
lola: rewrite Frontend/Parser/formula_rewrite.k:72
lola: rewrite Frontend/Parser/formula_rewrite.k:78
lola: FINISHED task # 5 (type SKEL/CNST)
lola: result : false
lola: LAUNCH task # 56 (type SKEL/FNDP) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 58 (type SKEL/EQUN) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 60 (type SKEL/SRCH) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 61 (type SKEL/SRCH) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: FINISHED task # 60 (type SKEL/SRCH)
lola: result : true
lola: markings : 7
lola: fired transitions : 6
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 56 (type FNDP) for
lola: CANCELED task # 58 (type EQUN) for
lola: CANCELED task # 61 (type SRCH) for
lola: LAUNCH task # 49 (type SKEL/FNDP) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 50 (type SKEL/EQUN) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 63 (type SKEL/SRCH) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 64 (type SKEL/SRCH) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: FINISHED task # 56 (type SKEL/FNDP)
lola: result : true
lola: fired transitions : 5
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: FINISHED task # 49 (type SKEL/FNDP)
lola: result : true
lola: fired transitions : 7
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 50 (type EQUN) for
lola: CANCELED task # 63 (type SRCH) for
lola: CANCELED task # 64 (type SRCH) for
lola: TR BINDINGS DONE
lola: Places: 208, Transitions: 1024
lola: LAUNCH task # 99 (type SKEL/FNDP) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 100 (type SKEL/EQUN)
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: LAUNCH task # 102 (type SKEL/SRCH)
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 103 (type SKEL/SRCH)
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 103 (type SKEL/SRCH)
lola: result : true
lola: markings : 83
lola: fired transitions : 82
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 99 (type FNDP) for
lola: CANCELED task # 100 (type EQUN) for
lola: CANCELED task # 102 (type SRCH) for
lola: LAUNCH task # 53 (type SKEL/FNDP) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 54 (type SKEL/EQUN) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 74 (type SKEL/SRCH) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 75 (type SKEL/SRCH) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 99 (type SKEL/FNDP)
lola: result : true
lola: fired transitions : 5
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 100 (type SKEL/EQUN)
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:72
lola: rewrite Frontend/Parser/formula_rewrite.k:78
lola: FINISHED task # 74 (type SKEL/SRCH)
lola: result : true
lola: markings : 14
lola: fired transitions : 13
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 53 (type FNDP) for
lola: CANCELED task # 54 (type EQUN) for
lola: CANCELED task # 75 (type SRCH) for
lola: LAUNCH task # 67 (type SKEL/FNDP) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 68 (type SKEL/EQUN) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 70 (type SKEL/SRCH) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 71 (type SKEL/SRCH) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: FINISHED task # 53 (type SKEL/FNDP)
lola: result : true
lola: fired transitions : 12
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/R
sara: try reading problem file /home/mcc/execution/R
lola: FINISHED task # 67 (type SKEL/FNDP)
lola: result : true
lola: fired transitions : 13
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 68 (type EQUN) for
lola: CANCELED task # 70 (type SRCH) for
lola: CANCELED task # 71 (type SRCH) for
lola: LAUNCH task # 80 (type SKEL/FNDP) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 81 (type SKEL/EQUN) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 83 (type SKEL/SRCH) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 84 (type SKEL/SRCH) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: place or transition ordering is non-determinis
sara: try reading problem file /home/mcc/execution/R

sara: try reading problem file /home/mcc/execution/R

sara: place or transition ordering is non-determinis
lola: rewrite Frontend/Parser/formula_rewrite.k:71

lola: FINISHED task # 80 (type SKEL/FNDP)
lola: result : true
lola: fired transitions : 14
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 58 (type SKEL/EQUN)
lola: result : true
lola: FINISHED task # 83 (type SKEL/SRCH)
lola: result : true
lola: markings : 16
lola: fired transitions : 15
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 84 (type SKEL/SRCH)
lola: result : true
lola: markings : 282
lola: fired transitions : 281
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 50 (type SKEL/EQUN)
lola: result : true
lola: CANCELED task # 81 (type EQUN) for
lola: LAUNCH task # 86 (type SKEL/FNDP) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 87 (type SKEL/EQUN) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 89 (type SKEL/SRCH) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 90 (type SKEL/SRCH) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: try reading problem file /home/mcc/execution/R
lola: FINISHED task # 89 (type SKEL/SRCH)
lola: result : true
lola: markings : 16
lola: fired transitions : 15
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 86 (type FNDP) for
lola: CANCELED task # 87 (type EQUN) for
lola: CANCELED task # 90 (type SRCH) for
lola: LAUNCH task # 92 (type SKEL/FNDP) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 93 (type SKEL/EQUN) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 95 (type SKEL/SRCH) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 96 (type SKEL/SRCH) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 68 (type SKEL/EQUN)
lola: result : true

lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: FINISHED task # 54 (type SKEL/EQUN)
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: FINISHED task # 86 (type SKEL/FNDP)
lola: result : true
lola: fired transitions : 14
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/R
lola: @ trans switch9
sara: try reading problem file /home/mcc/execution/R
lola: @ trans switch3
lola: @ trans switch4
lola: FINISHED task # 96 (type SKEL/SRCH)
lola: result : true
lola: markings : 282
lola: fired transitions : 281
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 92 (type FNDP) for
lola: CANCELED task # 93 (type EQUN) for
lola: CANCELED task # 95 (type SRCH) for

lola: @ trans display4
lola: FINISHED task # 93 (type SKEL/EQUN)
lola: result : unknown
lola: FINISHED task # 81 (type SKEL/EQUN)
lola: result : true
lola: FINISHED task # 87 (type SKEL/EQUN)
lola: result : true
lola: FINISHED task # 92 (type SKEL/FNDP)
lola: result : true
lola: fired transitions : 14
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: @ trans display3
lola: @ trans switch7
lola: @ trans switch8
lola: @ trans switch11
lola: @ trans switch10
lola: @ trans switch2
lola: @ trans switch1
lola: @ trans switch5
lola: @ trans switch12
lola: @ trans display2
lola: @ trans display1
lola: @ trans switch6
FINISHED FORMULA: CATEGORY
PermAdmissibility-COL-20-ReachabilityFireability-01: INITIAL

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lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 112 (type EQUN) for
lola: LAUNCH task # 121 (type EXCL) for 0
lola: time limit : 449 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 117 (type FNDP) for 0
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 118 (type EQUN) for 0
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 120 (type SRCH) for 0
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: try reading problem file /home/mcc/execution/R
sara: place or transition ordering is non-determinis
lola: rewrite Frontend/Parser/formula_rewrite.k:72
lola: rewrite Frontend/Parser/formula_rewrite.k:78

lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: FINISHED task # 112 (type EQUN) for
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:72
lola: rewrite Frontend/Parser/formula_rewrite.k:78
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:72
lola: rewrite Frontend/Parser/formula_rewrite.k:78
lola: FINISHED task # 120 (type SRCH) for
lola: result : true
lola: markings : 16
lola: fired transitions : 15
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:72
lola: rewrite Frontend/Parser/formula_rewrite.k:78
lola: rewrite Frontend/Parser/formula_rewrite.k:72
lola: rewrite Frontend/Parser/formula_rewrite.k:78
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: CANCELED task # 117 (type FNDP) for
lola: CANCELED task # 118 (type EQUN) for
lola: CANCELED task # 121 (type EXCL) for
lola: LAUNCH task # 153 (type EXCL) for 9
lola: time limit : 524 sec
lola: memory limit: 32 pages
sara: try reading problem file /home/mcc/execution/R
lola: LAUNCH task # 126 (type FNDP) for 39
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 134 (type EQUN) for 39
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: LAUNCH task # 136 (type SRCH) for 39
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: FINISHED task # 117 (type FNDP) for
lola: result : true
lola: fired transitions : 14
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
sara: try reading problem file /home/mcc/execution/R
lola: FINISHED task # 153 (type EXCL) for
lola: result : true
lola: markings : 21
lola: fired transitions : 20
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: LAUNCH task # 150 (type EXCL) for 42
lola: time limit : 314 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:72
lola: rewrite Frontend/Parser/formula_rewrite.k:78
lola: rewrite Frontend/Parser/formula_rewrite.k:72
lola: rewrite Frontend/Parser/formula_rewrite.k:78
lola: rewrite Frontend/Parser/formula_rewrite.k:72
lola: rewrite Frontend/Parser/formula_rewrite.k:78
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
sara: place or transition ordering is non-determinis
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: FINISHED task # 150 (type EXCL) for
lola: result : true
lola: markings : 122
lola: fired transitions : 121
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 164 (type EXCL) for 27
lola: time limit : 285 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: FINISHED task # 126 (type FNDP) for
lola: result : true
lola: fired transitions : 20
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: place or transition ordering is non-determinis
lola: CANCELED task # 134 (type EQUN) for
lola: CANCELED task # 136 (type SRCH) for
lola: LAUNCH task # 131 (type FNDP) for 30
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 138 (type EQUN) for 30
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 167 (type SRCH) for 30
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 136 (type SRCH) for
lola: result : true
lola: markings : 22
lola: fired transitions : 21
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: FINISHED task # 164 (type EXCL) for
lola: result : true
lola: markings : 282
lola: fired transitions : 281
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 188 (type EXCL) for 45
lola: time limit : 393 sec
lola: memory limit: 32 pages
lola: FINISHED task # 131 (type FNDP) for
lola: result : true
lola: fired transitions : 24
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 138 (type EQUN) for
lola: CANCELED task # 167 (type SRCH) for
lola: LAUNCH task # 191 (type FNDP) for 24
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 192 (type EQUN) for 24
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 194 (type SRCH) for 24
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: FINISHED task # 188 (type EXCL) for
lola: result : true
lola: markings : 282
lola: fired transitions : 281
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 171 (type EXCL) for 33
lola: time limit : 524 sec
lola: memory limit: 32 pages
lola: FINISHED task # 194 (type SRCH) for
lola: result : true
lola: markings : 14
lola: fired transitions : 13
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 191 (type FNDP) for
lola: CANCELED task # 192 (type EQUN) for
lola: LAUNCH task # 123 (type FNDP) for 36
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 127 (type EQUN) for 36
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 154 (type SRCH) for 36
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 191 (type FNDP) for
lola: result : true
lola: fired transitions : 12
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: FINISHED task # 154 (type SRCH) for
lola: result : true
lola: markings : 40
lola: fired transitions : 39
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 123 (type FNDP) for
lola: CANCELED task # 127 (type EQUN) for
lola: LAUNCH task # 161 (type FNDP) for 21
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 172 (type EQUN) for 21
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 176 (type SRCH) for 21
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 123 (type FNDP) for
lola: result : unknown
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: FINISHED task # 171 (type EXCL) for
lola: result : true
lola: markings : 242
lola: fired transitions : 241
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 166 (type EXCL) for 12
lola: time limit : 1048 sec
lola: memory limit: 32 pages
sara: try reading problem file /home/mcc/execution/R
sara: place or transition ordering is non-determinis
lola: FINISHED task # 176 (type SRCH) for
lola: result : true
lola: markings : 22
lola: fired transitions : 21
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 161 (type FNDP) for
lola: CANCELED task # 172 (type EQUN) for
lola: LAUNCH task # 169 (type FNDP) for 18
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 174 (type EQUN) for 18
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 183 (type SRCH) for 18
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 166 (type EXCL) for
lola: result : true
lola: markings : 162
lola: fired transitions : 161
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 184 (type EXCL) for 18
lola: time limit : 3144 sec
lola: memory limit: 32 pages

lola: rewrite Frontend/Parser/formula_rewrite.k:71
lola: FINISHED task # 127 (type EQUN) for
lola: result : true
lola: FINISHED task # 161 (type FNDP) for
lola: result : true
lola: fired transitions : 20
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 183 (type SRCH) for
lola: result : true
lola: markings : 98
lola: fired transitions : 97
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 169 (type FNDP) for
lola: CANCELED task # 174 (type EQUN) for
lola: CANCELED task # 184 (type EXCL) for
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY
PermAdmissibility-COL-20-ReachabilityFireability-00:
PermAdmissibility-COL-20-ReachabilityFireability-01: INITIAL
PermAdmissibility-COL-20-ReachabilityFireability-02:
PermAdmissibility-COL-20-ReachabilityFireability-03:
PermAdmissibility-COL-20-ReachabilityFireability-04:
PermAdmissibility-COL-20-ReachabilityFireability-05:
PermAdmissibility-COL-20-ReachabilityFireability-06:
PermAdmissibility-COL-20-ReachabilityFireability-07:
PermAdmissibility-COL-20-ReachabilityFireability-08:
PermAdmissibility-COL-20-ReachabilityFireability-09:
PermAdmissibility-COL-20-ReachabilityFireability-10:
PermAdmissibility-COL-20-ReachabilityFireability-11:
PermAdmissibility-COL-20-ReachabilityFireability-12:
PermAdmissibility-COL-20-ReachabilityFireability-13:
PermAdmissibility-COL-20-ReachabilityFireability-14:
PermAdmissibility-COL-20-ReachabilityFireability-15:

Time elapsed: 456 secs. Pages in use: 3
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................................................................................................................................................................................................................................................................................................................................... ======================================= is ReachabilityFireability ================= ity.txt ity.xml ity.txt ity.xml ertiesDefinition.xml ertiesVerdict.xml ity.txt ity.xml ity.txt ity.xml yCardinality.txt yCardinality.xml yFireability.txt yFireability.xml .txt .xml (invocation template) vector(from text file) reability-00 reability-01 reability-02 reability-03 reability-04 reability-05 reability-06 reability-07 reability-08 reability-09 reability-10 reability-11 reability-12 reability-13 reability-14 reability-15 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT nml ml la) chabilityFireability.xml 6 7 1 1 7 3 PermAdmissibility-COL-20-ReachabilityFireability-01 1 1 1 1 1 1 1 1 1 1 1 1 7 1 7 1 7 for PermAdmissibility-COL-20-ReachabilityFireability-01 15 PermAdmissibility-COL-20-ReachabilityFireability-05 15 PermAdmissibility-COL-20-ReachabilityFireability-05 15 PermAdmissibility-COL-20-ReachabilityFireability-05 15 PermAdmissibility-COL-20-ReachabilityFireability-05 1 for PermAdmissibility-COL-20-ReachabilityFireability-05 PermAdmissibility-COL-20-ReachabilityFireability-05 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-05 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-05 (obsolete) 12 PermAdmissibility-COL-20-ReachabilityFireability-04 12 PermAdmissibility-COL-20-ReachabilityFireability-04 12 PermAdmissibility-COL-20-ReachabilityFireability-04 12 PermAdmissibility-COL-20-ReachabilityFireability-04 1 1 1 1 1 1 1 1 1 1 1 1 1 1 for PermAdmissibility-COL-20-ReachabilityFireability-05 1 1 1 for PermAdmissibility-COL-20-ReachabilityFireability-04 PermAdmissibility-COL-20-ReachabilityFireability-04 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-04 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-04 (obsolete) 42 PermAdmissibility-COL-20-ReachabilityFireability-14 for 42 PermAdmissibility-COL-20-ReachabilityFireability-14 1 for 42 PermAdmissibility-COL-20-ReachabilityFireability-14 for 42 PermAdmissibility-COL-20-ReachabilityFireability-14 for PermAdmissibility-COL-20-ReachabilityFireability-14 PermAdmissibility-COL-20-ReachabilityFireability-14 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-14 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-14 (obsolete) 33 PermAdmissibility-COL-20-ReachabilityFireability-11 33 PermAdmissibility-COL-20-ReachabilityFireability-11 33 PermAdmissibility-COL-20-ReachabilityFireability-11 33 PermAdmissibility-COL-20-ReachabilityFireability-11 for PermAdmissibility-COL-20-ReachabilityFireability-14 for PermAdmissibility-COL-20-ReachabilityFireability-14 1 7 for PermAdmissibility-COL-20-ReachabilityFireability-11 PermAdmissibility-COL-20-ReachabilityFireability-11 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-11 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-11 (obsolete) 6 PermAdmissibility-COL-20-ReachabilityFireability-02 6 PermAdmissibility-COL-20-ReachabilityFireability-02 6 PermAdmissibility-COL-20-ReachabilityFireability-02 6 PermAdmissibility-COL-20-ReachabilityFireability-02 1 for PermAdmissibility-COL-20-ReachabilityFireability-11 eachabilityFireability-50.sara. eachabilityFireability-58.sara. for PermAdmissibility-COL-20-ReachabilityFireability-02 PermAdmissibility-COL-20-ReachabilityFireability-02 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-02 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-02 (obsolete) 27 PermAdmissibility-COL-20-ReachabilityFireability-09 27 PermAdmissibility-COL-20-ReachabilityFireability-09 27 PermAdmissibility-COL-20-ReachabilityFireability-09 27 PermAdmissibility-COL-20-ReachabilityFireability-09 tic eachabilityFireability-54.sara. eachabilityFireability-68.sara. tic 1 for PermAdmissibility-COL-20-ReachabilityFireability-09 for PermAdmissibility-COL-20-ReachabilityFireability-05 for PermAdmissibility-COL-20-ReachabilityFireability-09 for PermAdmissibility-COL-20-ReachabilityFireability-09 for PermAdmissibility-COL-20-ReachabilityFireability-04 PermAdmissibility-COL-20-ReachabilityFireability-09 (obsolete) 0 PermAdmissibility-COL-20-ReachabilityFireability-00 0 PermAdmissibility-COL-20-ReachabilityFireability-00 0 PermAdmissibility-COL-20-ReachabilityFireability-00 0 PermAdmissibility-COL-20-ReachabilityFireability-00 eachabilityFireability-81.sara. for PermAdmissibility-COL-20-ReachabilityFireability-00 PermAdmissibility-COL-20-ReachabilityFireability-00 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-00 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-00 (obsolete) 45 PermAdmissibility-COL-20-ReachabilityFireability-15 45 PermAdmissibility-COL-20-ReachabilityFireability-15 45 PermAdmissibility-COL-20-ReachabilityFireability-15 45 PermAdmissibility-COL-20-ReachabilityFireability-15 for PermAdmissibility-COL-20-ReachabilityFireability-02 1 for PermAdmissibility-COL-20-ReachabilityFireability-11 1 for PermAdmissibility-COL-20-ReachabilityFireability-00 eachabilityFireability-93.sara. eachabilityFireability-87.sara. for PermAdmissibility-COL-20-ReachabilityFireability-15 PermAdmissibility-COL-20-ReachabilityFireability-15 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-15 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-15 (obsolete) for PermAdmissibility-COL-20-ReachabilityFireability-15 for PermAdmissibility-COL-20-ReachabilityFireability-09 for PermAdmissibility-COL-20-ReachabilityFireability-00 for PermAdmissibility-COL-20-ReachabilityFireability-15 VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 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VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 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skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 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0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS VALUE PRODUCED BY false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 2 0 0 3 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 2 0 0 3 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 4 0 0 1 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 2 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 3 0 0 2 EF 0 0 0 0 3 0 0 2 STATUS places removed 1 1 1 1 PermAdmissibility-COL-20-ReachabilityFireability-02 PermAdmissibility-COL-20-ReachabilityFireability-02 PermAdmissibility-COL-20-ReachabilityFireability-02 PermAdmissibility-COL-20-ReachabilityFireability-02 1 1 1 1 1 PermAdmissibility-COL-20-ReachabilityFireability-02 PermAdmissibility-COL-20-ReachabilityFireability-02 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-02 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-02 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-05 PermAdmissibility-COL-20-ReachabilityFireability-05 PermAdmissibility-COL-20-ReachabilityFireability-05 1 PermAdmissibility-COL-20-ReachabilityFireability-05 1 1 1 1 1 PermAdmissibility-COL-20-ReachabilityFireability-02 1 1 1 1 PermAdmissibility-COL-20-ReachabilityFireability-05 PermAdmissibility-COL-20-ReachabilityFireability-05 PermAdmissibility-COL-20-ReachabilityFireability-05 PermAdmissibility-COL-20-ReachabilityFireability-05 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-00 PermAdmissibility-COL-20-ReachabilityFireability-00 PermAdmissibility-COL-20-ReachabilityFireability-00 PermAdmissibility-COL-20-ReachabilityFireability-00 eachabilityFireability-112.sara. tic 1 7 1 1 PermAdmissibility-COL-20-ReachabilityFireability-05 1 1 1 1 1 7 1 1 1 1 7 PermAdmissibility-COL-20-ReachabilityFireability-00 1 1 7 1 7 1 PermAdmissibility-COL-20-ReachabilityFireability-00 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-00 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-00 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-03 eachabilityFireability-106.sara. PermAdmissibility-COL-20-ReachabilityFireability-13 PermAdmissibility-COL-20-ReachabilityFireability-13 1 PermAdmissibility-COL-20-ReachabilityFireability-13 1 PermAdmissibility-COL-20-ReachabilityFireability-00 1 1 1 eachabilityFireability-118.sara. PermAdmissibility-COL-20-ReachabilityFireability-03 1 PermAdmissibility-COL-20-ReachabilityFireability-14 1 1 1 1 1 1 7 1 7 1 7 1 1 1 1 1 1 tic 1 1 PermAdmissibility-COL-20-ReachabilityFireability-14 PermAdmissibility-COL-20-ReachabilityFireability-09 1 1 1 1 1 1 1 PermAdmissibility-COL-20-ReachabilityFireability-13 tic PermAdmissibility-COL-20-ReachabilityFireability-13 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-13 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-10 PermAdmissibility-COL-20-ReachabilityFireability-10 PermAdmissibility-COL-20-ReachabilityFireability-10 PermAdmissibility-COL-20-ReachabilityFireability-13 1 PermAdmissibility-COL-20-ReachabilityFireability-09 PermAdmissibility-COL-20-ReachabilityFireability-15 PermAdmissibility-COL-20-ReachabilityFireability-10 PermAdmissibility-COL-20-ReachabilityFireability-10 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-10 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-08 PermAdmissibility-COL-20-ReachabilityFireability-08 PermAdmissibility-COL-20-ReachabilityFireability-08 1 PermAdmissibility-COL-20-ReachabilityFireability-15 PermAdmissibility-COL-20-ReachabilityFireability-11 PermAdmissibility-COL-20-ReachabilityFireability-08 PermAdmissibility-COL-20-ReachabilityFireability-08 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-08 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-12 PermAdmissibility-COL-20-ReachabilityFireability-12 PermAdmissibility-COL-20-ReachabilityFireability-12 PermAdmissibility-COL-20-ReachabilityFireability-08 1 PermAdmissibility-COL-20-ReachabilityFireability-12 PermAdmissibility-COL-20-ReachabilityFireability-12 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-12 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-07 PermAdmissibility-COL-20-ReachabilityFireability-07 PermAdmissibility-COL-20-ReachabilityFireability-07 PermAdmissibility-COL-20-ReachabilityFireability-12 1 PermAdmissibility-COL-20-ReachabilityFireability-11 PermAdmissibility-COL-20-ReachabilityFireability-04 eachabilityFireability-127.sara. tic PermAdmissibility-COL-20-ReachabilityFireability-07 PermAdmissibility-COL-20-ReachabilityFireability-07 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-07 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-06 PermAdmissibility-COL-20-ReachabilityFireability-06 PermAdmissibility-COL-20-ReachabilityFireability-06 PermAdmissibility-COL-20-ReachabilityFireability-04 PermAdmissibility-COL-20-ReachabilityFireability-06 1 PermAdmissibility-COL-20-ReachabilityFireability-12 PermAdmissibility-COL-20-ReachabilityFireability-07 PermAdmissibility-COL-20-ReachabilityFireability-06 PermAdmissibility-COL-20-ReachabilityFireability-06 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-06 (obsolete) PermAdmissibility-COL-20-ReachabilityFireability-06 (obsolete) VALUE PRODUCED BY EF true tandem / insertion false skeleton: preprocessing EF true tandem / insertion AG false tandem / relaxed EF true tandem / relaxed EF true findpath EF true tandem / insertion EF true tandem / insertion EF true tandem / insertion EF true tandem / relaxed EF true findpath AG false tandem / relaxed EF true tandem / insertion EF true findpath EF true tandem / relaxed EF true tandem / relaxed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PermAdmissibility-COL-20"
export BK_EXAMINATION="ReachabilityFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is PermAdmissibility-COL-20, examination is ReachabilityFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r262-smll-167863537400495"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/PermAdmissibility-COL-20.tgz
mv PermAdmissibility-COL-20 execution
cd execution
if [ "ReachabilityFireability" = "ReachabilityDeadlock" ] || [ "ReachabilityFireability" = "UpperBounds" ] || [ "ReachabilityFireability" = "QuasiLiveness" ] || [ "ReachabilityFireability" = "StableMarking" ] || [ "ReachabilityFireability" = "Liveness" ] || [ "ReachabilityFireability" = "OneSafe" ] || [ "ReachabilityFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityFireability" = "ReachabilityDeadlock" ] || [ "ReachabilityFireability" = "QuasiLiveness" ] || [ "ReachabilityFireability" = "StableMarking" ] || [ "ReachabilityFireability" = "Liveness" ] || [ "ReachabilityFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;