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Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r262-smll-167863537200402
Last Updated
May 14, 2023

About the Execution of LoLA for ParamProductionCell-PT-5

Execution Summary
Max Memory
Used (MB)		 Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
956.067 95571.00 96620.00 380.40 TTFFFFTTTTFFTFTF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r262-smll-167863537200402.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is ParamProductionCell-PT-5, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r262-smll-167863537200402
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 656K
-rw-r--r-- 1 mcc users 7.2K Feb 26 17:17 CTLCardinality.txt
-rw-r--r-- 1 mcc users 62K Feb 26 17:17 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.4K Feb 26 17:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 38K Feb 26 17:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.2K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.2K Feb 25 16:30 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:30 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K Feb 25 16:30 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 16:30 LTLFireability.xml
-rw-r--r-- 1 mcc users 19K Feb 26 17:19 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 166K Feb 26 17:19 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 26 17:18 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 66K Feb 26 17:18 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 25 16:30 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:30 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 174K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ParamProductionCell-PT-5-CTLFireability-00
FORMULA_NAME ParamProductionCell-PT-5-CTLFireability-01
FORMULA_NAME ParamProductionCell-PT-5-CTLFireability-02
FORMULA_NAME ParamProductionCell-PT-5-CTLFireability-03
FORMULA_NAME ParamProductionCell-PT-5-CTLFireability-04
FORMULA_NAME ParamProductionCell-PT-5-CTLFireability-05
FORMULA_NAME ParamProductionCell-PT-5-CTLFireability-06
FORMULA_NAME ParamProductionCell-PT-5-CTLFireability-07
FORMULA_NAME ParamProductionCell-PT-5-CTLFireability-08
FORMULA_NAME ParamProductionCell-PT-5-CTLFireability-09
FORMULA_NAME ParamProductionCell-PT-5-CTLFireability-10
FORMULA_NAME ParamProductionCell-PT-5-CTLFireability-11
FORMULA_NAME ParamProductionCell-PT-5-CTLFireability-12
FORMULA_NAME ParamProductionCell-PT-5-CTLFireability-13
FORMULA_NAME ParamProductionCell-PT-5-CTLFireability-14
FORMULA_NAME ParamProductionCell-PT-5-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678878902870

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ParamProductionCell-PT-5
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT ParamProductionCell-PT-5
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA ParamProductionCell-PT-5-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ParamProductionCell-PT-5-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ParamProductionCell-PT-5-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ParamProductionCell-PT-5-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ParamProductionCell-PT-5-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ParamProductionCell-PT-5-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ParamProductionCell-PT-5-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ParamProductionCell-PT-5-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ParamProductionCell-PT-5-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ParamProductionCell-PT-5-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ParamProductionCell-PT-5-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ParamProductionCell-PT-5-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ParamProductionCell-PT-5-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ParamProductionCell-PT-5-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ParamProductionCell-PT-5-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ParamProductionCell-PT-5-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678878998441

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:199
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 4 (type EXCL) for 3 ParamProductionCell-PT-5-CTLFireability-01
lola: time limit : 138 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 4 (type EXCL) for ParamProductionCell-PT-5-CTLFireability-01
lola: result : true
lola: markings : 3655
lola: fired transitions : 5006
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 ParamProductionCell-PT-5-CTLFireability-04
lola: time limit : 149 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:776
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-5-CTLFireability-01: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-5-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
ParamProductionCell-PT-5-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-10: F 0 1 0 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-14: DISJ 0 2 0 0 2 0 0 0
ParamProductionCell-PT-5-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/211 3/32 ParamProductionCell-PT-5-CTLFireability-04 520812 m, 104162 m/sec, 3035665 t fired, .

Time elapsed: 6 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 13 (type EXCL) for ParamProductionCell-PT-5-CTLFireability-04
lola: result : false
lola: markings : 566866
lola: fired transitions : 4022131
lola: time used : 6.000000
lola: memory pages used : 3
lola: LAUNCH task # 54 (type EXCL) for 53 ParamProductionCell-PT-5-CTLFireability-15
lola: time limit : 224 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-5-CTLFireability-01: CTL true CTL model checker
ParamProductionCell-PT-5-CTLFireability-04: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-5-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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ParamProductionCell-PT-5-CTLFireability-10: F 0 1 0 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 10/321 8/32 ParamProductionCell-PT-5-CTLFireability-09 1625347 m, 152652 m/sec, 7774616 t fired, .

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lola: FINISHED task # 32 (type EXCL) for ParamProductionCell-PT-5-CTLFireability-09
lola: result : true
lola: markings : 1657242
lola: fired transitions : 8415781
lola: time used : 11.000000
lola: memory pages used : 8
lola: LAUNCH task # 29 (type EXCL) for 28 ParamProductionCell-PT-5-CTLFireability-08
lola: time limit : 352 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-5-CTLFireability-01: CTL true CTL model checker
ParamProductionCell-PT-5-CTLFireability-04: CTL false CTL model checker
ParamProductionCell-PT-5-CTLFireability-09: CTL true CTL model checker
ParamProductionCell-PT-5-CTLFireability-11: CTL false CTL model checker
ParamProductionCell-PT-5-CTLFireability-13: CTL false CTL model checker
ParamProductionCell-PT-5-CTLFireability-14: DISJ true CTL model checker
ParamProductionCell-PT-5-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-5-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
ParamProductionCell-PT-5-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-10: F 0 1 0 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 4/352 3/32 ParamProductionCell-PT-5-CTLFireability-08 642036 m, 128407 m/sec, 2819667 t fired, .

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ParamProductionCell-PT-5-CTLFireability-01: CTL true CTL model checker
ParamProductionCell-PT-5-CTLFireability-04: CTL false CTL model checker
ParamProductionCell-PT-5-CTLFireability-09: CTL true CTL model checker
ParamProductionCell-PT-5-CTLFireability-11: CTL false CTL model checker
ParamProductionCell-PT-5-CTLFireability-13: CTL false CTL model checker
ParamProductionCell-PT-5-CTLFireability-14: DISJ true CTL model checker
ParamProductionCell-PT-5-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-5-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
ParamProductionCell-PT-5-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-10: F 0 1 0 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 9/352 7/32 ParamProductionCell-PT-5-CTLFireability-08 1394470 m, 150486 m/sec, 7008671 t fired, .

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lola: FINISHED task # 29 (type EXCL) for ParamProductionCell-PT-5-CTLFireability-08
lola: result : true
lola: markings : 1506167
lola: fired transitions : 7717879
lola: time used : 10.000000
lola: memory pages used : 7
lola: LAUNCH task # 19 (type EXCL) for 18 ParamProductionCell-PT-5-CTLFireability-06
lola: time limit : 390 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for ParamProductionCell-PT-5-CTLFireability-06
lola: result : true
lola: markings : 336041
lola: fired transitions : 1082878
lola: time used : 1.000000
lola: memory pages used : 2
lola: LAUNCH task # 16 (type EXCL) for 15 ParamProductionCell-PT-5-CTLFireability-05
lola: time limit : 439 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for ParamProductionCell-PT-5-CTLFireability-05
lola: result : false
lola: markings : 229
lola: fired transitions : 228
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 ParamProductionCell-PT-5-CTLFireability-03
lola: time limit : 501 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for ParamProductionCell-PT-5-CTLFireability-03
lola: result : false
lola: markings : 280
lola: fired transitions : 560
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 ParamProductionCell-PT-5-CTLFireability-00
lola: time limit : 585 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-5-CTLFireability-01: CTL true CTL model checker
ParamProductionCell-PT-5-CTLFireability-03: CTL false CTL model checker
ParamProductionCell-PT-5-CTLFireability-04: CTL false CTL model checker
ParamProductionCell-PT-5-CTLFireability-05: CTL false CTL model checker
ParamProductionCell-PT-5-CTLFireability-06: CTL true CTL model checker
ParamProductionCell-PT-5-CTLFireability-08: CTL true CTL model checker
ParamProductionCell-PT-5-CTLFireability-09: CTL true CTL model checker
ParamProductionCell-PT-5-CTLFireability-11: CTL false CTL model checker
ParamProductionCell-PT-5-CTLFireability-13: CTL false CTL model checker
ParamProductionCell-PT-5-CTLFireability-14: DISJ true CTL model checker
ParamProductionCell-PT-5-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-5-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
ParamProductionCell-PT-5-CTLFireability-10: F 0 1 0 0 1 0 0 0
ParamProductionCell-PT-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 3/585 4/32 ParamProductionCell-PT-5-CTLFireability-00 808325 m, 161665 m/sec, 2546431 t fired, .

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lola: FINISHED task # 1 (type EXCL) for ParamProductionCell-PT-5-CTLFireability-00
lola: result : true
lola: markings : 1328620
lola: fired transitions : 4419491
lola: time used : 5.000000
lola: memory pages used : 7
lola: LAUNCH task # 56 (type EXCL) for 34 ParamProductionCell-PT-5-CTLFireability-10
lola: time limit : 701 sec
lola: memory limit: 32 pages
lola: FINISHED task # 56 (type EXCL) for ParamProductionCell-PT-5-CTLFireability-10
lola: result : true
lola: markings : 280
lola: fired transitions : 280
lola: time used : 0.000000
lola: memory pages used : 1
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lola: time limit : 876 sec
lola: memory limit: 32 pages
lola: FINISHED task # 57 (type EXCL) for ParamProductionCell-PT-5-CTLFireability-07
lola: result : false
lola: markings : 1525
lola: fired transitions : 1825
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 26 (type EXCL) for 21 ParamProductionCell-PT-5-CTLFireability-07
lola: time limit : 1169 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for ParamProductionCell-PT-5-CTLFireability-07
lola: result : true
lola: markings : 307
lola: fired transitions : 307
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 41 (type EXCL) for 40 ParamProductionCell-PT-5-CTLFireability-12
lola: time limit : 1753 sec
lola: memory limit: 32 pages
lola: FINISHED task # 41 (type EXCL) for ParamProductionCell-PT-5-CTLFireability-12
lola: result : true
lola: markings : 236
lola: fired transitions : 236
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 ParamProductionCell-PT-5-CTLFireability-02
lola: time limit : 3507 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-5-CTLFireability-00: CTL true CTL model checker
ParamProductionCell-PT-5-CTLFireability-01: CTL true CTL model checker
ParamProductionCell-PT-5-CTLFireability-03: CTL false CTL model checker
ParamProductionCell-PT-5-CTLFireability-04: CTL false CTL model checker
ParamProductionCell-PT-5-CTLFireability-05: CTL false CTL model checker
ParamProductionCell-PT-5-CTLFireability-06: CTL true CTL model checker
ParamProductionCell-PT-5-CTLFireability-07: CONJ true CONJ
ParamProductionCell-PT-5-CTLFireability-08: CTL true CTL model checker
ParamProductionCell-PT-5-CTLFireability-09: CTL true CTL model checker
ParamProductionCell-PT-5-CTLFireability-10: F false state space / EG
ParamProductionCell-PT-5-CTLFireability-11: CTL false CTL model checker
ParamProductionCell-PT-5-CTLFireability-12: CTL true CTL model checker
ParamProductionCell-PT-5-CTLFireability-13: CTL false CTL model checker
ParamProductionCell-PT-5-CTLFireability-14: DISJ true CTL model checker
ParamProductionCell-PT-5-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-5-CTLFireability-02: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 3/3507 2/32 ParamProductionCell-PT-5-CTLFireability-02 393168 m, 78633 m/sec, 2255221 t fired, .

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lola: FINISHED task # 7 (type EXCL) for ParamProductionCell-PT-5-CTLFireability-02
lola: result : false
lola: markings : 409385
lola: fired transitions : 2386227
lola: time used : 3.000000
lola: memory pages used : 2
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-5-CTLFireability-00: CTL true CTL model checker
ParamProductionCell-PT-5-CTLFireability-01: CTL true CTL model checker
ParamProductionCell-PT-5-CTLFireability-02: CTL false CTL model checker
ParamProductionCell-PT-5-CTLFireability-03: CTL false CTL model checker
ParamProductionCell-PT-5-CTLFireability-04: CTL false CTL model checker
ParamProductionCell-PT-5-CTLFireability-05: CTL false CTL model checker
ParamProductionCell-PT-5-CTLFireability-06: CTL true CTL model checker
ParamProductionCell-PT-5-CTLFireability-07: CONJ true CONJ
ParamProductionCell-PT-5-CTLFireability-08: CTL true CTL model checker
ParamProductionCell-PT-5-CTLFireability-09: CTL true CTL model checker
ParamProductionCell-PT-5-CTLFireability-10: F false state space / EG
ParamProductionCell-PT-5-CTLFireability-11: CTL false CTL model checker
ParamProductionCell-PT-5-CTLFireability-12: CTL true CTL model checker
ParamProductionCell-PT-5-CTLFireability-13: CTL false CTL model checker
ParamProductionCell-PT-5-CTLFireability-14: DISJ true CTL model checker
ParamProductionCell-PT-5-CTLFireability-15: CTL false CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ParamProductionCell-PT-5"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is ParamProductionCell-PT-5, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r262-smll-167863537200402"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ParamProductionCell-PT-5.tgz
mv ParamProductionCell-PT-5 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;