fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r262-smll-167863537200394
Last Updated
May 14, 2023

About the Execution of LoLA for ParamProductionCell-PT-4

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
2864.231 77076.00 230804.00 184.80 FFTTFFTFFTFTFTTF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r262-smll-167863537200394.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is ParamProductionCell-PT-4, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r262-smll-167863537200394
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 652K
-rw-r--r-- 1 mcc users 9.3K Feb 26 17:17 CTLCardinality.txt
-rw-r--r-- 1 mcc users 86K Feb 26 17:17 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.0K Feb 26 17:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 58K Feb 26 17:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.2K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.8K Feb 25 16:30 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K Feb 25 16:30 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Feb 25 16:30 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:30 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 26 17:19 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 117K Feb 26 17:19 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.1K Feb 26 17:18 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 58K Feb 26 17:18 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 25 16:30 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:30 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 174K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-00
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-01
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-02
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-03
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-04
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-05
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-06
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-07
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-08
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-09
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-10
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-11
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-12
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-13
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-14
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678878223842

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ParamProductionCell-PT-4
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT ParamProductionCell-PT-4
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA ParamProductionCell-PT-4-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ParamProductionCell-PT-4-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ParamProductionCell-PT-4-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ParamProductionCell-PT-4-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ParamProductionCell-PT-4-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ParamProductionCell-PT-4-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ParamProductionCell-PT-4-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ParamProductionCell-PT-4-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ParamProductionCell-PT-4-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ParamProductionCell-PT-4-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ParamProductionCell-PT-4-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ParamProductionCell-PT-4-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ParamProductionCell-PT-4-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ParamProductionCell-PT-4-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ParamProductionCell-PT-4-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ParamProductionCell-PT-4-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678878300918

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:183
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:460
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:182
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 4 (type EXCL) for 3 ParamProductionCell-PT-4-CTLFireability-01
lola: time limit : 138 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
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lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
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lola: FINISHED task # 53 (type FNDP) for ParamProductionCell-PT-4-CTLFireability-14
lola: result : true
lola: fired transitions : 60
lola: tried executions : 1
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lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: FINISHED task # 61 (type SRCH) for ParamProductionCell-PT-4-CTLFireability-10
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lola: result : true
lola: fired transitions : 69
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lola: CANCELED task # 59 (type EQUN) for ParamProductionCell-PT-4-CTLFireability-10 (obsolete)
sara: try reading problem file /home/mcc/execution/CTLFireability-54.sara.
sara: try reading problem file /home/mcc/execution/CTLFireability-59.sara.
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-4-CTLFireability-10: AG false findpath
ParamProductionCell-PT-4-CTLFireability-14: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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ParamProductionCell-PT-4-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
ParamProductionCell-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/239 3/32 ParamProductionCell-PT-4-CTLFireability-01 596120 m, 119224 m/sec, 3444591 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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ParamProductionCell-PT-4-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
ParamProductionCell-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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ParamProductionCell-PT-4-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
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ParamProductionCell-PT-4-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/239 5/32 ParamProductionCell-PT-4-CTLFireability-01 933090 m, 67394 m/sec, 7497355 t fired, .

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ParamProductionCell-PT-4-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
ParamProductionCell-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/239 5/32 ParamProductionCell-PT-4-CTLFireability-01 936979 m, 777 m/sec, 11262720 t fired, .

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lola: result : true
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lola: FINISHED task # 32 (type EXCL) for ParamProductionCell-PT-4-CTLFireability-09
lola: result : true
lola: markings : 1138
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lola: time limit : 358 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-4-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-09: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-10: AG false findpath
ParamProductionCell-PT-4-CTLFireability-11: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-12: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-14: EF true findpath
ParamProductionCell-PT-4-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-4-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
ParamProductionCell-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 4/358 4/32 ParamProductionCell-PT-4-CTLFireability-08 802609 m, 160521 m/sec, 2853149 t fired, .

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ParamProductionCell-PT-4-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-09: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-10: AG false findpath
ParamProductionCell-PT-4-CTLFireability-11: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-12: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-14: EF true findpath
ParamProductionCell-PT-4-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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ParamProductionCell-PT-4-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 9/358 8/32 ParamProductionCell-PT-4-CTLFireability-08 1671279 m, 173734 m/sec, 6901460 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-4-CTLFireability-01: CTL false CTL model checker
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ParamProductionCell-PT-4-CTLFireability-08: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-09: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-10: AG false findpath
ParamProductionCell-PT-4-CTLFireability-11: CTL true CTL model checker
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ParamProductionCell-PT-4-CTLFireability-14: EF true findpath
ParamProductionCell-PT-4-CTLFireability-15: CTL false CTL model checker

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14 CTL EXCL 3/446 2/32 ParamProductionCell-PT-4-CTLFireability-03 281211 m, 56242 m/sec, 1562956 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-4-CTLFireability-01: CTL false CTL model checker
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ParamProductionCell-PT-4-CTLFireability-05: CTL false CTL model checker
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ParamProductionCell-PT-4-CTLFireability-10: AG false findpath
ParamProductionCell-PT-4-CTLFireability-11: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-12: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-14: EF true findpath
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11 CTL EXCL 2/509 3/32 ParamProductionCell-PT-4-CTLFireability-02 441761 m, 88352 m/sec, 1333781 t fired, .

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ParamProductionCell-PT-4-CTLFireability-03: CTL true CTL model checker
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ParamProductionCell-PT-4-CTLFireability-11: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-12: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-14: EF true findpath
ParamProductionCell-PT-4-CTLFireability-15: CTL false CTL model checker

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ParamProductionCell-PT-4-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

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1 CTL EXCL 3/712 3/32 ParamProductionCell-PT-4-CTLFireability-00 480595 m, 96119 m/sec, 1949844 t fired, .

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ParamProductionCell-PT-4-CTLFireability-11: CTL true CTL model checker
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ParamProductionCell-PT-4-CTLFireability-14: EF true findpath
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ParamProductionCell-PT-4-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 8/712 6/32 ParamProductionCell-PT-4-CTLFireability-00 1267475 m, 157376 m/sec, 5579979 t fired, .

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ParamProductionCell-PT-4-CTLFireability-05: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-08: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-09: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-10: AG false findpath
ParamProductionCell-PT-4-CTLFireability-11: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-12: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-14: EF true findpath
ParamProductionCell-PT-4-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-4-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 13/712 10/32 ParamProductionCell-PT-4-CTLFireability-00 2016471 m, 149799 m/sec, 9324338 t fired, .

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lola: FINISHED task # 1 (type EXCL) for ParamProductionCell-PT-4-CTLFireability-00
lola: result : false
lola: markings : 2409739
lola: fired transitions : 12333114
lola: time used : 17.000000
lola: memory pages used : 12
lola: LAUNCH task # 26 (type EXCL) for 25 ParamProductionCell-PT-4-CTLFireability-07
lola: time limit : 886 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for ParamProductionCell-PT-4-CTLFireability-07
lola: result : false
lola: markings : 28714
lola: fired transitions : 65368
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 23 (type EXCL) for 22 ParamProductionCell-PT-4-CTLFireability-06
lola: time limit : 1181 sec
lola: memory limit: 32 pages
lola: FINISHED task # 23 (type EXCL) for ParamProductionCell-PT-4-CTLFireability-06
lola: result : true
lola: markings : 353
lola: fired transitions : 367
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 44 (type EXCL) for 43 ParamProductionCell-PT-4-CTLFireability-13
lola: time limit : 1772 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-4-CTLFireability-00: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-02: DISJ true CTL model checker
ParamProductionCell-PT-4-CTLFireability-03: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-05: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-06: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-07: EFEG false state space /EFEG
ParamProductionCell-PT-4-CTLFireability-08: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-09: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-10: AG false findpath
ParamProductionCell-PT-4-CTLFireability-11: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-12: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-14: EF true findpath
ParamProductionCell-PT-4-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-4-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 1/1772 1/32 ParamProductionCell-PT-4-CTLFireability-13 69446 m, 13889 m/sec, 170457 t fired, .

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ParamProductionCell-PT-4-CTLFireability-00: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-02: DISJ true CTL model checker
ParamProductionCell-PT-4-CTLFireability-03: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-05: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-06: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-07: EFEG false state space /EFEG
ParamProductionCell-PT-4-CTLFireability-08: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-09: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-10: AG false findpath
ParamProductionCell-PT-4-CTLFireability-11: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-12: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-14: EF true findpath
ParamProductionCell-PT-4-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-4-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 6/1772 3/32 ParamProductionCell-PT-4-CTLFireability-13 516633 m, 89437 m/sec, 3856717 t fired, .

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ParamProductionCell-PT-4-CTLFireability-00: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-02: DISJ true CTL model checker
ParamProductionCell-PT-4-CTLFireability-03: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-05: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-06: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-07: EFEG false state space /EFEG
ParamProductionCell-PT-4-CTLFireability-08: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-09: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-10: AG false findpath
ParamProductionCell-PT-4-CTLFireability-11: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-12: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-14: EF true findpath
ParamProductionCell-PT-4-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-4-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 11/1772 5/32 ParamProductionCell-PT-4-CTLFireability-13 923133 m, 81300 m/sec, 7851314 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-4-CTLFireability-00: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-02: DISJ true CTL model checker
ParamProductionCell-PT-4-CTLFireability-03: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-05: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-06: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-07: EFEG false state space /EFEG
ParamProductionCell-PT-4-CTLFireability-08: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-09: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-10: AG false findpath
ParamProductionCell-PT-4-CTLFireability-11: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-12: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-14: EF true findpath
ParamProductionCell-PT-4-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-4-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ParamProductionCell-PT-4-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 16/1772 5/32 ParamProductionCell-PT-4-CTLFireability-13 976022 m, 10577 m/sec, 12306873 t fired, .

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# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 44 (type EXCL) for ParamProductionCell-PT-4-CTLFireability-13
lola: result : true
lola: markings : 976022
lola: fired transitions : 12830435
lola: time used : 16.000000
lola: memory pages used : 5
lola: LAUNCH task # 17 (type EXCL) for 16 ParamProductionCell-PT-4-CTLFireability-04
lola: time limit : 3529 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-4-CTLFireability-00: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-02: DISJ true CTL model checker
ParamProductionCell-PT-4-CTLFireability-03: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-05: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-06: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-07: EFEG false state space /EFEG
ParamProductionCell-PT-4-CTLFireability-08: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-09: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-10: AG false findpath
ParamProductionCell-PT-4-CTLFireability-11: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-12: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-13: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-14: EF true findpath
ParamProductionCell-PT-4-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ParamProductionCell-PT-4-CTLFireability-04: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 5/3529 3/32 ParamProductionCell-PT-4-CTLFireability-04 452547 m, 90509 m/sec, 3912235 t fired, .

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lola: FINISHED task # 17 (type EXCL) for ParamProductionCell-PT-4-CTLFireability-04
lola: result : false
lola: markings : 611890
lola: fired transitions : 5447112
lola: time used : 6.000000
lola: memory pages used : 3
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ParamProductionCell-PT-4-CTLFireability-00: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-01: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-02: DISJ true CTL model checker
ParamProductionCell-PT-4-CTLFireability-03: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-04: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-05: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-06: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-07: EFEG false state space /EFEG
ParamProductionCell-PT-4-CTLFireability-08: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-09: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-10: AG false findpath
ParamProductionCell-PT-4-CTLFireability-11: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-12: CTL false CTL model checker
ParamProductionCell-PT-4-CTLFireability-13: CTL true CTL model checker
ParamProductionCell-PT-4-CTLFireability-14: EF true findpath
ParamProductionCell-PT-4-CTLFireability-15: CTL false CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ParamProductionCell-PT-4"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is ParamProductionCell-PT-4, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r262-smll-167863537200394"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ParamProductionCell-PT-4.tgz
mv ParamProductionCell-PT-4 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;