About the Execution of LoLa+red for MAPKbis-PT-5310
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 4332.752 | 3600000.00 | 3830340.00 | 9836.20 | ?TTTTFT?FF??F?TT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r231-tall-167856416300634.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is MAPKbis-PT-5310, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r231-tall-167856416300634
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 636K
-rw-r--r-- 1 mcc users 6.4K Feb 25 16:17 CTLCardinality.txt
-rw-r--r-- 1 mcc users 54K Feb 25 16:17 CTLCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 15:59 CTLFireability.txt
-rw-r--r-- 1 mcc users 48K Feb 25 15:59 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.2K Feb 25 16:22 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:22 LTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K Feb 25 16:22 LTLFireability.txt
-rw-r--r-- 1 mcc users 21K Feb 25 16:22 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 16:35 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 111K Feb 25 16:35 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 22K Feb 25 16:26 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 82K Feb 25 16:26 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:22 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:22 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 170K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME MAPKbis-PT-5310-CTLFireability-00
FORMULA_NAME MAPKbis-PT-5310-CTLFireability-01
FORMULA_NAME MAPKbis-PT-5310-CTLFireability-02
FORMULA_NAME MAPKbis-PT-5310-CTLFireability-03
FORMULA_NAME MAPKbis-PT-5310-CTLFireability-04
FORMULA_NAME MAPKbis-PT-5310-CTLFireability-05
FORMULA_NAME MAPKbis-PT-5310-CTLFireability-06
FORMULA_NAME MAPKbis-PT-5310-CTLFireability-07
FORMULA_NAME MAPKbis-PT-5310-CTLFireability-08
FORMULA_NAME MAPKbis-PT-5310-CTLFireability-09
FORMULA_NAME MAPKbis-PT-5310-CTLFireability-10
FORMULA_NAME MAPKbis-PT-5310-CTLFireability-11
FORMULA_NAME MAPKbis-PT-5310-CTLFireability-12
FORMULA_NAME MAPKbis-PT-5310-CTLFireability-13
FORMULA_NAME MAPKbis-PT-5310-CTLFireability-14
FORMULA_NAME MAPKbis-PT-5310-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679469843145
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=MAPKbis-PT-5310
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-22 07:24:04] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-22 07:24:04] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-22 07:24:04] [INFO ] Load time of PNML (sax parser for PT used): 53 ms
[2023-03-22 07:24:04] [INFO ] Transformed 106 places.
[2023-03-22 07:24:04] [INFO ] Transformed 173 transitions.
[2023-03-22 07:24:04] [INFO ] Found NUPN structural information;
[2023-03-22 07:24:04] [INFO ] Parsed PT model containing 106 places and 173 transitions and 986 arcs in 112 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Deduced a syphon composed of 11 places in 2 ms
Reduce places removed 15 places and 41 transitions.
Reduce places removed 7 places and 0 transitions.
FORMULA MAPKbis-PT-5310-CTLFireability-02 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA MAPKbis-PT-5310-CTLFireability-05 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA MAPKbis-PT-5310-CTLFireability-09 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA MAPKbis-PT-5310-CTLFireability-12 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 73 out of 84 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 84/84 places, 132/132 transitions.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 84 transition count 130
Applied a total of 2 rules in 192 ms. Remains 84 /84 variables (removed 0) and now considering 130/132 (removed 2) transitions.
[2023-03-22 07:24:04] [INFO ] Flow matrix only has 84 transitions (discarded 46 similar events)
// Phase 1: matrix 84 rows 84 cols
[2023-03-22 07:24:05] [INFO ] Computed 42 place invariants in 9 ms
[2023-03-22 07:24:05] [INFO ] Implicit Places using invariants in 190 ms returned []
[2023-03-22 07:24:05] [INFO ] Flow matrix only has 84 transitions (discarded 46 similar events)
[2023-03-22 07:24:05] [INFO ] Invariant cache hit.
[2023-03-22 07:24:05] [INFO ] State equation strengthened by 42 read => feed constraints.
[2023-03-22 07:24:05] [INFO ] Implicit Places using invariants and state equation in 90 ms returned []
Implicit Place search using SMT with State Equation took 305 ms to find 0 implicit places.
[2023-03-22 07:24:05] [INFO ] Flow matrix only has 84 transitions (discarded 46 similar events)
[2023-03-22 07:24:05] [INFO ] Invariant cache hit.
[2023-03-22 07:24:05] [INFO ] Dead Transitions using invariants and state equation in 81 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 84/84 places, 130/132 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 581 ms. Remains : 84/84 places, 130/132 transitions.
Support contains 73 out of 84 places after structural reductions.
[2023-03-22 07:24:05] [INFO ] Flatten gal took : 28 ms
[2023-03-22 07:24:05] [INFO ] Flatten gal took : 12 ms
[2023-03-22 07:24:05] [INFO ] Input system was already deterministic with 130 transitions.
Support contains 72 out of 84 places (down from 73) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 409 ms. (steps per millisecond=24 ) properties (out of 53) seen :48
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 51 ms. (steps per millisecond=196 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=322 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=434 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=384 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=416 ) properties (out of 5) seen :0
Running SMT prover for 5 properties.
[2023-03-22 07:24:06] [INFO ] Flow matrix only has 84 transitions (discarded 46 similar events)
[2023-03-22 07:24:06] [INFO ] Invariant cache hit.
[2023-03-22 07:24:06] [INFO ] [Real]Absence check using 42 positive place invariants in 15 ms returned sat
[2023-03-22 07:24:06] [INFO ] After 211ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0 real:4
[2023-03-22 07:24:06] [INFO ] [Nat]Absence check using 42 positive place invariants in 5 ms returned sat
[2023-03-22 07:24:06] [INFO ] After 36ms SMT Verify possible using state equation in natural domain returned unsat :1 sat :4
[2023-03-22 07:24:06] [INFO ] State equation strengthened by 42 read => feed constraints.
[2023-03-22 07:24:06] [INFO ] After 31ms SMT Verify possible using 42 Read/Feed constraints in natural domain returned unsat :1 sat :4
[2023-03-22 07:24:06] [INFO ] After 81ms SMT Verify possible using trap constraints in natural domain returned unsat :1 sat :4
Attempting to minimize the solution found.
Minimization took 71 ms.
[2023-03-22 07:24:06] [INFO ] After 251ms SMT Verify possible using all constraints in natural domain returned unsat :1 sat :4
Fused 5 Parikh solutions to 3 different solutions.
Parikh walk visited 0 properties in 8 ms.
Support contains 8 out of 84 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 84/84 places, 130/130 transitions.
Graph (complete) has 261 edges and 84 vertex of which 74 are kept as prefixes of interest. Removing 10 places using SCC suffix rule.2 ms
Discarding 10 places :
Also discarding 4 output transitions
Drop transitions removed 4 transitions
Drop transitions removed 10 transitions
Reduce isomorphic transitions removed 10 transitions.
Iterating post reduction 0 with 10 rules applied. Total rules applied 11 place count 74 transition count 116
Applied a total of 11 rules in 20 ms. Remains 74 /84 variables (removed 10) and now considering 116/130 (removed 14) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 20 ms. Remains : 74/84 places, 116/130 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 115 ms. (steps per millisecond=86 ) properties (out of 4) seen :2
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=526 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=666 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-22 07:24:06] [INFO ] Flow matrix only has 74 transitions (discarded 42 similar events)
// Phase 1: matrix 74 rows 74 cols
[2023-03-22 07:24:06] [INFO ] Computed 37 place invariants in 2 ms
[2023-03-22 07:24:06] [INFO ] [Real]Absence check using 37 positive place invariants in 4 ms returned sat
[2023-03-22 07:24:06] [INFO ] After 105ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-22 07:24:07] [INFO ] [Nat]Absence check using 37 positive place invariants in 15 ms returned sat
[2023-03-22 07:24:07] [INFO ] After 24ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-22 07:24:07] [INFO ] State equation strengthened by 37 read => feed constraints.
[2023-03-22 07:24:07] [INFO ] After 9ms SMT Verify possible using 37 Read/Feed constraints in natural domain returned unsat :0 sat :2
[2023-03-22 07:24:07] [INFO ] After 21ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 9 ms.
[2023-03-22 07:24:07] [INFO ] After 105ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
Parikh walk visited 0 properties in 2 ms.
Support contains 5 out of 74 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 74/74 places, 116/116 transitions.
Graph (complete) has 233 edges and 74 vertex of which 68 are kept as prefixes of interest. Removing 6 places using SCC suffix rule.1 ms
Discarding 6 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Drop transitions removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Iterating post reduction 0 with 9 rules applied. Total rules applied 10 place count 68 transition count 105
Applied a total of 10 rules in 6 ms. Remains 68 /74 variables (removed 6) and now considering 105/116 (removed 11) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 6 ms. Remains : 68/74 places, 105/116 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 101 ms. (steps per millisecond=99 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=416 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=555 ) properties (out of 2) seen :0
Interrupted probabilistic random walk after 594303 steps, run timeout after 3001 ms. (steps per millisecond=198 ) properties seen :{}
Probabilistic random walk after 594303 steps, saw 334258 distinct states, run finished after 3002 ms. (steps per millisecond=197 ) properties seen :0
Running SMT prover for 2 properties.
[2023-03-22 07:24:10] [INFO ] Flow matrix only has 68 transitions (discarded 37 similar events)
// Phase 1: matrix 68 rows 68 cols
[2023-03-22 07:24:10] [INFO ] Computed 34 place invariants in 5 ms
[2023-03-22 07:24:10] [INFO ] [Real]Absence check using 34 positive place invariants in 4 ms returned sat
[2023-03-22 07:24:10] [INFO ] After 64ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-22 07:24:10] [INFO ] [Nat]Absence check using 34 positive place invariants in 4 ms returned sat
[2023-03-22 07:24:10] [INFO ] After 32ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-22 07:24:10] [INFO ] State equation strengthened by 34 read => feed constraints.
[2023-03-22 07:24:10] [INFO ] After 10ms SMT Verify possible using 34 Read/Feed constraints in natural domain returned unsat :0 sat :2
[2023-03-22 07:24:10] [INFO ] After 21ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 11 ms.
[2023-03-22 07:24:10] [INFO ] After 109ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
Parikh walk visited 0 properties in 0 ms.
Support contains 5 out of 68 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 68/68 places, 105/105 transitions.
Applied a total of 0 rules in 6 ms. Remains 68 /68 variables (removed 0) and now considering 105/105 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 6 ms. Remains : 68/68 places, 105/105 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 68/68 places, 105/105 transitions.
Applied a total of 0 rules in 5 ms. Remains 68 /68 variables (removed 0) and now considering 105/105 (removed 0) transitions.
[2023-03-22 07:24:10] [INFO ] Flow matrix only has 68 transitions (discarded 37 similar events)
[2023-03-22 07:24:10] [INFO ] Invariant cache hit.
[2023-03-22 07:24:10] [INFO ] Implicit Places using invariants in 64 ms returned []
[2023-03-22 07:24:10] [INFO ] Flow matrix only has 68 transitions (discarded 37 similar events)
[2023-03-22 07:24:10] [INFO ] Invariant cache hit.
[2023-03-22 07:24:10] [INFO ] State equation strengthened by 34 read => feed constraints.
[2023-03-22 07:24:10] [INFO ] Implicit Places using invariants and state equation in 86 ms returned []
Implicit Place search using SMT with State Equation took 151 ms to find 0 implicit places.
[2023-03-22 07:24:10] [INFO ] Redundant transitions in 2 ms returned []
[2023-03-22 07:24:10] [INFO ] Flow matrix only has 68 transitions (discarded 37 similar events)
[2023-03-22 07:24:10] [INFO ] Invariant cache hit.
[2023-03-22 07:24:10] [INFO ] Dead Transitions using invariants and state equation in 80 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 248 ms. Remains : 68/68 places, 105/105 transitions.
Graph (trivial) has 90 edges and 68 vertex of which 58 / 68 are part of one of the 29 SCC in 2 ms
Free SCC test removed 29 places
Drop transitions removed 90 transitions
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 95 transitions.
Graph (complete) has 10 edges and 39 vertex of which 10 are kept as prefixes of interest. Removing 29 places using SCC suffix rule.0 ms
Discarding 29 places :
Also discarding 0 output transitions
Applied a total of 2 rules in 5 ms. Remains 10 /68 variables (removed 58) and now considering 10/105 (removed 95) transitions.
Running SMT prover for 2 properties.
// Phase 1: matrix 10 rows 10 cols
[2023-03-22 07:24:10] [INFO ] Computed 5 place invariants in 1 ms
[2023-03-22 07:24:10] [INFO ] [Real]Absence check using 5 positive place invariants in 0 ms returned sat
[2023-03-22 07:24:10] [INFO ] After 5ms SMT Verify possible using state equation in real domain returned unsat :0 sat :2
[2023-03-22 07:24:10] [INFO ] After 9ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :1 real:1
Attempting to minimize the solution found.
Minimization took 2 ms.
[2023-03-22 07:24:10] [INFO ] After 35ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-22 07:24:10] [INFO ] [Nat]Absence check using 5 positive place invariants in 1 ms returned sat
[2023-03-22 07:24:10] [INFO ] After 5ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-22 07:24:10] [INFO ] After 9ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 14 ms.
[2023-03-22 07:24:10] [INFO ] After 53ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
Successfully simplified 1 atomic propositions for a total of 10 simplifications.
[2023-03-22 07:24:10] [INFO ] Flatten gal took : 8 ms
[2023-03-22 07:24:10] [INFO ] Flatten gal took : 9 ms
[2023-03-22 07:24:10] [INFO ] Input system was already deterministic with 130 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 84/84 places, 130/130 transitions.
Applied a total of 0 rules in 2 ms. Remains 84 /84 variables (removed 0) and now considering 130/130 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 84/84 places, 130/130 transitions.
[2023-03-22 07:24:10] [INFO ] Flatten gal took : 7 ms
[2023-03-22 07:24:10] [INFO ] Flatten gal took : 8 ms
[2023-03-22 07:24:10] [INFO ] Input system was already deterministic with 130 transitions.
Starting structural reductions in LTL mode, iteration 0 : 84/84 places, 130/130 transitions.
Applied a total of 0 rules in 2 ms. Remains 84 /84 variables (removed 0) and now considering 130/130 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 84/84 places, 130/130 transitions.
[2023-03-22 07:24:10] [INFO ] Flatten gal took : 7 ms
[2023-03-22 07:24:10] [INFO ] Flatten gal took : 8 ms
[2023-03-22 07:24:10] [INFO ] Input system was already deterministic with 130 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 84/84 places, 130/130 transitions.
Applied a total of 0 rules in 6 ms. Remains 84 /84 variables (removed 0) and now considering 130/130 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 7 ms. Remains : 84/84 places, 130/130 transitions.
[2023-03-22 07:24:10] [INFO ] Flatten gal took : 7 ms
[2023-03-22 07:24:10] [INFO ] Flatten gal took : 8 ms
[2023-03-22 07:24:10] [INFO ] Input system was already deterministic with 130 transitions.
Starting structural reductions in LTL mode, iteration 0 : 84/84 places, 130/130 transitions.
Applied a total of 0 rules in 1 ms. Remains 84 /84 variables (removed 0) and now considering 130/130 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 84/84 places, 130/130 transitions.
[2023-03-22 07:24:10] [INFO ] Flatten gal took : 7 ms
[2023-03-22 07:24:10] [INFO ] Flatten gal took : 7 ms
[2023-03-22 07:24:10] [INFO ] Input system was already deterministic with 130 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 84/84 places, 130/130 transitions.
Applied a total of 0 rules in 6 ms. Remains 84 /84 variables (removed 0) and now considering 130/130 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 84/84 places, 130/130 transitions.
[2023-03-22 07:24:11] [INFO ] Flatten gal took : 6 ms
[2023-03-22 07:24:11] [INFO ] Flatten gal took : 7 ms
[2023-03-22 07:24:11] [INFO ] Input system was already deterministic with 130 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 84/84 places, 130/130 transitions.
Applied a total of 0 rules in 6 ms. Remains 84 /84 variables (removed 0) and now considering 130/130 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 8 ms. Remains : 84/84 places, 130/130 transitions.
[2023-03-22 07:24:11] [INFO ] Flatten gal took : 5 ms
[2023-03-22 07:24:11] [INFO ] Flatten gal took : 6 ms
[2023-03-22 07:24:11] [INFO ] Input system was already deterministic with 130 transitions.
Starting structural reductions in LTL mode, iteration 0 : 84/84 places, 130/130 transitions.
Applied a total of 0 rules in 2 ms. Remains 84 /84 variables (removed 0) and now considering 130/130 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 84/84 places, 130/130 transitions.
[2023-03-22 07:24:11] [INFO ] Flatten gal took : 5 ms
[2023-03-22 07:24:11] [INFO ] Flatten gal took : 6 ms
[2023-03-22 07:24:11] [INFO ] Input system was already deterministic with 130 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 84/84 places, 130/130 transitions.
Applied a total of 0 rules in 6 ms. Remains 84 /84 variables (removed 0) and now considering 130/130 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 84/84 places, 130/130 transitions.
[2023-03-22 07:24:11] [INFO ] Flatten gal took : 6 ms
[2023-03-22 07:24:11] [INFO ] Flatten gal took : 6 ms
[2023-03-22 07:24:11] [INFO ] Input system was already deterministic with 130 transitions.
Starting structural reductions in LTL mode, iteration 0 : 84/84 places, 130/130 transitions.
Applied a total of 0 rules in 2 ms. Remains 84 /84 variables (removed 0) and now considering 130/130 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 84/84 places, 130/130 transitions.
[2023-03-22 07:24:11] [INFO ] Flatten gal took : 6 ms
[2023-03-22 07:24:11] [INFO ] Flatten gal took : 6 ms
[2023-03-22 07:24:11] [INFO ] Input system was already deterministic with 130 transitions.
Starting structural reductions in LTL mode, iteration 0 : 84/84 places, 130/130 transitions.
Applied a total of 0 rules in 1 ms. Remains 84 /84 variables (removed 0) and now considering 130/130 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 84/84 places, 130/130 transitions.
[2023-03-22 07:24:11] [INFO ] Flatten gal took : 5 ms
[2023-03-22 07:24:11] [INFO ] Flatten gal took : 5 ms
[2023-03-22 07:24:11] [INFO ] Input system was already deterministic with 130 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 84/84 places, 130/130 transitions.
Applied a total of 0 rules in 5 ms. Remains 84 /84 variables (removed 0) and now considering 130/130 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 84/84 places, 130/130 transitions.
[2023-03-22 07:24:11] [INFO ] Flatten gal took : 4 ms
[2023-03-22 07:24:11] [INFO ] Flatten gal took : 4 ms
[2023-03-22 07:24:11] [INFO ] Input system was already deterministic with 130 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 84/84 places, 130/130 transitions.
Applied a total of 0 rules in 6 ms. Remains 84 /84 variables (removed 0) and now considering 130/130 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 84/84 places, 130/130 transitions.
[2023-03-22 07:24:11] [INFO ] Flatten gal took : 4 ms
[2023-03-22 07:24:11] [INFO ] Flatten gal took : 5 ms
[2023-03-22 07:24:11] [INFO ] Input system was already deterministic with 130 transitions.
[2023-03-22 07:24:11] [INFO ] Flatten gal took : 5 ms
[2023-03-22 07:24:11] [INFO ] Flatten gal took : 5 ms
[2023-03-22 07:24:11] [INFO ] Export to MCC of 12 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-22 07:24:11] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 84 places, 130 transitions and 670 arcs took 1 ms.
Total runtime 6635 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT MAPKbis-PT-5310
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability
FORMULA MAPKbis-PT-5310-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPKbis-PT-5310-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPKbis-PT-5310-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPKbis-PT-5310-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPKbis-PT-5310-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPKbis-PT-5310-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPKbis-PT-5310-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 11817580 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16101064 kB
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 4 (type CNST) for 3 MAPKbis-PT-5310-CTLFireability-01
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 4 (type CNST) for MAPKbis-PT-5310-CTLFireability-01
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 16 (type EXCL) for 15 MAPKbis-PT-5310-CTLFireability-07
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 37 (type FNDP) for 24 MAPKbis-PT-5310-CTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 38 (type FNDP) for 30 MAPKbis-PT-5310-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 39 (type EQUN) for 30 MAPKbis-PT-5310-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 38 (type FNDP) for MAPKbis-PT-5310-CTLFireability-14
lola: result : true
lola: fired transitions : 142
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 39 (type EQUN) for MAPKbis-PT-5310-CTLFireability-14 (obsolete)
sara: try reading problem file /home/mcc/execution/375/CTLFireability-39.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 39 (type EQUN) for MAPKbis-PT-5310-CTLFireability-14
lola: result : unknown
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPKbis-PT-5310-CTLFireability-01: INITIAL true preprocessing
MAPKbis-PT-5310-CTLFireability-14: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPKbis-PT-5310-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-06: EGEF 0 1 0 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-11: EF DL 0 1 1 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 5/360 5/32 MAPKbis-PT-5310-CTLFireability-07 1172500 m, 234500 m/sec, 5126550 t fired, .
37 EF DL FNDP 5/3600 0/5 MAPKbis-PT-5310-CTLFireability-11 2445348 t fired, 3 attempts, .
Time elapsed: 5 secs. Pages in use: 5
# running tasks: 2 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPKbis-PT-5310-CTLFireability-01: INITIAL true preprocessing
MAPKbis-PT-5310-CTLFireability-14: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPKbis-PT-5310-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-06: EGEF 0 1 0 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-11: EF DL 0 1 1 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 10/360 10/32 MAPKbis-PT-5310-CTLFireability-07 2211705 m, 207841 m/sec, 9962134 t fired, .
37 EF DL FNDP 10/3600 0/5 MAPKbis-PT-5310-CTLFireability-11 4954273 t fired, 5 attempts, .
Time elapsed: 10 secs. Pages in use: 10
# running tasks: 2 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPKbis-PT-5310-CTLFireability-01: INITIAL true preprocessing
MAPKbis-PT-5310-CTLFireability-14: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPKbis-PT-5310-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-06: EGEF 0 1 0 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-11: EF DL 0 1 1 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 15/360 14/32 MAPKbis-PT-5310-CTLFireability-07 3197401 m, 197139 m/sec, 14645637 t fired, .
37 EF DL FNDP 15/3600 0/5 MAPKbis-PT-5310-CTLFireability-11 7548182 t fired, 8 attempts, .
Time elapsed: 15 secs. Pages in use: 14
# running tasks: 2 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPKbis-PT-5310-CTLFireability-01: INITIAL true preprocessing
MAPKbis-PT-5310-CTLFireability-14: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPKbis-PT-5310-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-06: EGEF 0 1 0 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-11: EF DL 0 1 1 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
MAPKbis-PT-5310-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 20/360 18/32 MAPKbis-PT-5310-CTLFireability-07 4167115 m, 193942 m/sec, 19333084 t fired, .
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="MAPKbis-PT-5310"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is MAPKbis-PT-5310, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r231-tall-167856416300634"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/MAPKbis-PT-5310.tgz
mv MAPKbis-PT-5310 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;