Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r231-tall-167856416300570.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..........................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is MAPK-PT-00080, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r231-tall-167856416300570
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 516K
-rw-r--r-- 1 mcc users 5.9K Feb 26 10:47 CTLCardinality.txt
-rw-r--r-- 1 mcc users 56K Feb 26 10:47 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K Feb 26 10:46 CTLFireability.txt
-rw-r--r-- 1 mcc users 59K Feb 26 10:46 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.2K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:21 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:21 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 16:22 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:22 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 26 10:47 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 126K Feb 26 10:47 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 26 10:47 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 106K Feb 26 10:47 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:22 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:22 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 25K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME MAPK-PT-00080-CTLFireability-00
FORMULA_NAME MAPK-PT-00080-CTLFireability-01
FORMULA_NAME MAPK-PT-00080-CTLFireability-02
FORMULA_NAME MAPK-PT-00080-CTLFireability-03
FORMULA_NAME MAPK-PT-00080-CTLFireability-04
FORMULA_NAME MAPK-PT-00080-CTLFireability-05
FORMULA_NAME MAPK-PT-00080-CTLFireability-06
FORMULA_NAME MAPK-PT-00080-CTLFireability-07
FORMULA_NAME MAPK-PT-00080-CTLFireability-08
FORMULA_NAME MAPK-PT-00080-CTLFireability-09
FORMULA_NAME MAPK-PT-00080-CTLFireability-10
FORMULA_NAME MAPK-PT-00080-CTLFireability-11
FORMULA_NAME MAPK-PT-00080-CTLFireability-12
FORMULA_NAME MAPK-PT-00080-CTLFireability-13
FORMULA_NAME MAPK-PT-00080-CTLFireability-14
FORMULA_NAME MAPK-PT-00080-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679463946938

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=MAPK-PT-00080
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-22 05:45:48] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-22 05:45:48] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-22 05:45:48] [INFO ] Load time of PNML (sax parser for PT used): 24 ms
[2023-03-22 05:45:48] [INFO ] Transformed 22 places.
[2023-03-22 05:45:48] [INFO ] Transformed 30 transitions.
[2023-03-22 05:45:48] [INFO ] Parsed PT model containing 22 places and 30 transitions and 90 arcs in 82 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 12 ms.
Initial state reduction rules removed 1 formulas.
FORMULA MAPK-PT-00080-CTLFireability-06 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 22 out of 22 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 9 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
// Phase 1: matrix 30 rows 22 cols
[2023-03-22 05:45:48] [INFO ] Computed 7 place invariants in 10 ms
[2023-03-22 05:45:48] [INFO ] Implicit Places using invariants in 146 ms returned []
[2023-03-22 05:45:48] [INFO ] Invariant cache hit.
[2023-03-22 05:45:48] [INFO ] Implicit Places using invariants and state equation in 46 ms returned []
Implicit Place search using SMT with State Equation took 218 ms to find 0 implicit places.
[2023-03-22 05:45:48] [INFO ] Invariant cache hit.
[2023-03-22 05:45:48] [INFO ] Dead Transitions using invariants and state equation in 35 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 263 ms. Remains : 22/22 places, 30/30 transitions.
Support contains 22 out of 22 places after structural reductions.
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 19 ms
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 6 ms
[2023-03-22 05:45:49] [INFO ] Input system was already deterministic with 30 transitions.
Incomplete random walk after 10009 steps, including 2 resets, run finished after 84 ms. (steps per millisecond=119 ) properties (out of 41) seen :32
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 48 ms. (steps per millisecond=208 ) properties (out of 9) seen :6
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=384 ) properties (out of 3) seen :2
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=625 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-22 05:45:49] [INFO ] Invariant cache hit.
[2023-03-22 05:45:49] [INFO ] After 25ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0
Fused 1 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 1 atomic propositions for a total of 15 simplifications.
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 4 ms
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 3 ms
[2023-03-22 05:45:49] [INFO ] Input system was already deterministic with 30 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 3 ms
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 2 ms
[2023-03-22 05:45:49] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 2 ms
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 2 ms
[2023-03-22 05:45:49] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 1 place count 22 transition count 30
Applied a total of 1 rules in 6 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 2 ms
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:45:49] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 22 transition count 29
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 20 transition count 29
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 20 transition count 28
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 5 place count 20 transition count 27
Reduce places removed 2 places and 0 transitions.
Graph (trivial) has 3 edges and 18 vertex of which 2 / 18 are part of one of the 1 SCC in 1 ms
Free SCC test removed 1 places
Iterating post reduction 1 with 3 rules applied. Total rules applied 8 place count 17 transition count 27
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 10 place count 17 transition count 25
Applied a total of 10 rules in 6 ms. Remains 17 /22 variables (removed 5) and now considering 25/30 (removed 5) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 17/22 places, 25/30 transitions.
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 2 ms
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:45:49] [INFO ] Input system was already deterministic with 25 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 22 transition count 29
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 20 transition count 29
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 20 transition count 28
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 5 place count 20 transition count 27
Reduce places removed 2 places and 0 transitions.
Graph (trivial) has 3 edges and 18 vertex of which 2 / 18 are part of one of the 1 SCC in 0 ms
Free SCC test removed 1 places
Iterating post reduction 1 with 3 rules applied. Total rules applied 8 place count 17 transition count 27
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 10 place count 17 transition count 25
Partial Post-agglomeration rule applied 2 times.
Drop transitions removed 2 transitions
Iterating global reduction 3 with 2 rules applied. Total rules applied 12 place count 17 transition count 25
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 13 place count 16 transition count 24
Iterating global reduction 3 with 1 rules applied. Total rules applied 14 place count 16 transition count 24
Applied a total of 14 rules in 5 ms. Remains 16 /22 variables (removed 6) and now considering 24/30 (removed 6) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 16/22 places, 24/30 transitions.
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:45:49] [INFO ] Input system was already deterministic with 24 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 22 transition count 29
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 20 transition count 29
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 20 transition count 28
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 5 place count 20 transition count 27
Reduce places removed 2 places and 0 transitions.
Graph (trivial) has 3 edges and 18 vertex of which 2 / 18 are part of one of the 1 SCC in 0 ms
Free SCC test removed 1 places
Iterating post reduction 1 with 3 rules applied. Total rules applied 8 place count 17 transition count 27
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 10 place count 17 transition count 25
Applied a total of 10 rules in 3 ms. Remains 17 /22 variables (removed 5) and now considering 25/30 (removed 5) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 17/22 places, 25/30 transitions.
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:45:49] [INFO ] Input system was already deterministic with 25 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 2 ms
[2023-03-22 05:45:49] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:45:49] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 2 ms
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:45:49] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 2 ms
[2023-03-22 05:45:49] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:45:49] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:45:49] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Partial Post-agglomeration rule applied 2 times.
Drop transitions removed 2 transitions
Iterating global reduction 0 with 2 rules applied. Total rules applied 2 place count 22 transition count 30
Applied a total of 2 rules in 2 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 2 ms
[2023-03-22 05:45:49] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:45:49] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:45:49] [INFO ] Input system was already deterministic with 30 transitions.
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 2 ms
[2023-03-22 05:45:49] [INFO ] Flatten gal took : 3 ms
[2023-03-22 05:45:49] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-22 05:45:49] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 22 places, 30 transitions and 90 arcs took 1 ms.
Total runtime 1286 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT MAPK-PT-00080
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability

FORMULA MAPK-PT-00080-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA MAPK-PT-00080-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA MAPK-PT-00080-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA MAPK-PT-00080-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA MAPK-PT-00080-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA MAPK-PT-00080-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA MAPK-PT-00080-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA MAPK-PT-00080-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA MAPK-PT-00080-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA MAPK-PT-00080-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679464121096

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
++ perl -pe 's/.*\.//g'
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
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MAPK-PT-00080-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
MAPK-PT-00080-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-07: DISJ 0 3 0 0 3 0 0 0
MAPK-PT-00080-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-11: EFEG 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-15: CONJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/200 5/32 MAPK-PT-00080-CTLFireability-01 1226509 m, 245301 m/sec, 9396234 t fired, .

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MAPK-PT-00080-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-07: DISJ 0 3 0 0 3 0 0 0
MAPK-PT-00080-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-11: EFEG 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-15: CONJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/200 10/32 MAPK-PT-00080-CTLFireability-01 2293731 m, 213444 m/sec, 17818378 t fired, .

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MAPK-PT-00080-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-07: DISJ 0 3 0 0 3 0 0 0
MAPK-PT-00080-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-11: EFEG 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-15: CONJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/200 15/32 MAPK-PT-00080-CTLFireability-01 3482290 m, 237711 m/sec, 25817413 t fired, .

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MAPK-PT-00080-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-07: DISJ 0 3 0 0 3 0 0 0
MAPK-PT-00080-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-11: EFEG 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-15: CONJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 20/200 19/32 MAPK-PT-00080-CTLFireability-01 4589815 m, 221505 m/sec, 33233960 t fired, .

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MAPK-PT-00080-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-07: DISJ 0 3 0 0 3 0 0 0
MAPK-PT-00080-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-11: EFEG 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-15: CONJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 25/200 24/32 MAPK-PT-00080-CTLFireability-01 5924917 m, 267020 m/sec, 40043195 t fired, .

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MAPK-PT-00080-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-07: DISJ 0 3 0 0 3 0 0 0
MAPK-PT-00080-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-11: EFEG 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-15: CONJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 30/200 30/32 MAPK-PT-00080-CTLFireability-01 7445808 m, 304178 m/sec, 47236427 t fired, .

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MAPK-PT-00080-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-07: DISJ 0 3 0 0 3 0 0 0
MAPK-PT-00080-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
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MAPK-PT-00080-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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lola: result : true
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lola: fired transitions : 1
lola: time used : 0.000000
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lola: fired transitions : 331
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lola: fired transitions : 712838
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lola: fired transitions : 1684
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MAPK-PT-00080-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
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MAPK-PT-00080-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00080-CTLFireability-07: DISJ 0 1 1 0 4 0 0 0
MAPK-PT-00080-CTLFireability-11: EFEG 0 1 0 0 1 0 0 0
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MAPK-PT-00080-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
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MAPK-PT-00080-CTLFireability-11: EFEG 0 1 0 0 1 0 0 0
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16 AGEF EXCL 20/868 27/32 MAPK-PT-00080-CTLFireability-05 7406653 m, 349148 m/sec, 34157158 t fired, .

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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="MAPK-PT-00080"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is MAPK-PT-00080, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r231-tall-167856416300570"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/MAPK-PT-00080.tgz
mv MAPK-PT-00080 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;